imx8mp-venice-gw702x.dtsi

  1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2/*
  3 * Copyright 2023 Gateworks Corporation
  4 */
  5
  6#include <dt-bindings/gpio/gpio.h>
  7#include <dt-bindings/input/linux-event-codes.h>
  8#include <dt-bindings/leds/common.h>
  9#include <dt-bindings/net/ti-dp83867.h>
 10
 11/ {
 12	aliases {
 13		ethernet0 = &eqos;
 14		rtc0 = &gsc_rtc;
 15		rtc1 = &snvs_rtc;
 16	};
 17
 18	memory@40000000 {
 19		device_type = "memory";
 20		reg = <0x0 0x40000000 0 0x80000000>;
 21	};
 22
 23	gpio-keys {
 24		compatible = "gpio-keys";
 25
 26		key-user-pb {
 27			label = "user_pb";
 28			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
 29			linux,code = <BTN_0>;
 30		};
 31
 32		key-user-pb1x {
 33			label = "user_pb1x";
 34			linux,code = <BTN_1>;
 35			interrupt-parent = <&gsc>;
 36			interrupts = <0>;
 37		};
 38
 39		key-erased {
 40			label = "key_erased";
 41			linux,code = <BTN_2>;
 42			interrupt-parent = <&gsc>;
 43			interrupts = <1>;
 44		};
 45
 46		key-eeprom-wp {
 47			label = "eeprom_wp";
 48			linux,code = <BTN_3>;
 49			interrupt-parent = <&gsc>;
 50			interrupts = <2>;
 51		};
 52
 53		key-tamper {
 54			label = "tamper";
 55			linux,code = <BTN_4>;
 56			interrupt-parent = <&gsc>;
 57			interrupts = <5>;
 58		};
 59
 60		switch-hold {
 61			label = "switch_hold";
 62			linux,code = <BTN_5>;
 63			interrupt-parent = <&gsc>;
 64			interrupts = <7>;
 65		};
 66	};
 67};
 68
 69&A53_0 {
 70	cpu-supply = <&buck3_reg>;
 71};
 72
 73&A53_1 {
 74	cpu-supply = <&buck3_reg>;
 75};
 76
 77&A53_2 {
 78	cpu-supply = <&buck3_reg>;
 79};
 80
 81&A53_3 {
 82	cpu-supply = <&buck3_reg>;
 83};
 84
 85&eqos {
 86	pinctrl-names = "default";
 87	pinctrl-0 = <&pinctrl_eqos>;
 88	phy-mode = "rgmii-id";
 89	phy-handle = <&ethphy0>;
 90	status = "okay";
 91
 92	mdio {
 93		compatible = "snps,dwmac-mdio";
 94		#address-cells = <1>;
 95		#size-cells = <0>;
 96
 97		ethphy0: ethernet-phy@0 {
 98			compatible = "ethernet-phy-ieee802.3-c22";
 99			pinctrl-0 = <&pinctrl_ethphy0>;
100			pinctrl-names = "default";
101			reg = <0x0>;
102			interrupt-parent = <&gpio3>;
103			interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
104			ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
105			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
106			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
107			tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
108			rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
109
110			leds {
111				#address-cells = <1>;
112				#size-cells = <0>;
113
114				led@1 {
115					reg = <1>;
116					color = <LED_COLOR_ID_AMBER>;
117					function = LED_FUNCTION_LAN;
118					default-state = "keep";
119				};
120
121				led@2 {
122					reg = <2>;
123					color = <LED_COLOR_ID_GREEN>;
124					function = LED_FUNCTION_LAN;
125					default-state = "keep";
126				};
127			};
128		};
129	};
130};
131
132&i2c1 {
133	clock-frequency = <100000>;
134	pinctrl-names = "default", "gpio";
135	pinctrl-0 = <&pinctrl_i2c1>;
136	pinctrl-1 = <&pinctrl_i2c1_gpio>;
137	scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
138	sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
139	status = "okay";
140
141	gsc: gsc@20 {
142		compatible = "gw,gsc";
143		reg = <0x20>;
144		pinctrl-0 = <&pinctrl_gsc>;
145		interrupt-parent = <&gpio2>;
146		interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
147		interrupt-controller;
148		#interrupt-cells = <1>;
149		#address-cells = <1>;
150		#size-cells = <0>;
151
152		adc {
153			compatible = "gw,gsc-adc";
154			#address-cells = <1>;
155			#size-cells = <0>;
156
157			channel@6 {
158				gw,mode = <0>;
159				reg = <0x06>;
160				label = "temp";
161			};
162
163			channel@8 {
164				gw,mode = <3>;
165				reg = <0x08>;
166				label = "vdd_bat";
167			};
168
169			channel@16 {
170				gw,mode = <4>;
171				reg = <0x16>;
172				label = "fan_tach";
173			};
174
175			channel@82 {
176				gw,mode = <2>;
177				reg = <0x82>;
178				label = "vdd_vin";
179				gw,voltage-divider-ohms = <22100 1000>;
180			};
181
182			channel@84 {
183				gw,mode = <2>;
184				reg = <0x84>;
185				label = "vdd_adc1";
186				gw,voltage-divider-ohms = <10000 10000>;
187			};
188
189			channel@86 {
190				gw,mode = <2>;
191				reg = <0x86>;
192				label = "vdd_adc2";
193				gw,voltage-divider-ohms = <10000 10000>;
194			};
195
196			channel@88 {
197				gw,mode = <2>;
198				reg = <0x88>;
199				label = "vdd_1p0";
200			};
201
202			channel@8c {
203				gw,mode = <2>;
204				reg = <0x8c>;
205				label = "vdd_1p8";
206			};
207
208			channel@8e {
209				gw,mode = <2>;
210				reg = <0x8e>;
211				label = "vdd_2p5";
212			};
213
214			channel@90 {
215				gw,mode = <2>;
216				reg = <0x90>;
217				label = "vdd_3p3";
218				gw,voltage-divider-ohms = <10000 10000>;
219			};
220
221			channel@92 {
222				gw,mode = <2>;
223				reg = <0x92>;
224				label = "vdd_dram";
225			};
226
227			channel@98 {
228				gw,mode = <2>;
229				reg = <0x98>;
230				label = "vdd_soc";
231			};
232
233			channel@9a {
234				gw,mode = <2>;
235				reg = <0x9a>;
236				label = "vdd_arm";
237			};
238
239			channel@a2 {
240				gw,mode = <2>;
241				reg = <0xa2>;
242				label = "vdd_gsc";
243				gw,voltage-divider-ohms = <10000 10000>;
244			};
245		};
246
247		fan-controller@0 {
248			compatible = "gw,gsc-fan";
249			reg = <0x0a>;
250		};
251	};
252
253	gpio: gpio@23 {
254		compatible = "nxp,pca9555";
255		reg = <0x23>;
256		gpio-controller;
257		#gpio-cells = <2>;
258		interrupt-parent = <&gsc>;
259		interrupts = <4>;
260	};
261
262	eeprom@50 {
263		compatible = "atmel,24c02";
264		reg = <0x50>;
265		pagesize = <16>;
266	};
267
268	eeprom@51 {
269		compatible = "atmel,24c02";
270		reg = <0x51>;
271		pagesize = <16>;
272	};
273
274	eeprom@52 {
275		compatible = "atmel,24c02";
276		reg = <0x52>;
277		pagesize = <16>;
278	};
279
280	eeprom@53 {
281		compatible = "atmel,24c02";
282		reg = <0x53>;
283		pagesize = <16>;
284	};
285
286	gsc_rtc: rtc@68 {
287		compatible = "dallas,ds1672";
288		reg = <0x68>;
289	};
290
291	pmic@69 {
292		compatible = "mps,mp5416";
293		reg = <0x69>;
294
295		regulators {
296			/* vdd_soc */
297			buck1 {
298				regulator-name = "buck1";
299				regulator-min-microvolt = <850000>;
300				regulator-max-microvolt = <1000000>;
301				regulator-always-on;
302				regulator-boot-on;
303			};
304
305			/* vdd_dram */
306			buck2 {
307				regulator-name = "buck2";
308				regulator-min-microvolt = <1100000>;
309				regulator-max-microvolt = <1100000>;
310				regulator-always-on;
311				regulator-boot-on;
312			};
313
314			/* vdd_arm */
315			buck3_reg: buck3 {
316				regulator-name = "buck3";
317				regulator-min-microvolt = <850000>;
318				regulator-max-microvolt = <1000000>;
319				regulator-always-on;
320				regulator-boot-on;
321			};
322
323			/* vdd_1p8 */
324			buck4 {
325				regulator-name = "buck4";
326				regulator-min-microvolt = <1800000>;
327				regulator-max-microvolt = <1800000>;
328				regulator-always-on;
329				regulator-boot-on;
330			};
331
332			/* OUT2: nvcc_snvs_1p8 */
333			ldo1 {
334				regulator-name = "ldo1";
335				regulator-min-microvolt = <1800000>;
336				regulator-max-microvolt = <1800000>;
337				regulator-always-on;
338				regulator-boot-on;
339			};
340
341			/* OUT3: vdd_1p0 */
342			ldo2 {
343				regulator-name = "ldo2";
344				regulator-min-microvolt = <1000000>;
345				regulator-max-microvolt = <1000000>;
346				regulator-always-on;
347				regulator-boot-on;
348			};
349
350			/* OUT4: vdd_2p5 */
351			ldo3 {
352				regulator-name = "ldo3";
353				regulator-min-microvolt = <2500000>;
354				regulator-max-microvolt = <2500000>;
355				regulator-always-on;
356				regulator-boot-on;
357			};
358
359			/* OUT5: vdd_3p3 */
360			ldo4 {
361				regulator-name = "ldo4";
362				regulator-min-microvolt = <3300000>;
363				regulator-max-microvolt = <3300000>;
364				regulator-always-on;
365				regulator-boot-on;
366			};
367		};
368	};
369};
370
371/* off-board header */
372&i2c2 {
373	clock-frequency = <400000>;
374	pinctrl-names = "default", "gpio";
375	pinctrl-0 = <&pinctrl_i2c2>;
376	pinctrl-1 = <&pinctrl_i2c2_gpio>;
377	scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
378	sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
379	status = "okay";
380
381	eeprom@52 {
382		compatible = "atmel,24c32";
383		reg = <0x52>;
384		pagesize = <32>;
385	};
386};
387
388/* off-board header */
389&i2c3 {
390	clock-frequency = <400000>;
391	pinctrl-names = "default", "gpio";
392	pinctrl-0 = <&pinctrl_i2c3>;
393	pinctrl-1 = <&pinctrl_i2c3_gpio>;
394	scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
395	sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
396	status = "okay";
397};
398
399/* console */
400&uart2 {
401	pinctrl-names = "default";
402	pinctrl-0 = <&pinctrl_uart2>;
403	status = "okay";
404};
405
406/* eMMC */
407&usdhc3 {
408	pinctrl-names = "default", "state_100mhz", "state_200mhz";
409	pinctrl-0 = <&pinctrl_usdhc3>;
410	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
411	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
412	assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
413	assigned-clock-rates = <400000000>;
414	bus-width = <8>;
415	non-removable;
416	status = "okay";
417};
418
419&wdog1 {
420	pinctrl-names = "default";
421	pinctrl-0 = <&pinctrl_wdog>;
422	fsl,ext-reset-output;
423	status = "okay";
424};
425
426&iomuxc {
427	pinctrl_eqos: eqosgrp {
428		fsl,pins = <
429			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC			0x2
430			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO			0x2
431			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0		0x90
432			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1		0x90
433			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2		0x90
434			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3		0x90
435			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x90
436			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL		0x90
437			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0		0x16
438			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1		0x16
439			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2		0x16
440			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3		0x16
441			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL		0x16
442			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x0
443		>;
444	};
445
446	pinctrl_ethphy0: ethphy0grp {
447		fsl,pins = <
448			MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14	0x140 /* RST# */
449			MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16	0x150 /* IRQ# */
450		>;
451	};
452
453	pinctrl_gsc: gscgrp {
454		fsl,pins = <
455			MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06	0x150 /* IRQ# */
456		>;
457	};
458
459	pinctrl_i2c1: i2c1grp {
460		fsl,pins = <
461			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL		0x400001c2
462			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA		0x400001c2
463		>;
464	};
465
466	pinctrl_i2c1_gpio: i2c1gpiogrp {
467		fsl,pins = <
468			MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14	0x400001c2
469			MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15	0x400001c2
470		>;
471	};
472
473	pinctrl_i2c2: i2c2grp {
474		fsl,pins = <
475			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL		0x400001c2
476			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA		0x400001c2
477		>;
478	};
479
480	pinctrl_i2c2_gpio: i2c2gpiogrp {
481		fsl,pins = <
482			MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16	0x400001c2
483			MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17	0x400001c2
484		>;
485	};
486
487	pinctrl_i2c3: i2c3grp {
488		fsl,pins = <
489			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL		0x400001c2
490			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA		0x400001c2
491		>;
492	};
493
494	pinctrl_i2c3_gpio: i2c3gpiogrp {
495		fsl,pins = <
496			MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18	0x400001c2
497			MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19	0x400001c2
498		>;
499	};
500
501	pinctrl_uart2: uart2grp {
502		fsl,pins = <
503			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX	0x140
504			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX	0x140
505		>;
506	};
507
508	pinctrl_usdhc3: usdhc3grp {
509		fsl,pins = <
510			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x190
511			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d0
512			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d0
513			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d0
514			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d0
515			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d0
516			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d0
517			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d0
518			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d0
519			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d0
520			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x190
521		>;
522	};
523
524	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
525		fsl,pins = <
526			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x194
527			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d4
528			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d4
529			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d4
530			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d4
531			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d4
532			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d4
533			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d4
534			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d4
535			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d4
536			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x194
537		>;
538	};
539
540	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
541		fsl,pins = <
542			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x196
543			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d6
544			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d6
545			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d6
546			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d6
547			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d6
548			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d6
549			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d6
550			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d6
551			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d6
552			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x196
553		>;
554	};
555
556	pinctrl_wdog: wdoggrp {
557		fsl,pins = <
558			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B	0x166
559		>;
560	};
561};