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imx8mp-tx8p-ml81.dtsi
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linux-6.19.14/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81.dtsi
1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2020 Lothar Waßmann <LW@KARO-electronics.de> 4 * 2025 Maud Spierings <maudspierings@gocontroll.com> 5 */ 6 7#include "imx8mp.dtsi" 8 9/ { 10 /* PHY regulator */ 11 regulator-3v3-etn { 12 compatible = "regulator-fixed"; 13 gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; 14 enable-active-high; 15 pinctrl-0 = <&pinctrl_reg_3v3_etn>; 16 pinctrl-names = "default"; 17 regulator-always-on; 18 regulator-boot-on; 19 regulator-max-microvolt = <3300000>; 20 regulator-min-microvolt = <3300000>; 21 regulator-name = "3v3-etn"; 22 vin-supply = <®_vdd_3v3>; 23 }; 24}; 25 26&A53_0 { 27 cpu-supply = <®_vdd_arm>; 28}; 29 30&A53_1 { 31 cpu-supply = <®_vdd_arm>; 32}; 33 34&A53_2 { 35 cpu-supply = <®_vdd_arm>; 36}; 37 38&A53_3 { 39 cpu-supply = <®_vdd_arm>; 40}; 41 42&eqos { 43 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>, 44 <&clk IMX8MP_CLK_ENET_QOS_TIMER>, 45 <&clk IMX8MP_CLK_ENET_QOS>; 46 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, 47 <&clk IMX8MP_SYS_PLL2_100M>, 48 <&clk IMX8MP_SYS_PLL2_50M>; 49 assigned-clock-rates = <266000000>, <100000000>, <50000000>; 50 nvmem-cells = <ð_mac1>; 51 phy-handle = <ðphy0>; 52 phy-mode = "rmii"; 53 pinctrl-0 = <&pinctrl_eqos>; 54 pinctrl-1 = <&pinctrl_eqos_sleep>; 55 pinctrl-names = "default", "sleep"; 56 status = "okay"; 57 58 mdio { 59 compatible = "snps,dwmac-mdio"; 60 #address-cells = <1>; 61 #size-cells = <0>; 62 pinctrl-0 = <&pinctrl_ethphy_rst_b>; 63 pinctrl-names = "default"; 64 reset-delay-us = <25000>; 65 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; 66 67 ethphy0: ethernet-phy@0 { 68 reg = <0>; 69 interrupt-parent = <&gpio4>; 70 interrupts = <21 IRQ_TYPE_EDGE_FALLING>; 71 clocks = <&clk IMX8MP_CLK_ENET_QOS>; 72 pinctrl-0 = <&pinctrl_ethphy_int_b>; 73 pinctrl-names = "default"; 74 smsc,disable-energy-detect; 75 }; 76 }; 77}; 78 79&fec { 80 nvmem-cells = <ð_mac2>; 81}; 82 83&gpio1 { 84 gpio-line-names = "SODIMM_152", 85 "SODIMM_42", 86 "PMIC_WDOG_B SODIMM_153", 87 "PMIC_IRQ_B", 88 "SODIMM_154", 89 "SODIMM_155", 90 "SODIMM_156", 91 "SODIMM_157", 92 "SODIMM_158", 93 "SODIMM_159", 94 "SODIMM_161", 95 "SODIMM_162", 96 "SODIMM_34", 97 "SODIMM_36", 98 "SODIMM_27", 99 "SODIMM_28", 100 "ENET_MDC", 101 "ENET_MDIO", 102 "", 103 "ENET_XTAL1/CLKIN", 104 "ENET_TXD1", 105 "ENET_TXD0", 106 "ENET_TXEN", 107 "ENET_POWER", 108 "ENET_COL/CRS_DV", 109 "ENET_RXER", 110 "ENET_RXD0", 111 "ENET_RXD1", 112 "", 113 "", 114 "", 115 ""; 116}; 117 118&gpio2 { 119 gpio-line-names = "", 120 "", 121 "", 122 "", 123 "", 124 "", 125 "", 126 "", 127 "", 128 "", 129 "", 130 "", 131 "SODIMM_51", 132 "SODIMM_57", 133 "SODIMM_56", 134 "SODIMM_52", 135 "SODIMM_53", 136 "SODIMM_54", 137 "SODIMM_55", 138 "SODIMM_15", 139 "", 140 "", 141 "", 142 "", 143 "", 144 "", 145 "", 146 "", 147 "", 148 "", 149 "", 150 ""; 151}; 152 153&gpio3 { 154 gpio-line-names = "", 155 "", 156 "EMMC_DS", 157 "EMMC_DAT5", 158 "EMMC_DAT6", 159 "EMMC_DAT7", 160 "", 161 "", 162 "", 163 "", 164 "EMMC_DAT0", 165 "EMMC_DAT1", 166 "EMMC_DAT2", 167 "EMMC_DAT3", 168 "", 169 "EMMC_DAT4", 170 "", 171 "EMMC_CLK", 172 "EMMC_CMD", 173 "SODIMM_75", 174 "SODIMM_145", 175 "SODIMM_163", 176 "SODIMM_164", 177 "SODIMM_165", 178 "SODIMM_143", 179 "SODIMM_144", 180 "SODIMM_72", 181 "SODIMM_73", 182 "SODIMM_74", 183 "SODIMM_93", 184 "", 185 ""; 186}; 187 188&gpio4 { 189 gpio-line-names = "SODIMM_98", 190 "SODIMM_99", 191 "SODIMM_100", 192 "SODIMM_101", 193 "SODIMM_45", 194 "SODIMM_43", 195 "SODIMM_105", 196 "SODIMM_106", 197 "SODIMM_107", 198 "SODIMM_108", 199 "SODIMM_104", 200 "SODIMM_103", 201 "SODIMM_115", 202 "SODIMM_114", 203 "SODIMM_113", 204 "SODIMM_112", 205 "SODIMM_109", 206 "SODIMM_110", 207 "SODIMM_95", 208 "SODIMM_96", 209 "SODIMM_97", 210 "ENET_nINT", 211 "ENET_nRST", 212 "SODIMM_84", 213 "SODIMM_87", 214 "SODIMM_86", 215 "SODIMM_85", 216 "SODIMM_83", 217 "", 218 "SODIMM_66", 219 "SODIMM_65", 220 ""; 221}; 222 223&gpio5 { 224 gpio-line-names = "", 225 "", 226 "", 227 "SODIMM_76", 228 "SODIMM_81", 229 "SODIMM_146", 230 "SODIMM_48", 231 "SODIMM_46", 232 "SODIMM_47", 233 "SODIMM_44", 234 "SODIMM_49", 235 "", 236 "SODIMM_70", 237 "SODIMM_69", 238 "PMIC_SCL", 239 "PMIC_SDA", 240 "SODIMM_41", 241 "SODIMM_40", 242 "SODIMM_148", 243 "SODIMM_149", 244 "SODIMM_150", 245 "SODIMM_151", 246 "SODIMM_60", 247 "SODIMM_59", 248 "SODIMM_64", 249 "SODIMM_63", 250 "SODIMM_62", 251 "SODIMM_61", 252 "SODIMM_68", 253 "SODIMM_67", 254 "", 255 ""; 256}; 257 258&i2c1 { 259 clock-frequency = <400000>; 260 pinctrl-0 = <&pinctrl_i2c1>; 261 pinctrl-1 = <&pinctrl_i2c1_gpio>; 262 pinctrl-names = "default", "gpio"; 263 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 264 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 265 status = "okay"; 266 267 pmic@25 { 268 compatible = "nxp,pca9450c"; 269 reg = <0x25>; 270 interrupt-parent = <&gpio1>; 271 interrupts = <3 IRQ_TYPE_EDGE_FALLING>; 272 pinctrl-0 = <&pinctrl_pmic>; 273 pinctrl-names = "default"; 274 275 regulators { 276 reg_vdd_soc: BUCK1 { 277 regulator-always-on; 278 regulator-boot-on; 279 regulator-max-microvolt = <900000>; 280 regulator-min-microvolt = <805000>; 281 regulator-name = "vdd-soc"; 282 regulator-ramp-delay = <3125>; 283 }; 284 285 reg_vdd_arm: BUCK2 { 286 regulator-always-on; 287 regulator-boot-on; 288 regulator-max-microvolt = <950000>; 289 regulator-min-microvolt = <805000>; 290 regulator-name = "vdd-core"; 291 regulator-ramp-delay = <3125>; 292 nxp,dvs-run-voltage = <950000>; 293 nxp,dvs-standby-voltage = <850000>; 294 }; 295 296 reg_vdd_3v3: BUCK4 { 297 regulator-always-on; 298 regulator-boot-on; 299 regulator-max-microvolt = <3300000>; 300 regulator-min-microvolt = <3300000>; 301 regulator-name = "3v3"; 302 }; 303 304 reg_nvcc_nand: BUCK5 { 305 regulator-always-on; 306 regulator-boot-on; 307 regulator-max-microvolt = <1800000>; 308 regulator-min-microvolt = <1800000>; 309 regulator-name = "nvcc-nand"; 310 }; 311 312 reg_nvcc_dram: BUCK6 { 313 regulator-always-on; 314 regulator-boot-on; 315 regulator-max-microvolt = <1100000>; 316 regulator-min-microvolt = <1100000>; 317 regulator-name = "nvcc-dram"; 318 }; 319 320 reg_snvs_1v8: LDO1 { 321 regulator-always-on; 322 regulator-boot-on; 323 regulator-max-microvolt = <1800000>; 324 regulator-min-microvolt = <1800000>; 325 regulator-name = "snvs-1v8"; 326 }; 327 328 ldo2_reg: LDO2 { 329 regulator-always-on; 330 regulator-max-microvolt = <1150000>; 331 regulator-min-microvolt = <800000>; 332 regulator-name = "LDO2"; 333 }; 334 335 reg_vdda_1v8: LDO3 { 336 regulator-always-on; 337 regulator-boot-on; 338 regulator-max-microvolt = <1800000>; 339 regulator-min-microvolt = <1800000>; 340 regulator-name = "vdda-1v8"; 341 }; 342 343 ldo4_reg: LDO4 { 344 regulator-max-microvolt = <3300000>; 345 regulator-min-microvolt = <800000>; 346 regulator-name = "LDO4"; 347 }; 348 349 ldo5_reg: LDO5 { 350 regulator-always-on; 351 regulator-boot-on; 352 regulator-max-microvolt = <3300000>; 353 regulator-min-microvolt = <1800000>; 354 regulator-name = "LDO5"; 355 }; 356 }; 357 }; 358}; 359 360&iomuxc { 361 pinctrl_eqos: eqosgrp { 362 fsl,pins = < 363 MX8MP_IOMUXC_ENET_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK 364 (MX8MP_DSE_X4 | MX8MP_PULL_UP | MX8MP_PULL_ENABLE | MX8MP_SION) 365 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 366 (MX8MP_DSE_X4 | MX8MP_PULL_UP | MX8MP_PULL_ENABLE) 367 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 368 (MX8MP_DSE_X4 | MX8MP_PULL_UP | MX8MP_PULL_ENABLE) 369 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 370 (MX8MP_DSE_X6 | MX8MP_FSEL_FAST) 371 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 372 (MX8MP_DSE_X6 | MX8MP_FSEL_FAST) 373 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 374 (MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_PULL_ENABLE) 375 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 376 (MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_PULL_ENABLE) 377 MX8MP_IOMUXC_ENET_RXC__ENET_QOS_RX_ER 378 (MX8MP_FSEL_FAST | MX8MP_PULL_ENABLE) 379 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 380 (MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_ENABLE) 381 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 382 (MX8MP_DSE_X6 | MX8MP_FSEL_FAST) 383 >; 384 }; 385 386 pinctrl_eqos_sleep: eqos-sleep-grp { 387 fsl,pins = < 388 MX8MP_IOMUXC_ENET_TD2__GPIO1_IO19 389 (MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE) 390 MX8MP_IOMUXC_ENET_MDC__GPIO1_IO16 391 (MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE) 392 MX8MP_IOMUXC_ENET_MDIO__GPIO1_IO17 393 (MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE) 394 MX8MP_IOMUXC_ENET_TD0__GPIO1_IO21 395 (MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE) 396 MX8MP_IOMUXC_ENET_TD1__GPIO1_IO20 397 (MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE) 398 MX8MP_IOMUXC_ENET_RD0__GPIO1_IO26 399 (MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE) 400 MX8MP_IOMUXC_ENET_RD1__GPIO1_IO27 401 (MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE) 402 MX8MP_IOMUXC_ENET_RXC__GPIO1_IO25 403 (MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE) 404 MX8MP_IOMUXC_ENET_RX_CTL__GPIO1_IO24 405 (MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE) 406 MX8MP_IOMUXC_ENET_TX_CTL__GPIO1_IO22 407 (MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE) 408 >; 409 }; 410 411 pinctrl_ethphy_int_b: ethphy-int-bgrp { 412 fsl,pins = < 413 MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 414 (MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT) 415 >; 416 }; 417 418 pinctrl_ethphy_rst_b: ethphy-rst-bgrp { 419 fsl,pins = < 420 MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 421 (MX8MP_PULL_UP | MX8MP_PULL_ENABLE) 422 >; 423 }; 424 425 pinctrl_i2c1: i2c1grp { 426 fsl,pins = < 427 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 428 MX8MP_I2C_DEFAULT 429 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 430 MX8MP_I2C_DEFAULT 431 >; 432 }; 433 434 pinctrl_i2c1_gpio: i2c1-gpiogrp { 435 fsl,pins = < 436 MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 437 MX8MP_I2C_DEFAULT 438 MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 439 MX8MP_I2C_DEFAULT 440 >; 441 }; 442 443 pinctrl_pmic: pmicgrp { 444 fsl,pins = < 445 MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 446 (MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE) 447 >; 448 }; 449 450 pinctrl_reg_3v3_etn: reg-3v3-etngrp { 451 fsl,pins = < 452 MX8MP_IOMUXC_ENET_TXC__GPIO1_IO23 453 (MX8MP_PULL_UP | MX8MP_PULL_ENABLE) 454 >; 455 }; 456 457 pinctrl_usdhc3: usdhc3grp { 458 fsl,pins = < 459 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 460 (MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE) 461 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 462 MX8MP_USDHC_DATA_DEFAULT 463 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 464 MX8MP_USDHC_DATA_DEFAULT 465 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 466 MX8MP_USDHC_DATA_DEFAULT 467 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 468 MX8MP_USDHC_DATA_DEFAULT 469 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 470 MX8MP_USDHC_DATA_DEFAULT 471 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 472 MX8MP_USDHC_DATA_DEFAULT 473 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 474 MX8MP_USDHC_DATA_DEFAULT 475 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 476 MX8MP_USDHC_DATA_DEFAULT 477 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 478 MX8MP_USDHC_DATA_DEFAULT 479 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 480 (MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE) 481 >; 482 }; 483 484 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 485 fsl,pins = < 486 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 487 (MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE) 488 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 489 (MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT) 490 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 491 (MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT) 492 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 493 (MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT) 494 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 495 (MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT) 496 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 497 (MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT) 498 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 499 (MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT) 500 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 501 (MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT) 502 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 503 (MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT) 504 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 505 (MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT) 506 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 507 (MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE) 508 >; 509 }; 510 511 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 512 fsl,pins = < 513 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 514 (MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE) 515 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 516 (MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT) 517 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 518 (MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT) 519 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 520 (MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT) 521 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 522 (MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT) 523 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 524 (MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT) 525 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 526 (MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT) 527 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 528 (MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT) 529 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 530 (MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT) 531 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 532 (MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT) 533 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 534 (MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE) 535 >; 536 }; 537}; 538 539&usdhc3 { 540 assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; 541 assigned-clock-rates = <200000000>; 542 bus-width = <8>; 543 max-frequency = <200000000>; 544 non-removable; 545 pinctrl-0 = <&pinctrl_usdhc3>; 546 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 547 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 548 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 549 vmmc-supply = <®_vdd_3v3>; 550 voltage-ranges = <3300 3300>; 551 vqmmc-supply = <®_nvcc_nand>; 552 status = "okay"; 553};
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