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imx8mp-toradex-smarc.dtsi
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linux-6.19.14/arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc.dtsi
1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2/* Copyright (C) 2025 Toradex */ 3 4#include <dt-bindings/phy/phy-imx8-pcie.h> 5#include <dt-bindings/net/ti-dp83867.h> 6#include "imx8mp.dtsi" 7 8/ { 9 aliases { 10 can0 = &flexcan2; 11 can1 = &flexcan1; 12 ethernet0 = &eqos; 13 ethernet1 = &fec; 14 mmc0 = &usdhc3; 15 mmc1 = &usdhc2; 16 mmc2 = &usdhc1; 17 rtc0 = &rtc_i2c; 18 rtc1 = &snvs_rtc; 19 serial0 = &uart1; 20 serial1 = &uart4; 21 serial2 = &uart2; 22 serial3 = &uart3; 23 }; 24 25 chosen { 26 stdout-path = &uart4; 27 }; 28 29 connector { 30 compatible = "gpio-usb-b-connector", "usb-b-connector"; 31 pinctrl-names = "default"; 32 pinctrl-0 = <&pinctrl_usb0_id>; 33 id-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; 34 label = "USB0"; 35 self-powered; 36 type = "micro"; 37 vbus-supply = <®_usb0_vbus>; 38 39 port { 40 usb_dr_connector: endpoint { 41 remote-endpoint = <&usb3_0_dwc>; 42 }; 43 }; 44 }; 45 46 gpio-keys { 47 compatible = "gpio-keys"; 48 pinctrl-names = "default"; 49 pinctrl-0 = <&pinctrl_sleep>; 50 51 smarc_key_sleep: key-sleep { 52 gpios = <&gpio3 1 GPIO_ACTIVE_LOW>; 53 label = "SMARC_SLEEP#"; 54 wakeup-source; 55 linux,code = <KEY_SLEEP>; 56 }; 57 58 smarc_switch_lid: switch-lid { 59 gpios = <&som_ec_gpio_expander 2 GPIO_ACTIVE_LOW>; 60 label = "SMARC_LID#"; 61 linux,code = <SW_LID>; 62 linux,input-type = <EV_SW>; 63 }; 64 }; 65 66 reg_usb0_vbus: regulator-usb0-vbus { 67 compatible = "regulator-fixed"; 68 pinctrl-names = "default"; 69 pinctrl-0 = <&pinctrl_usb0_en_oc>; 70 gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; 71 enable-active-high; 72 regulator-name = "USB0_EN_OC#"; 73 }; 74 75 reg_usb1_vbus: regulator-usb1-vbus { 76 compatible = "regulator-fixed"; 77 pinctrl-names = "default"; 78 pinctrl-0 = <&pinctrl_usb1_en_oc>; 79 gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; 80 enable-active-high; 81 regulator-name = "USB2_EN_OC#"; 82 }; 83 84 reg_usdhc2_vmmc: regulator-usdhc2-vmmc { 85 compatible = "regulator-fixed"; 86 pinctrl-names = "default"; 87 pinctrl-0 = <&pinctrl_usdhc2_pwr_en>; 88 gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; 89 enable-active-high; 90 off-on-delay-us = <100000>; 91 regulator-max-microvolt = <3300000>; 92 regulator-min-microvolt = <3300000>; 93 regulator-name = "3V3_SD"; 94 startup-delay-us = <20000>; 95 }; 96 97 reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc { 98 compatible = "regulator-gpio"; 99 pinctrl-names = "default"; 100 pinctrl-0 = <&pinctrl_usdhc2_vsel>; 101 gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; 102 regulator-max-microvolt = <3300000>; 103 regulator-min-microvolt = <1800000>; 104 states = <1800000 0x1>, 105 <3300000 0x0>; 106 regulator-name = "PMIC_USDHC_VSELECT"; 107 vin-supply = <®_sd_3v3_1v8>; 108 }; 109 110 reg_wifi_en: regulator-wifi-en { 111 compatible = "regulator-fixed"; 112 pinctrl-names = "default"; 113 pinctrl-0 = <&pinctrl_wifi_pwr_en>; 114 gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; 115 enable-active-high; 116 regulator-max-microvolt = <3300000>; 117 regulator-min-microvolt = <3300000>; 118 regulator-name = "CTRL_EN_WIFI"; 119 startup-delay-us = <2000>; 120 }; 121 122 reserved-memory { 123 linux,cma { 124 size = <0 0x20000000>; 125 alloc-ranges = <0 0x40000000 0 0x80000000>; 126 }; 127 }; 128 129 sound_hdmi: sound-hdmi { 130 compatible = "fsl,imx-audio-hdmi"; 131 model = "audio-hdmi"; 132 audio-cpu = <&aud2htx>; 133 hdmi-out; 134 status = "disabled"; 135 }; 136}; 137 138&A53_0 { 139 cpu-supply = <®_vdd_arm>; 140}; 141 142&A53_1 { 143 cpu-supply = <®_vdd_arm>; 144}; 145 146&A53_2 { 147 cpu-supply = <®_vdd_arm>; 148}; 149 150&A53_3 { 151 cpu-supply = <®_vdd_arm>; 152}; 153 154/* SMARC SPI0 */ 155&ecspi1 { 156 pinctrl-names = "default"; 157 pinctrl-0 = <&pinctrl_ecspi1>; 158 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>, <&gpio4 28 GPIO_ACTIVE_LOW>; 159}; 160 161/* SMARC SPI1 */ 162&ecspi2 { 163 pinctrl-names = "default"; 164 pinctrl-0 = <&pinctrl_ecspi2>, <&pinctrl_tpm_cs>; 165 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, 166 <&gpio4 3 GPIO_ACTIVE_LOW>, 167 <&gpio3 6 GPIO_ACTIVE_LOW>; 168 status = "okay"; 169 170 tpm@2 { 171 compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; 172 reg = <2>; 173 spi-max-frequency = <18500000>; 174 }; 175}; 176 177/* SMARC GBE0 */ 178&eqos { 179 pinctrl-names = "default"; 180 pinctrl-0 = <&pinctrl_eqos>, 181 <&pinctrl_eth_mdio>, 182 <&pinctrl_eqos_1588_event>; 183 phy-handle = <&eqos_phy>; 184 phy-mode = "rgmii-id"; 185 snps,force_thresh_dma_mode; 186 snps,mtl-rx-config = <&mtl_rx_setup>; 187 snps,mtl-tx-config = <&mtl_tx_setup>; 188 189 mdio: mdio { 190 compatible = "snps,dwmac-mdio"; 191 #address-cells = <1>; 192 #size-cells = <0>; 193 }; 194 195 mtl_rx_setup: rx-queues-config { 196 snps,rx-queues-to-use = <5>; 197 198 queue0 { 199 snps,dcb-algorithm; 200 snps,priority = <0x1>; 201 snps,map-to-dma-channel = <0>; 202 }; 203 204 queue1 { 205 snps,dcb-algorithm; 206 snps,priority = <0x2>; 207 snps,map-to-dma-channel = <1>; 208 }; 209 210 queue2 { 211 snps,dcb-algorithm; 212 snps,priority = <0x4>; 213 snps,map-to-dma-channel = <2>; 214 }; 215 216 queue3 { 217 snps,dcb-algorithm; 218 snps,priority = <0x8>; 219 snps,map-to-dma-channel = <3>; 220 }; 221 222 queue4 { 223 snps,dcb-algorithm; 224 snps,priority = <0xf0>; 225 snps,map-to-dma-channel = <4>; 226 }; 227 }; 228 229 mtl_tx_setup: tx-queues-config { 230 snps,tx-queues-to-use = <5>; 231 232 queue0 { 233 snps,dcb-algorithm; 234 snps,priority = <0x1>; 235 }; 236 237 queue1 { 238 snps,dcb-algorithm; 239 snps,priority = <0x2>; 240 }; 241 242 queue2 { 243 snps,dcb-algorithm; 244 snps,priority = <0x4>; 245 }; 246 247 queue3 { 248 snps,dcb-algorithm; 249 snps,priority = <0x8>; 250 }; 251 252 queue4 { 253 snps,dcb-algorithm; 254 snps,priority = <0xf0>; 255 }; 256 }; 257}; 258 259/* SMARC GBE1 */ 260&fec { 261 pinctrl-names = "default"; 262 pinctrl-0 = <&pinctrl_fec>, <&pinctrl_fec_1588_event>; 263 phy-handle = <&fec_phy>; 264 phy-mode = "rgmii-id"; 265 fsl,magic-packet; 266}; 267 268/* SMARC CAN1 */ 269&flexcan1 { 270 pinctrl-names = "default"; 271 pinctrl-0 = <&pinctrl_flexcan1>; 272}; 273 274/* SMARC CAN0 */ 275&flexcan2 { 276 pinctrl-names = "default"; 277 pinctrl-0 = <&pinctrl_flexcan2>; 278}; 279 280&gpio1 { 281 gpio-line-names = "SMARC_GPIO7", /* 0 */ 282 "SMARC_GPIO8", 283 "", 284 "PMIC_INT#", 285 "PMIC_USDHC_VSELECT", 286 "SMARC_GPIO9", 287 "SMARC_GPIO10", 288 "SMARC_GPIO11", 289 "SMARC_GPIO12", 290 "", 291 "SMARC_GPIO5", /* 10 */ 292 "", 293 "SMARC_USB0_EN_OC#", 294 "SMARC_GPIO13", 295 "SMARC_USB2_EN_OC#"; 296}; 297 298&gpio2 { 299 gpio-line-names = "", /* 0 */ 300 "", 301 "", 302 "", 303 "", 304 "", 305 "", 306 "", 307 "", 308 "", 309 "", /* 10 */ 310 "", 311 "SMARC_SDIO_CD#", 312 "", 313 "", 314 "", 315 "", 316 "", 317 "", 318 "SMARC_SDIO_PWR_EN", 319 "SMARC_SDIO_WP"; /* 20 */ 320}; 321 322&gpio3 { 323 pinctrl-names = "default"; 324 pinctrl-0 = <&pinctrl_lvds_dsi_sel>; 325 gpio-line-names = "ETH_0_INT#", /* 0 */ 326 "SLEEP#", 327 "", 328 "", 329 "", 330 "", 331 "TPM_CS#", 332 "LVDS_DSI_SEL", 333 "MCU_INT#", 334 "GPIO_EX_INT#", 335 "", /* 10 */ 336 "", 337 "", 338 "", 339 "", 340 "", 341 "SMARC_SMB_ALERT#", 342 "", 343 "", 344 "", 345 "SMARC_I2C_PM_DAT", /* 20 */ 346 "", 347 "", 348 "", 349 "", 350 "", 351 "", 352 "", 353 "SMARC_I2C_PM_CK"; 354}; 355 356&gpio4 { 357 gpio-line-names = "SMARC_PCIE_WAKE#", /* 0 */ 358 "", 359 "", 360 "SMARC_SPI1_CS1#", 361 "", 362 "", 363 "", 364 "", 365 "", 366 "", 367 "", /* 10 */ 368 "", 369 "", 370 "", 371 "", 372 "", 373 "", 374 "", 375 "SMARC_GPIO4", 376 "SMARC_PCIE_A_RST#", 377 "", /* 20 */ 378 "", 379 "", 380 "", 381 "", 382 "", 383 "", 384 "", 385 "SMARC_SPI0_CS1#", 386 "SMARC_GPIO6"; 387}; 388 389&gpio5 { 390 gpio-line-names = "", /* 0 */ 391 "", 392 "SMARC_USB0_OTG_ID", 393 "SMARC_I2C_CAM1_CK", 394 "SMARC_I2C_CAM1_DAT", 395 "", 396 "", 397 "", 398 "", 399 "SMARC_SPI0_CS0#", 400 "", /* 10 */ 401 "", 402 "", 403 "SMARC_SPI1_CS0#", 404 "CTRL_I2C_SCL", 405 "CTRL_I2C_SDA", 406 "SMARC_I2C_LCD_CK", 407 "SMARC_I2C_LCD_DAT", 408 "SMARC_I2C_CAM0_CK", 409 "SMARC_I2C_CAM0_DAT", 410 "SMARC_I2C_GP_CK", /* 20 */ 411 "SMARC_I2C_GP_DAT"; 412}; 413 414/* SMARC HDMI */ 415&hdmi_tx { 416 pinctrl-names = "default"; 417 pinctrl-0 = <&pinctrl_hdmi>; 418}; 419 420/* On-module I2C */ 421&i2c1 { 422 pinctrl-names = "default", "gpio"; 423 pinctrl-0 = <&pinctrl_i2c1>; 424 pinctrl-1 = <&pinctrl_i2c1_gpio>; 425 clock-frequency = <400000>; 426 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 427 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 428 single-master; 429 status = "okay"; 430 431 som_gpio_expander: gpio@21 { 432 compatible = "nxp,pcal6408"; 433 reg = <0x21>; 434 pinctrl-names = "default"; 435 pinctrl-0 = <&pinctrl_pcal6408>; 436 #interrupt-cells = <2>; 437 interrupt-controller; 438 interrupt-parent = <&gpio3>; 439 interrupts = <9 IRQ_TYPE_LEVEL_LOW>; 440 #gpio-cells = <2>; 441 gpio-controller; 442 gpio-line-names = 443 "SMARC_GPIO0", 444 "SMARC_GPIO1", 445 "SMARC_GPIO2", 446 "SMARC_GPIO3", 447 "SMARC_LCD0_VDD_EN", 448 "SMARC_LCD0_BKLT_EN", 449 "SMARC_LCD1_VDD_EN", 450 "SMARC_LCD1_BKLT_EN"; 451 }; 452 453 pca9450: pmic@25 { 454 compatible = "nxp,pca9450c"; 455 reg = <0x25>; 456 pinctrl-names = "default"; 457 pinctrl-0 = <&pinctrl_pmic>; 458 interrupt-parent = <&gpio1>; 459 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 460 461 regulators { 462 BUCK1 { 463 regulator-always-on; 464 regulator-boot-on; 465 regulator-max-microvolt = <1000000>; 466 regulator-min-microvolt = <805000>; 467 regulator-name = "+VDD_SOC (PMIC BUCK1)"; 468 regulator-ramp-delay = <3125>; 469 }; 470 471 reg_vdd_arm: BUCK2 { 472 regulator-always-on; 473 regulator-boot-on; 474 regulator-max-microvolt = <1000000>; 475 regulator-min-microvolt = <805000>; 476 regulator-name = "+VDD_ARM (PMIC BUCK2)"; 477 regulator-ramp-delay = <3125>; 478 nxp,dvs-run-voltage = <950000>; 479 nxp,dvs-standby-voltage = <850000>; 480 }; 481 482 reg_3v3: BUCK4 { 483 regulator-always-on; 484 regulator-boot-on; 485 regulator-max-microvolt = <3300000>; 486 regulator-min-microvolt = <3300000>; 487 regulator-name = "+V3.3 (PMIC BUCK4)"; 488 }; 489 490 reg_1v8: BUCK5 { 491 regulator-always-on; 492 regulator-boot-on; 493 regulator-max-microvolt = <1800000>; 494 regulator-min-microvolt = <1800000>; 495 regulator-name = "+V1.8 (PMIC BUCK5)"; 496 }; 497 498 BUCK6 { 499 regulator-always-on; 500 regulator-boot-on; 501 regulator-max-microvolt = <1155000>; 502 regulator-min-microvolt = <1045000>; 503 regulator-name = "+VDD_DDR (PMIC BUCK6)"; 504 }; 505 506 LDO1 { 507 regulator-always-on; 508 regulator-boot-on; 509 regulator-max-microvolt = <1950000>; 510 regulator-min-microvolt = <1710000>; 511 regulator-name = "+V1.8_SNVS (PMIC LDO1)"; 512 }; 513 514 LDO3 { 515 regulator-always-on; 516 regulator-boot-on; 517 regulator-max-microvolt = <1800000>; 518 regulator-min-microvolt = <1800000>; 519 regulator-name = "+V1.8A (PMIC LDO3)"; 520 }; 521 522 LDO4 { 523 regulator-always-on; 524 regulator-boot-on; 525 regulator-max-microvolt = <3300000>; 526 regulator-min-microvolt = <3300000>; 527 regulator-name = "+V3.3_ADC (PMIC LDO4)"; 528 }; 529 530 reg_sd_3v3_1v8: LDO5 { 531 regulator-max-microvolt = <3300000>; 532 regulator-min-microvolt = <1800000>; 533 regulator-name = "+V3.3_1.8_SD (PMIC LDO5)"; 534 }; 535 }; 536 }; 537 538 embedded-controller@28 { 539 compatible = "toradex,smarc-imx8mp-ec", "toradex,smarc-ec"; 540 reg = <0x28>; 541 }; 542 543 som_ec_gpio_expander: gpio@29 { 544 compatible = "toradex,ecgpiol16", "nxp,pcal6416"; 545 reg = <0x29>; 546 pinctrl-names = "default"; 547 pinctrl-0 = <&pinctrl_mcu_int>; 548 #interrupt-cells = <2>; 549 interrupt-controller; 550 interrupt-parent = <&gpio3>; 551 interrupts = <8 IRQ_TYPE_LEVEL_LOW>; 552 #gpio-cells = <2>; 553 gpio-controller; 554 gpio-line-names = 555 "SMARC_CHARGER_PRSNT#", 556 "SMARC_CHARGING#", 557 "SMARC_LID#", 558 "SMARC_BATLOW#"; 559 }; 560 561 rtc_i2c: rtc@32 { 562 compatible = "epson,rx8130"; 563 reg = <0x32>; 564 }; 565 566 temperature-sensor@48 { 567 compatible = "ti,tmp1075"; 568 reg = <0x48>; 569 }; 570 571 eeprom@50 { 572 compatible = "st,24c02", "atmel,24c02"; 573 reg = <0x50>; 574 pagesize = <16>; 575 }; 576}; 577 578/* SMARC I2C_LCD */ 579&i2c2 { 580 pinctrl-names = "default", "gpio"; 581 pinctrl-0 = <&pinctrl_i2c2>; 582 pinctrl-1 = <&pinctrl_i2c2_gpio>; 583 clock-frequency = <100000>; 584 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 585 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 586 single-master; 587}; 588 589/* SMARC I2C_CAM0 */ 590&i2c3 { 591 pinctrl-names = "default", "gpio"; 592 pinctrl-0 = <&pinctrl_i2c3>; 593 pinctrl-1 = <&pinctrl_i2c3_gpio>; 594 clock-frequency = <400000>; 595 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 596 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 597 single-master; 598}; 599 600/* SMARC I2C_GP */ 601&i2c4 { 602 pinctrl-names = "default", "gpio"; 603 pinctrl-0 = <&pinctrl_i2c4>; 604 pinctrl-1 = <&pinctrl_i2c4_gpio>; 605 clock-frequency = <400000>; 606 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 607 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 608 single-master; 609 status = "okay"; 610 611 eeprom@50 { 612 compatible = "st,24c32", "atmel,24c32"; 613 reg = <0x50>; 614 pagesize = <32>; 615 }; 616}; 617 618/* SMARC I2C_CAM1 */ 619&i2c5 { 620 pinctrl-names = "default", "gpio"; 621 pinctrl-0 = <&pinctrl_i2c5>; 622 pinctrl-1 = <&pinctrl_i2c5_gpio>; 623 clock-frequency = <400000>; 624 scl-gpios = <&gpio5 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 625 sda-gpios = <&gpio5 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 626 single-master; 627}; 628 629/* SMARC I2C_PM */ 630&i2c6 { 631 pinctrl-names = "default", "gpio"; 632 pinctrl-0 = <&pinctrl_i2c6>; 633 pinctrl-1 = <&pinctrl_i2c6_gpio>; 634 clock-frequency = <400000>; 635 scl-gpios = <&gpio3 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 636 sda-gpios = <&gpio3 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 637 single-master; 638}; 639 640&mdio { 641 eqos_phy: ethernet-phy@1 { 642 reg = <1>; 643 interrupt-parent = <&gpio3>; 644 interrupts = <0 IRQ_TYPE_LEVEL_LOW>; 645 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 646 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 647 }; 648 649 fec_phy: ethernet-phy@2 { 650 reg = <2>; 651 interrupt-parent = <&gpio3>; 652 interrupts = <0 IRQ_TYPE_LEVEL_LOW>; 653 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 654 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 655 }; 656}; 657 658/* SMARC PCIE_A */ 659&pcie { 660 pinctrl-names = "default"; 661 pinctrl-0 = <&pinctrl_pcie>; 662 reset-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>; 663}; 664 665&pcie_phy { 666 clocks = <&hsio_blk_ctrl>; 667 clock-names = "ref"; 668 fsl,clkreq-unsupported; 669 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>; 670}; 671 672/* SMARC LCD1_BKLT_PWM */ 673&pwm1 { 674 pinctrl-names = "default"; 675 pinctrl-0 = <&pinctrl_lcd1_bklt_pwm1>; 676}; 677 678/* SMARC LCD0_BKLT_PWM */ 679&pwm2 { 680 pinctrl-names = "default"; 681 pinctrl-0 = <&pinctrl_lcd0_bklt_pwm2>; 682}; 683 684/* SMARC GPIO5 as PWM */ 685&pwm3 { 686 pinctrl-names = "default"; 687 pinctrl-0 = <&pinctrl_gpio5_pwm>; 688}; 689 690&snvs_pwrkey { 691 status = "okay"; 692}; 693 694/* SMARC SER0 */ 695&uart1 { 696 pinctrl-names = "default"; 697 pinctrl-0 = <&pinctrl_uart1>; 698 uart-has-rtscts; 699}; 700 701/* SMARC SER2 */ 702&uart2 { 703 pinctrl-names = "default"; 704 pinctrl-0 = <&pinctrl_uart2>; 705 uart-has-rtscts; 706}; 707 708/* On-module Bluetooth, optional SMARC SER3 */ 709&uart3 { 710 pinctrl-names = "default"; 711 pinctrl-0 = <&pinctrl_bt_uart>; 712 uart-has-rtscts; 713 status = "okay"; 714 715 som_bt: bluetooth { 716 compatible = "mrvl,88w8997"; 717 max-speed = <921600>; 718 }; 719}; 720 721/* SMARC SER1, used as the Linux Console */ 722&uart4 { 723 pinctrl-names = "default"; 724 pinctrl-0 = <&pinctrl_uart4>; 725}; 726 727/* SMARC USB0 */ 728&usb3_0 { 729 fsl,disable-port-power-control; 730}; 731 732/* SMARC USB1..4 */ 733&usb3_1 { 734 fsl,disable-port-power-control; 735}; 736 737&usb3_phy1 { 738 vbus-supply = <®_usb1_vbus>; 739}; 740 741&usb_dwc3_0 { 742 adp-disable; 743 dr_mode = "otg"; 744 hnp-disable; 745 maximum-speed = "high-speed"; 746 srp-disable; 747 usb-role-switch; 748 749 port { 750 usb3_0_dwc: endpoint { 751 remote-endpoint = <&usb_dr_connector>; 752 }; 753 }; 754}; 755 756&usb_dwc3_1 { 757 dr_mode = "host"; 758}; 759 760/* On-module Wi-Fi */ 761&usdhc1 { 762 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 763 pinctrl-0 = <&pinctrl_usdhc1>; 764 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 765 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 766 keep-power-in-suspend; 767 non-removable; 768 vmmc-supply = <®_wifi_en>; 769 status = "okay"; 770}; 771 772/* SMARC SDIO */ 773&usdhc2 { 774 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 775 pinctrl-0 = <&pinctrl_usdhc2>, 776 <&pinctrl_usdhc2_cd>, 777 <&pinctrl_usdhc2_wp>; 778 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, 779 <&pinctrl_usdhc2_cd>, 780 <&pinctrl_usdhc2_wp>; 781 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, 782 <&pinctrl_usdhc2_cd>, 783 <&pinctrl_usdhc2_wp>; 784 pinctrl-3 = <&pinctrl_usdhc2_sleep>, 785 <&pinctrl_usdhc2_cd_sleep>, 786 <&pinctrl_usdhc2_wp>; 787 assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; 788 assigned-clock-rates = <400000000>; 789 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 790 vmmc-supply = <®_usdhc2_vmmc>; 791 vqmmc-supply = <®_usdhc2_vqmmc>; 792 wp-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; 793}; 794 795/* On-module eMMC */ 796&usdhc3 { 797 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 798 pinctrl-0 = <&pinctrl_usdhc3>; 799 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 800 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 801 assigned-clocks = <&clk IMX8MP_CLK_USDHC3_ROOT>; 802 assigned-clock-rates = <400000000>; 803 bus-width = <8>; 804 non-removable; 805 status = "okay"; 806}; 807 808&wdog1 { 809 pinctrl-names = "default"; 810 pinctrl-0 = <&pinctrl_wdog>; 811 fsl,ext-reset-output; 812 status = "okay"; 813}; 814 815&iomuxc { 816 /* On-module Bluetooth */ 817 pinctrl_bt_uart: btuartgrp { 818 fsl,pins = <MX8MP_IOMUXC_SD1_DATA6__UART3_DCE_TX 0x1c4>, /* WiFi_UART_TXD */ 819 <MX8MP_IOMUXC_SD1_DATA7__UART3_DCE_RX 0x1c4>, /* WiFi_UART_RXD */ 820 <MX8MP_IOMUXC_SD1_STROBE__UART3_DCE_CTS 0x1c4>, /* WiFi_UART_RTS */ 821 <MX8MP_IOMUXC_SD1_RESET_B__UART3_DCE_RTS 0x1c4>; /* WiFi_UART_CTS */ 822 }; 823 824 /* SMARC CAM_MCK */ 825 pinctrl_csi_mclk: csimclkgrp { 826 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO15__CCM_CLKO2 0x16>; /* SMARC S6 - CAM_MCK */ 827 }; 828 829 /* SMARC SPI0 */ 830 pinctrl_ecspi1: ecspi1grp { 831 fsl,pins = <MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x1c4>, /* SMARC P45 - SPI0_DIN */ 832 <MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x4>, /* SMARC P46 - SPI0_DO */ 833 <MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x4>, /* SMARC P44 - SPI0_CK */ 834 <MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x1c4>, /* SMARC P43 - SPI0_CS0# */ 835 <MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x1c4>; /* SMARC P31 - SPI0_CS1# */ 836 }; 837 838 /* SMARC SPI1 */ 839 pinctrl_ecspi2: ecspi2grp { 840 fsl,pins = <MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x1c4>, /* SMARC P56 - SPI1_DIN */ 841 <MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x4>, /* SMARC P57 - SPI1_DO */ 842 <MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x4>, /* SMARC P58 - SPI1_CK */ 843 <MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x1c4>, /* SMARC P54 - SPI1_CS0# */ 844 <MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x1c4>; /* SMARC P55 - SPI1_CS1# */ 845 }; 846 847 /* ETH_0 RGMII (On-module PHY) */ 848 pinctrl_eqos: eqosgrp { 849 fsl,pins = <MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90>, /* ETH0_RGMII_RXD0 */ 850 <MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90>, /* ETH0_RGMII_RXD1 */ 851 <MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90>, /* ETH0_RGMII_RXD2 */ 852 <MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90>, /* ETH0_RGMII_RXD3 */ 853 <MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90>, /* ETH0_RGMII_RXC */ 854 <MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90>, /* ETH0_RGMII_RX_CTL */ 855 <MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16>, /* ETH0_RGMII_TXD0 */ 856 <MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16>, /* ETH0_RGMII_TXD1 */ 857 <MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16>, /* ETH0_RGMII_TXD2 */ 858 <MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16>, /* ETH0_RGMII_TXD3 */ 859 <MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16>, /* ETH0_RGMII_TX_CTL */ 860 <MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16>; /* ETH0_RGMII_TXC */ 861 }; 862 863 /* SMARC GBE0_SDP */ 864 pinctrl_eqos_1588_event: eqos1588eventgrp { 865 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO09__ENET_QOS_1588_EVENT0_OUT 0x4>; /* SMARC P6 - GBE0_SDP */ 866 }; 867 868 /* ETH_0_MDIO and ETH_0_INT# shared between ETH_PHY0 and ETH_PHY1 */ 869 pinctrl_eth_mdio: ethmdiogrp { 870 fsl,pins = <MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2>, /* ETH_0_MDC */ 871 <MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2>, /* ETH_0_MDIO */ 872 <MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x80>; /* ETH_0_INT# */ 873 }; 874 875 /* ETH_1 RGMII (On-module PHY) */ 876 pinctrl_fec: fecgrp { 877 fsl,pins = <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90>, /* ETH1_RGMII_RXD0 */ 878 <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90>, /* ETH1_RGMII_RXD1 */ 879 <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90>, /* ETH1_RGMII_RXD2 */ 880 <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90>, /* ETH1_RGMII_RXD3 */ 881 <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90>, /* ETH1_RGMII_RXC */ 882 <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90>, /* ETH1_RGMII_RX_CTL */ 883 <MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16>, /* ETH1_RGMII_TXD0 */ 884 <MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16>, /* ETH1_RGMII_TXD1 */ 885 <MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16>, /* ETH1_RGMII_TXD2 */ 886 <MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16>, /* ETH1_RGMII_TXD3 */ 887 <MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16>, /* ETH1_RGMII_TX_CTL */ 888 <MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16>; /* ETH1_RGMII_TXC */ 889 }; 890 891 /* SMARC GBE1_SDP */ 892 pinctrl_fec_1588_event: fec1588eventgrp { 893 fsl,pins = <MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x4>; /* SMARC P5 - GBE1_SDP */ 894 }; 895 896 /* SMARC CAN1 */ 897 pinctrl_flexcan1: flexcan1grp { 898 fsl,pins = <MX8MP_IOMUXC_SAI2_TXC__CAN1_RX 0x154>, /* SMARC P146 - CAN1_RX */ 899 <MX8MP_IOMUXC_SAI2_RXC__CAN1_TX 0x154>; /* SMARC P145 - CAN1_TX */ 900 }; 901 902 /* SMARC CAN0 */ 903 pinctrl_flexcan2: flexcan2grp { 904 fsl,pins = <MX8MP_IOMUXC_SAI2_MCLK__CAN2_RX 0x154>, /* SMARC P144 - CAN0_RX */ 905 <MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX 0x154>; /* SMARC P143 - CAN0_TX */ 906 }; 907 908 /* SMARC GPIO4 */ 909 pinctrl_gpio4: gpio4grp { 910 fsl,pins = <MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x144>; /* SMARC P112 - GPIO4 */ 911 }; 912 913 /* SMARC GPIO5 */ 914 pinctrl_gpio5: gpio5grp { 915 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x144>; /* SMARC P113 - GPIO5 */ 916 }; 917 918 /* SMARC GPIO5 as PWM */ 919 pinctrl_gpio5_pwm: gpio5pwmgrp { 920 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO10__PWM3_OUT 0x12>; /* SMARC P113 - PWM_OUT */ 921 }; 922 923 /* SMARC GPIO6 */ 924 pinctrl_gpio6: gpio6grp { 925 fsl,pins = <MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x144>; /* SMARC P114 - GPIO6 */ 926 }; 927 928 /* SMARC GPIO7 */ 929 pinctrl_gpio7: gpio7grp { 930 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x144>; /* SMARC P115 - GPIO7 */ 931 }; 932 933 /* SMARC GPIO8 */ 934 pinctrl_gpio8: gpio8grp { 935 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x144>; /* SMARC P116 - GPIO8 */ 936 }; 937 938 /* SMARC GPIO9 */ 939 pinctrl_gpio9: gpio9grp { 940 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x144>; /* SMARC P117 - GPIO9 */ 941 }; 942 943 /* SMARC GPIO10 */ 944 pinctrl_gpio10: gpio10grp { 945 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x144>; /* SMARC P118 - GPIO10 */ 946 }; 947 948 /* SMARC GPIO11 */ 949 pinctrl_gpio11: gpio11grp { 950 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x144>; /* SMARC P119 - GPIO11 */ 951 }; 952 953 /* SMARC GPIO12 */ 954 pinctrl_gpio12: gpio12grp { 955 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x144>; /* SMARC S142 - GPIO12 */ 956 }; 957 958 /* SMARC GPIO13 */ 959 pinctrl_gpio13: gpio13grp { 960 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144>; /* SMARC S123 - GPIO13 */ 961 }; 962 963 /* SMARC HDMI */ 964 pinctrl_hdmi: hdmigrp { 965 fsl,pins = <MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c6>, /* SMARC P105 - HDMI_CTRL_CK */ 966 <MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c6>, /* SMARC P106 - HDMI_CTRL_DAT */ 967 <MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x180>; /* SMARC P104 - HDMI_HPD */ 968 }; 969 970 /* On-module I2C */ 971 pinctrl_i2c1: i2c1grp { 972 fsl,pins = <MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c6>, /* CTRL_I2C_SCL */ 973 <MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c6>; /* CTRL_I2C_SDA */ 974 }; 975 976 /* On-module I2C as GPIOs */ 977 pinctrl_i2c1_gpio: i2c1gpiogrp { 978 fsl,pins = <MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c6>, /* CTRL_I2C_SCL */ 979 <MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c6>; /* CTRL_I2C_SDA */ 980 }; 981 982 /* SMARC I2C_LCD */ 983 pinctrl_i2c2: i2c2grp { 984 fsl,pins = <MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c6>, /* SMARC S139 - I2C_LCD_CK */ 985 <MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c6>; /* SMARC S140 - I2C_LCD_DAT */ 986 }; 987 988 /* SMARC I2C_LCD as GPIOs */ 989 pinctrl_i2c2_gpio: i2c2gpiogrp { 990 fsl,pins = <MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c6>, /* SMARC S139 - I2C_LCD_CK */ 991 <MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c6>; /* SMARC S140 - I2C_LCD_DAT */ 992 }; 993 994 /* SMARC I2C_CAM0 */ 995 pinctrl_i2c3: i2c3grp { 996 fsl,pins = <MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c6>, /* SMARC S5 - I2C_CAM0_CK */ 997 <MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c6>; /* SMARC S7 - I2C_CAM0_DAT */ 998 }; 999 1000 /* SMARC I2C_CAM0 as GPIOs */ 1001 pinctrl_i2c3_gpio: i2c3gpiogrp { 1002 fsl,pins = <MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c6>, /* SMARC S5 - I2C_CAM0_CK */ 1003 <MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c6>; /* SMARC S7 - I2C_CAM0_DAT */ 1004 }; 1005 1006 /* SMARC I2C_GP */ 1007 pinctrl_i2c4: i2c4grp { 1008 fsl,pins = <MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c6>, /* SMARC S48 - I2C_GP_CK */ 1009 <MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c6>; /* SMARC S49 - I2C_GP_DAT */ 1010 }; 1011 1012 /* SMARC I2C_GP as GPIOs */ 1013 pinctrl_i2c4_gpio: i2c4gpiogrp { 1014 fsl,pins = <MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001c6>, /* SMARC S48 - I2C_GP_CK */ 1015 <MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001c6>; /* SMARC S49 - I2C_GP_DAT */ 1016 }; 1017 1018 /* SMARC I2C_CAM1 */ 1019 pinctrl_i2c5: i2c5grp { 1020 fsl,pins = <MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c6>, /* SMARC S2 - I2C_CAM1_DAT */ 1021 <MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c6>; /* SMARC S1 - I2C_CAM1_CK */ 1022 }; 1023 1024 /* SMARC I2C_CAM1 as GPIOs */ 1025 pinctrl_i2c5_gpio: i2c5gpiogrp { 1026 fsl,pins = <MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x400001c6>, /* SMARC S2 - I2C_CAM1_DAT */ 1027 <MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03 0x400001c6>; /* SMARC S1 - I2C_CAM1_CK */ 1028 }; 1029 1030 /* SMARC I2C_PM */ 1031 pinctrl_i2c6: i2c6grp { 1032 fsl,pins = <MX8MP_IOMUXC_HDMI_CEC__I2C6_SCL 0x400001c6>, /* SMARC P121 - I2C_PM_CK */ 1033 <MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x400001c6>; /* SMARC P122 - I2C_PM_DAT */ 1034 }; 1035 1036 /* SMARC I2C_PM as GPIOs */ 1037 pinctrl_i2c6_gpio: i2c6gpiogrp { 1038 fsl,pins = <MX8MP_IOMUXC_HDMI_CEC__GPIO3_IO28 0x400001c6>, /* SMARC P121 - I2C_PM_CK */ 1039 <MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x400001c6>; /* SMARC P122 - I2C_PM_DAT */ 1040 }; 1041 1042 pinctrl_lvds_dsi_sel: lvdsdsiselgrp { 1043 fsl,pins = <MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x104>; /* LVDS_DSI_SEL */ 1044 }; 1045 1046 pinctrl_mcu_int: mcuintgrp { 1047 fsl,pins = <MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x1C0>; /* MCU_INT# */ 1048 }; 1049 1050 /* SMARC LCD1_BKLT_PWM */ 1051 pinctrl_lcd1_bklt_pwm1: pwm1grp { 1052 fsl,pins = <MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT 0x12>; /* SMARC S122 - LCD1_BKLT_PWM */ 1053 }; 1054 1055 /* SMARC LCD0_BKLT_PWM */ 1056 pinctrl_lcd0_bklt_pwm2: pwm2grp { 1057 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x12>; /* SMARC S141 - LCD0_BKLT_PWM */ 1058 }; 1059 1060 /* PCAL6408 Interrupt */ 1061 pinctrl_pcal6408: pcal6408intgrp { 1062 fsl,pins = <MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x1c4>; /* GPIO_EX_INT# */ 1063 }; 1064 1065 /* SMARC PCIE_A */ 1066 pinctrl_pcie: pciegrp { 1067 fsl,pins = <MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x1c0>, /* SMARC S146 - PCIE_WAKE# */ 1068 <MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x04>; /* SMARC P75 - PCIE_A_RST# */ 1069 }; 1070 1071 /* PMIC Interrupt */ 1072 pinctrl_pmic: pmicintgrp { 1073 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c4>; /* PMIC_INT# */ 1074 }; 1075 1076 /* SMARC I2S0 */ 1077 pinctrl_sai1: sai1grp { 1078 fsl,pins = <MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI1_TX_BCLK 0x94>, /* SMARC S42 - I2S0_CK */ 1079 <MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_SYNC 0x94>, /* SMARC S39 - I2S0_LRCLK */ 1080 <MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_RX_DATA00 0x94>, /* SMARC S41 - I2S0_SDIN */ 1081 <MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI1_TX_DATA00 0x94>; /* SMARC S40 - I2S0_SDOUT */ 1082 }; 1083 1084 /* SMARC AUDIO_MCK */ 1085 pinctrl_sai1_mclk: sai1mclkgrp { 1086 fsl,pins = <MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_MCLK 0x96>; /* SMARC S38 - AUDIO_MCK */ 1087 }; 1088 1089 /* SMARC I2S2 */ 1090 pinctrl_sai3: sai3grp { 1091 fsl,pins = <MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0x94>, /* SMARC S52 - I2S2_SDIN */ 1092 <MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0x94>, /* SMARC S53 - I2S2_CK */ 1093 <MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0x94>, /* SMARC S51 - I2S2_SDOUT */ 1094 <MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0x94>; /* SMARC S50 - I2S2_LRCLK */ 1095 }; 1096 1097 /* SMARC SLEEP# */ 1098 pinctrl_sleep: sleepgrp { 1099 fsl,pins = <MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x1C0>; /* SMARC S149 - SLEEP# */ 1100 }; 1101 1102 /* SMARC SMB_ALERT# */ 1103 pinctrl_smb_alert: smbalertgrp { 1104 fsl,pins = <MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x1C0>; /* SMARC P1 - SMB_ALERT# */ 1105 }; 1106 1107 /* TPM_CS# */ 1108 pinctrl_tpm_cs: tpmcsgrp { 1109 fsl,pins = <MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x82>; /* TPM_CS# */ 1110 }; 1111 1112 /* WIFI_BT_WKUP_HOST/TPM_INT# */ 1113 pinctrl_tpm_irq_wifi_bt_wkup: tpmirq-wifibtwkupgrp { 1114 fsl,pins = <MX8MP_IOMUXC_SAI1_RXD2__GPIO4_IO04 0x16>; /* WIFI_BT_WKUP_HOST/TPM_INT# */ 1115 }; 1116 1117 /* SMARC SER0 */ 1118 pinctrl_uart1: uart1grp { 1119 fsl,pins = <MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS 0x1c4>, /* SMARC P132 - SER2_CTS */ 1120 <MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS 0x1c4>, /* SMARC P131 - SER2_RTS */ 1121 <MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x1c4>, /* SMARC P130 - SER2_RX */ 1122 <MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x1c4>; /* SMARC P139 - SER2_TX */ 1123 }; 1124 1125 /* SMARC SER2 */ 1126 pinctrl_uart2: uart2grp { 1127 fsl,pins = <MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS 0x1c4>, /* SMARC P139 - SER2_CTS */ 1128 <MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS 0x1c4>, /* SMARC P138 - SER2_RTS */ 1129 <MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x1c4>, /* SMARC P137 - SER2_RX */ 1130 <MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x1c4>; /* SMARC P136 - SER2_TX */ 1131 }; 1132 1133 /* SMARC SER3 */ 1134 pinctrl_uart3: uart3grp { 1135 fsl,pins = <MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x1c4>, /* SMARC P141 - SER3_RX */ 1136 <MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x1c4>; /* SMARC P140 - SER3_TX */ 1137 }; 1138 1139 /* SMARC SER1 */ 1140 pinctrl_uart4: uart4grp { 1141 fsl,pins = <MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x1c4>, /* SMARC P135 - SER1_RX */ 1142 <MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x1c4>; /* SMARC P134 - SER1_TX */ 1143 }; 1144 1145 /* SMARC USB0_OTG_ID */ 1146 pinctrl_usb0_id: usb0idgrp { 1147 fsl,pins = <MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x1c4>; /* SMARC P64 - USB0_OTG_ID */ 1148 }; 1149 1150 /* SMARC USB0_EN_OC# */ 1151 pinctrl_usb0_en_oc: usb0enocgrp { 1152 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x04>; /* SMARC P62 - USB0_EN_OC# */ 1153 }; 1154 1155 /* On module USB Hub VBUS, or SMARC USB2_EN_OC# depending on assembling */ 1156 pinctrl_usb1_en_oc: usb1enocgrp { 1157 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x04>; /* SMARC P71 - USB2_EN_OC# */ 1158 }; 1159 1160 /* On-module Wi-Fi */ 1161 pinctrl_usdhc1: usdhc1grp { 1162 fsl,pins = <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190>, /* WiFi_SDIO_CLK */ 1163 <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0>, /* WiFi_SDIO_CMD */ 1164 <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0>, /* WiFi_SDIO_DATA0 */ 1165 <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0>, /* WiFi_SDIO_DATA1 */ 1166 <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0>, /* WiFi_SDIO_DATA2 */ 1167 <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0>; /* WiFi_SDIO_DATA3 */ 1168 }; 1169 1170 /* On-module Wi-Fi */ 1171 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 1172 fsl,pins = <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194>, /* WiFi_SDIO_CLK */ 1173 <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4>, /* WiFi_SDIO_CMD */ 1174 <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4>, /* WiFi_SDIO_DATA0 */ 1175 <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4>, /* WiFi_SDIO_DATA1 */ 1176 <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4>, /* WiFi_SDIO_DATA2 */ 1177 <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4>; /* WiFi_SDIO_DATA3 */ 1178 }; 1179 1180 /* On-module Wi-Fi */ 1181 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 1182 fsl,pins = <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196>, /* WiFi_SDIO_CLK */ 1183 <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6>, /* WiFi_SDIO_CMD */ 1184 <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6>, /* WiFi_SDIO_DATA0 */ 1185 <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6>, /* WiFi_SDIO_DATA1 */ 1186 <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6>, /* WiFi_SDIO_DATA2 */ 1187 <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6>; /* WiFi_SDIO_DATA3 */ 1188 }; 1189 1190 /* SMARC SDIO */ 1191 pinctrl_usdhc2: usdhc2grp { 1192 fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190>, /* SMARC P36 - SDIO_CK */ 1193 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0>, /* SMARC P34 - SDIO_CMD */ 1194 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0>, /* SMARC P39 - SDIO_DO */ 1195 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0>, /* SMARC P40 - SDIO_D1 */ 1196 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0>, /* SMARC P41 - SDIO_D2 */ 1197 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0>; /* SMARC P42 - SDIO_D3 */ 1198 }; 1199 1200 /* SMARC SDIO 100MHz */ 1201 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 1202 fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>, /* SMARC P36 - SDIO_CK */ 1203 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>, /* SMARC P34 - SDIO_CMD */ 1204 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>, /* SMARC P39 - SDIO_DO */ 1205 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>, /* SMARC P40 - SDIO_D1 */ 1206 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>, /* SMARC P41 - SDIO_D2 */ 1207 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>; /* SMARC P42 - SDIO_D3 */ 1208 }; 1209 1210 /* SMARC SDIO 200MHz */ 1211 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 1212 fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196>, /* SMARC P36 - SDIO_CK */ 1213 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6>, /* SMARC P34 - SDIO_CMD */ 1214 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6>, /* SMARC P39 - SDIO_DO */ 1215 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6>, /* SMARC P40 - SDIO_D1 */ 1216 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6>, /* SMARC P41 - SDIO_D2 */ 1217 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6>; /* SMARC P42 - SDIO_D3 */ 1218 }; 1219 1220 /* SMARC SDIO_CD# */ 1221 pinctrl_usdhc2_cd: usdhc2cdgrp { 1222 fsl,pins = <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4>; /* SMARC P35 - SDIO_CD# */ 1223 }; 1224 1225 /* SMARC SDIO_CD# */ 1226 pinctrl_usdhc2_cd_sleep: usdhc2cdslpgrp { 1227 fsl,pins = <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x0>; /* SMARC P35 - SDIO_CD# */ 1228 }; 1229 1230 /* SMARC SDIO_PWR_EN */ 1231 pinctrl_usdhc2_pwr_en: usdhc2pwrengrp { 1232 fsl,pins = <MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x1c4>; /* SMARC P37 - SDIO_PWR_EN */ 1233 }; 1234 1235 /* SMARC SDIO Sleep - Avoid backfeeding with removed card power */ 1236 pinctrl_usdhc2_sleep: usdhc2slpgrp { 1237 fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x100>, /* SMARC P36 - SDIO_CK */ 1238 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x100>, /* SMARC P34 - SDIO_CMD */ 1239 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x100>, /* SMARC P39 - SDIO_DO */ 1240 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x100>, /* SMARC P39 - SDIO_D1 */ 1241 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x100>, /* SMARC P39 - SDIO_D2 */ 1242 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x100>; /* SMARC P39 - SDIO_D3 */ 1243 }; 1244 1245 pinctrl_usdhc2_vsel: usdhc2vselgrp { 1246 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04 0x4>; /* PMIC_USDHC_VSELECT */ 1247 }; 1248 1249 /* SMARC SDIO_WP */ 1250 pinctrl_usdhc2_wp: usdhc2wpgrp { 1251 fsl,pins = <MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x144>; /* SMARC P33 - SDIO_WP */ 1252 }; 1253 1254 /* On-module eMMC */ 1255 pinctrl_usdhc3: usdhc3grp { 1256 fsl,pins = <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190>, /* eMMC_STROBE */ 1257 <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0>, /* eMMC_DATA5 */ 1258 <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0>, /* eMMC_DATA6 */ 1259 <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0>, /* eMMC_DATA7 */ 1260 <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0>, /* eMMC_DATA0 */ 1261 <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0>, /* eMMC_DATA1 */ 1262 <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0>, /* eMMC_DATA2 */ 1263 <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0>, /* eMMC_DATA3 */ 1264 <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0>, /* eMMC_DATA4 */ 1265 <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190>, /* eMMC_CLK */ 1266 <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0>; /* eMMC_CMD */ 1267 }; 1268 1269 /* On-module eMMC */ 1270 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 1271 fsl,pins = <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194>, /* eMMC_STROBE */ 1272 <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4>, /* eMMC_DATA5 */ 1273 <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4>, /* eMMC_DATA6 */ 1274 <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4>, /* eMMC_DATA7 */ 1275 <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4>, /* eMMC_DATA0 */ 1276 <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4>, /* eMMC_DATA1 */ 1277 <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4>, /* eMMC_DATA2 */ 1278 <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4>, /* eMMC_DATA3 */ 1279 <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4>, /* eMMC_DATA4 */ 1280 <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194>, /* eMMC_CLK */ 1281 <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4>; /* eMMC_CMD */ 1282 }; 1283 1284 /* On-module eMMC */ 1285 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 1286 fsl,pins = <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196>, /* eMMC_STROBE */ 1287 <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d2>, /* eMMC_DATA5 */ 1288 <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d2>, /* eMMC_DATA6 */ 1289 <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d2>, /* eMMC_DATA7 */ 1290 <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d2>, /* eMMC_DATA0 */ 1291 <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d2>, /* eMMC_DATA1 */ 1292 <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d2>, /* eMMC_DATA2 */ 1293 <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d2>, /* eMMC_DATA3 */ 1294 <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d2>, /* eMMC_DATA4 */ 1295 <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196>, /* eMMC_CLK */ 1296 <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6>; /* eMMC_CMD */ 1297 }; 1298 1299 /* SoC Watchdog */ 1300 pinctrl_wdog: wdoggrp { 1301 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x4>; /* CTRL_SOC_WDOG */ 1302 }; 1303 1304 /* On-module Wi-Fi power enable */ 1305 pinctrl_wifi_pwr_en: wifipwrengrp { 1306 fsl,pins = <MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x104>; /* CTRL_EN_WIFI */ 1307 }; 1308};
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