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imx8mp-phycore-som.dtsi

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linux-6.19.14/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi DEVICETREE 
  1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2/*
  3 * Copyright (C) 2020 PHYTEC Messtechnik GmbH
  4 */
  5
  6#include <dt-bindings/net/ti-dp83867.h>
  7#include "imx8mp.dtsi"
  8
  9/ {
 10	model = "PHYTEC phyCORE-i.MX8MP";
 11	compatible = "phytec,imx8mp-phycore-som", "fsl,imx8mp";
 12
 13	aliases {
 14		rtc0 = &rv3028;
 15		rtc1 = &snvs_rtc;
 16	};
 17
 18	memory@40000000 {
 19		device_type = "memory";
 20		reg = <0x0 0x40000000 0 0x80000000>;
 21	};
 22
 23	reg_vdd_io: regulator-vdd-io {
 24		compatible = "regulator-fixed";
 25		regulator-always-on;
 26		regulator-boot-on;
 27		regulator-max-microvolt = <3300000>;
 28		regulator-min-microvolt = <3300000>;
 29		regulator-name = "VDD_IO";
 30	};
 31};
 32
 33&A53_0 {
 34	cpu-supply = <&buck2>;
 35};
 36
 37&A53_1 {
 38	cpu-supply = <&buck2>;
 39};
 40
 41&A53_2 {
 42	cpu-supply = <&buck2>;
 43};
 44
 45&A53_3 {
 46	cpu-supply = <&buck2>;
 47};
 48
 49/* ethernet 1 */
 50&fec {
 51	pinctrl-names = "default";
 52	pinctrl-0 = <&pinctrl_fec>;
 53	phy-handle = <&ethphy1>;
 54	phy-mode = "rgmii-id";
 55	fsl,magic-packet;
 56	status = "okay";
 57
 58	mdio {
 59		#address-cells = <1>;
 60		#size-cells = <0>;
 61
 62		ethphy1: ethernet-phy@0 {
 63			compatible = "ethernet-phy-ieee802.3-c22";
 64			reg = <0>;
 65			enet-phy-lane-no-swap;
 66			ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
 67			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
 68			ti,min-output-impedance;
 69			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
 70			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
 71		};
 72	};
 73};
 74
 75&flexspi {
 76	pinctrl-names = "default";
 77	pinctrl-0 = <&pinctrl_flexspi0>;
 78	status = "okay";
 79
 80	som_flash: flash@0 {
 81		compatible = "jedec,spi-nor";
 82		reg = <0>;
 83		spi-max-frequency = <80000000>;
 84		spi-rx-bus-width = <4>;
 85		spi-tx-bus-width = <1>;
 86	};
 87};
 88
 89&i2c1 {
 90	clock-frequency = <400000>;
 91	pinctrl-names = "default", "gpio";
 92	pinctrl-0 = <&pinctrl_i2c1>;
 93	pinctrl-1 = <&pinctrl_i2c1_gpio>;
 94	scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 95	sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 96	status = "okay";
 97
 98	pmic: pmic@25 {
 99		compatible = "nxp,pca9450c";
100		reg = <0x25>;
101		interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
102		interrupt-parent = <&gpio4>;
103		pinctrl-names = "default";
104		pinctrl-0 = <&pinctrl_pmic>;
105
106		regulators {
107			buck1: BUCK1 {
108				regulator-always-on;
109				regulator-boot-on;
110				regulator-max-microvolt = <1000000>;
111				regulator-min-microvolt = <805000>;
112				regulator-name = "VDD_SOC (BUCK1)";
113				regulator-ramp-delay = <3125>;
114			};
115
116			buck2: BUCK2 {
117				nxp,dvs-run-voltage = <950000>;
118				nxp,dvs-standby-voltage = <850000>;
119				regulator-always-on;
120				regulator-boot-on;
121				regulator-max-microvolt = <1050000>;
122				regulator-min-microvolt = <805000>;
123				regulator-name = "VDD_ARM (BUCK2)";
124				regulator-ramp-delay = <3125>;
125			};
126
127			buck4: BUCK4 {
128				regulator-always-on;
129				regulator-boot-on;
130				regulator-max-microvolt = <3300000>;
131				regulator-min-microvolt = <3300000>;
132				regulator-name = "VDD_3V3 (BUCK4)";
133			};
134
135			buck5: BUCK5 {
136				regulator-always-on;
137				regulator-boot-on;
138				regulator-max-microvolt = <1800000>;
139				regulator-min-microvolt = <1800000>;
140				regulator-name = "VDD_1V8 (BUCK5)";
141			};
142
143			buck6: BUCK6 {
144				regulator-always-on;
145				regulator-boot-on;
146				regulator-max-microvolt = <1155000>;
147				regulator-min-microvolt = <1045000>;
148				regulator-name = "NVCC_DRAM_1V1 (BUCK6)";
149			};
150
151			ldo1: LDO1 {
152				regulator-always-on;
153				regulator-boot-on;
154				regulator-max-microvolt = <1950000>;
155				regulator-min-microvolt = <1710000>;
156				regulator-name = "NVCC_SNVS_1V8 (LDO1)";
157			};
158
159			ldo3: LDO3 {
160				regulator-always-on;
161				regulator-boot-on;
162				regulator-max-microvolt = <1800000>;
163				regulator-min-microvolt = <1800000>;
164				regulator-name = "VDDA_1V8 (LDO3)";
165			};
166
167			ldo5: LDO5 {
168				regulator-always-on;
169				regulator-boot-on;
170				regulator-max-microvolt = <3300000>;
171				regulator-min-microvolt = <1800000>;
172				regulator-name = "NVCC_SD2 (LDO5)";
173			};
174		};
175	};
176
177	eeprom@51 {
178		compatible = "atmel,24c32";
179		reg = <0x51>;
180		pagesize = <32>;
181		vcc-supply = <&reg_vdd_io>;
182	};
183
184	rv3028: rtc@52 {
185		compatible = "microcrystal,rv3028";
186		reg = <0x52>;
187	};
188};
189
190/* eMMC */
191&usdhc3 {
192	assigned-clocks = <&clk IMX8MP_CLK_USDHC3_ROOT>;
193	assigned-clock-rates = <400000000>;
194	pinctrl-names = "default", "state_100mhz", "state_200mhz";
195	pinctrl-0 = <&pinctrl_usdhc3>;
196	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
197	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
198	bus-width = <8>;
199	non-removable;
200	status = "okay";
201};
202
203&wdog1 {
204	pinctrl-names = "default";
205	pinctrl-0 = <&pinctrl_wdog>;
206	fsl,ext-reset-output;
207	status = "okay";
208};
209
210&gpio1 {
211	gpio-line-names = "", "", "X_PMIC_WDOG_B";
212};
213
214&gpio4 {
215	gpio-line-names = "", "", "", "",
216		"", "", "", "", "", "",
217		"", "", "", "", "", "",
218		"", "", "X_PMIC_IRQ_B";
219};
220
221&iomuxc {
222	pinctrl_fec: fecgrp {
223		fsl,pins = <
224			MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x2
225			MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO		0x2
226			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0		0x90
227			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1		0x90
228			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2		0x90
229			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3		0x90
230			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x90
231			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0		0x12
232			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1		0x12
233			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2		0x14
234			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3		0x14
235			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x14
236			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC		0x14
237			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x90
238		>;
239	};
240
241	pinctrl_flexspi0: flexspi0grp {
242		fsl,pins = <
243			MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK		0x1c2
244			MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B	0x82
245			MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00	0x82
246			MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01	0x82
247			MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02	0x82
248			MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03	0x82
249		>;
250	};
251
252	pinctrl_i2c1: i2c1grp {
253		fsl,pins = <
254			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA		0x400001c2
255			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL		0x400001c2
256		>;
257	};
258
259	pinctrl_i2c1_gpio: i2c1gpiogrp {
260		fsl,pins = <
261			MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14	0x1e2
262			MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15	0x1e2
263		>;
264	};
265
266	pinctrl_pmic: pmicirqgrp {
267		fsl,pins = <
268			MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18	0x140
269		>;
270	};
271
272	pinctrl_usdhc3: usdhc3grp {
273		fsl,pins = <
274			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x190
275			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d0
276			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d0
277			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d0
278			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d0
279			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d0
280			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d0
281			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d0
282			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d0
283			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x190
284			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d0
285		>;
286	};
287
288	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
289		fsl,pins = <
290			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x194
291			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d4
292			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d4
293			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d4
294			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d4
295			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d4
296			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d4
297			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d4
298			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d4
299			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x194
300			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d4
301		>;
302	};
303
304	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
305		fsl,pins = <
306			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x196
307			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d2
308			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d2
309			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d2
310			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d2
311			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d2
312			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d2
313			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d2
314			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d2
315			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x196
316			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d6
317		>;
318	};
319
320	pinctrl_wdog: wdoggrp {
321		fsl,pins = <
322			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B	0xe6
323		>;
324	};
325};
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