imx8mp-nominal.dtsi

  1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2/*
  3 * Copyright (C) 2024 Pengutronix, Ahmad Fatoum <kernel@pengutronix.de>
  4 */
  5
  6&clk {
  7	assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
  8			  <&clk IMX8MP_CLK_A53_CORE>,
  9			  <&clk IMX8MP_SYS_PLL3>,
 10			  <&clk IMX8MP_CLK_NOC>,
 11			  <&clk IMX8MP_CLK_NOC_IO>,
 12			  <&clk IMX8MP_CLK_GIC>;
 13	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
 14				 <&clk IMX8MP_ARM_PLL_OUT>,
 15				 <0>,
 16				 <&clk IMX8MP_SYS_PLL1_800M>,
 17				 <&clk IMX8MP_SYS_PLL3_OUT>,
 18				 <&clk IMX8MP_SYS_PLL1_800M>;
 19	assigned-clock-rates = <0>, <0>,
 20			       <600000000>,
 21			       <800000000>,
 22			       <600000000>,
 23			       <400000000>;
 24	fsl,operating-mode = "nominal";
 25};
 26
 27&gpu2d {
 28	assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>;
 29	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
 30	assigned-clock-rates = <800000000>;
 31};
 32
 33&gpu3d {
 34	assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>,
 35			  <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>;
 36	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
 37				 <&clk IMX8MP_SYS_PLL1_800M>;
 38	assigned-clock-rates = <800000000>, <800000000>;
 39};
 40
 41&pgc_hdmimix {
 42	assigned-clocks = <&clk IMX8MP_CLK_HDMI_AXI>,
 43			  <&clk IMX8MP_CLK_HDMI_APB>;
 44	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
 45				 <&clk IMX8MP_SYS_PLL1_133M>;
 46	assigned-clock-rates = <400000000>, <133000000>;
 47};
 48
 49&pgc_hsiomix {
 50	assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
 51	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
 52	assigned-clock-rates = <400000000>;
 53};
 54
 55&pgc_gpumix {
 56	assigned-clocks = <&clk IMX8MP_CLK_GPU_AXI>,
 57			  <&clk IMX8MP_CLK_GPU_AHB>;
 58	assigned-clock-parents = <&clk IMX8MP_SYS_PLL3_OUT>,
 59				 <&clk IMX8MP_SYS_PLL3_OUT>;
 60	assigned-clock-rates = <600000000>, <300000000>;
 61};
 62
 63&pgc_mlmix {
 64	assigned-clocks = <&clk IMX8MP_CLK_ML_CORE>,
 65			  <&clk IMX8MP_CLK_ML_AXI>,
 66			  <&clk IMX8MP_CLK_ML_AHB>;
 67	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
 68				 <&clk IMX8MP_SYS_PLL1_800M>,
 69				 <&clk IMX8MP_SYS_PLL1_800M>;
 70	assigned-clock-rates = <800000000>,
 71			       <800000000>,
 72			       <300000000>;
 73};
 74
 75&media_blk_ctrl {
 76	assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>,
 77			  <&clk IMX8MP_CLK_MEDIA_APB>,
 78			  <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>,
 79			  <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>,
 80			  <&clk IMX8MP_CLK_MEDIA_ISP>,
 81			  <&clk IMX8MP_VIDEO_PLL1>;
 82	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
 83				 <&clk IMX8MP_SYS_PLL1_800M>,
 84				 <&clk IMX8MP_VIDEO_PLL1_OUT>,
 85				 <&clk IMX8MP_VIDEO_PLL1_OUT>,
 86				 <&clk IMX8MP_SYS_PLL1_800M>;
 87	assigned-clock-rates = <400000000>, <200000000>,
 88			       <0>, <0>, <400000000>,
 89			       <1039500000>;
 90};
 91
 92&vpu_g1 {
 93	assigned-clocks = <&clk IMX8MP_CLK_VPU_G1>;
 94	assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>;
 95	assigned-clock-rates = <600000000>;
 96};
 97
 98&vpu_g2 {
 99	assigned-clocks = <&clk IMX8MP_CLK_VPU_G2>;
100	assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;
101	assigned-clock-rates = <500000000>;
102};
103
104&vpumix_blk_ctrl {
105	assigned-clocks = <&clk IMX8MP_VPU_PLL>, <&clk IMX8MP_CLK_VPU_BUS>;
106	assigned-clock-parents = <0>, <&clk IMX8MP_VPU_PLL_OUT>;
107	assigned-clock-rates = <600000000>, <600000000>;
108};
109
110/delete-node/ &{noc_opp_table/opp-1000000000};