imx8mp-hummingboard-pulse-m2con.dtsi

 1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 2/*
 3 * Copyright 2025 Josua Mayer <josua@solid-run.com>
 4 */
 5
 6/ {
 7	rfkill-m2-gnss {
 8		compatible = "rfkill-gpio";
 9		pinctrl-names = "default";
10		pinctrl-0 = <&m2_gnss_rfkill_pins>;
11		label = "m.2 GNSS";
12		radio-type = "gps";
13		/* rfkill-gpio inverts internally */
14		shutdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
15	};
16
17	/* M.2 is B-keyed, so w-disable is for WWAN */
18	rfkill-m2-wwan {
19		compatible = "rfkill-gpio";
20		pinctrl-names = "default";
21		pinctrl-0 = <&m2_wwan_rfkill_pins>;
22		label = "m.2 WWAN";
23		radio-type = "wwan";
24		/* rfkill-gpio inverts internally */
25		shutdown-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
26	};
27};
28
29&iomuxc {
30	m2_gnss_rfkill_pins: pinctrl-m2-gnss-rfkill-grp {
31		fsl,pins = <
32			/* weak i/o, open drain */
33			MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07		0x20
34		>;
35	};
36
37	m2_reset_pins: pinctrl-m2-reset-grp {
38		fsl,pins = <
39			/*
40			 * 3.3V domain on SoC, set open-drain to ensure
41			 * 1.8V logic on connector
42			 */
43			MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06		0x20
44		>;
45	};
46
47	m2_wwan_rfkill_pins: pinctrl-m2-wwan-rfkill-grp {
48		fsl,pins = <
49			/* weak i/o, open drain */
50			MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13		0x20
51		>;
52	};
53
54	m2_wwan_wake_pins: pinctrl-m2-wwan-wake-grp {
55		fsl,pins = <
56			/* weak i/o, open drain */
57			MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12		0x20
58		>;
59	};
60};