imx8mp-dhcom-som.dtsi

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Copyright (C) 2021-2022 Marek Vasut <marex@denx.de>
   4 */
   5
   6#include "imx8mp.dtsi"
   7
   8/ {
   9	model = "DH electronics i.MX8M Plus DHCOM SoM";
  10	compatible = "dh,imx8mp-dhcom-som", "fsl,imx8mp";
  11
  12	aliases {
  13		ethernet0 = &eqos;
  14		ethernet1 = &fec;
  15		rtc0 = &rv3032;
  16		rtc1 = &snvs_rtc;
  17		spi0 = &flexspi;
  18	};
  19
  20	memory@40000000 {
  21		device_type = "memory";
  22		/* Memory size 512 MiB..8 GiB will be filled by U-Boot */
  23		reg = <0x0 0x40000000 0 0x08000000>;
  24	};
  25
  26	reg_eth_vio: regulator-eth-vio {
  27		compatible = "regulator-fixed";
  28		gpio = <&ioexp 2 GPIO_ACTIVE_LOW>;
  29		regulator-always-on;
  30		regulator-boot-on;
  31		regulator-min-microvolt = <3300000>;
  32		regulator-max-microvolt = <3300000>;
  33		regulator-name = "eth_vio";
  34		vin-supply = <&buck4>;
  35	};
  36
  37	reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
  38		compatible = "regulator-fixed";
  39		enable-active-high;
  40		gpio = <&gpio2 19 0>; /* SD2_RESET */
  41		off-on-delay-us = <12000>;
  42		pinctrl-names = "default";
  43		pinctrl-0 = <&pinctrl_usdhc2_vmmc>;
  44		regulator-max-microvolt = <3300000>;
  45		regulator-min-microvolt = <3300000>;
  46		regulator-name = "VDD_3V3_SD";
  47		startup-delay-us = <100>;
  48		vin-supply = <&buck4>;
  49	};
  50
  51	reg_vdd_3p3v_awo: regulator-vdd-3p3v-awo {	/* VDD_3V3_AWO */
  52		compatible = "regulator-fixed";
  53		regulator-always-on;
  54		regulator-min-microvolt = <3300000>;
  55		regulator-max-microvolt = <3300000>;
  56		regulator-name = "VDD_3P3V_AWO";
  57	};
  58
  59	wlan_pwrseq: wifi-pwrseq {
  60		compatible = "mmc-pwrseq-simple";
  61		reset-gpios = <&ioexp 1 GPIO_ACTIVE_LOW>;
  62	};
  63};
  64
  65&A53_0 {
  66	cpu-supply = <&buck2>;
  67};
  68
  69&A53_1 {
  70	cpu-supply = <&buck2>;
  71};
  72
  73&A53_2 {
  74	cpu-supply = <&buck2>;
  75};
  76
  77&A53_3 {
  78	cpu-supply = <&buck2>;
  79};
  80
  81&audio_blk_ctrl {
  82	assigned-clocks = <&clk IMX8MP_AUDIO_PLL1>;
  83	assigned-clock-rates = <393216000>;
  84};
  85
  86&ecspi1 {
  87	pinctrl-names = "default";
  88	pinctrl-0 = <&pinctrl_ecspi1>;
  89	cs-gpios = <&gpio5 17 GPIO_ACTIVE_LOW>;
  90	status = "disabled";
  91};
  92
  93&ecspi2 {
  94	pinctrl-names = "default";
  95	pinctrl-0 = <&pinctrl_ecspi2>;
  96	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
  97	status = "disabled";
  98};
  99
 100&eqos {	/* First ethernet */
 101	pinctrl-names = "default";
 102	pinctrl-0 = <&pinctrl_eqos_rgmii>;
 103	phy-handle = <&ethphy0g>;
 104	phy-mode = "rgmii-id";
 105	status = "okay";
 106
 107	mdio {
 108		compatible = "snps,dwmac-mdio";
 109		#address-cells = <1>;
 110		#size-cells = <0>;
 111
 112		/* Up to one of these two PHYs may be populated. */
 113		ethphy0f: ethernet-phy@1 { /* SMSC LAN8740Ai */
 114			compatible = "ethernet-phy-id0007.c110",
 115				     "ethernet-phy-ieee802.3-c22";
 116			clocks = <&clk IMX8MP_CLK_ENET_QOS>;
 117			interrupt-parent = <&gpio3>;
 118			interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
 119			pinctrl-0 = <&pinctrl_ethphy0>;
 120			pinctrl-names = "default";
 121			reg = <1>;
 122			reset-assert-us = <1000>;
 123			reset-deassert-us = <1000>;
 124			reset-gpios = <&ioexp 4 GPIO_ACTIVE_LOW>;
 125			/* Non-default PHY population option. */
 126			status = "disabled";
 127		};
 128
 129		ethphy0g: ethernet-phy@5 { /* Micrel KSZ9131RNXI */
 130			compatible = "ethernet-phy-id0022.1642",
 131				     "ethernet-phy-ieee802.3-c22";
 132			interrupt-parent = <&gpio3>;
 133			interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
 134			micrel,led-mode = <0>;
 135			pinctrl-0 = <&pinctrl_ethphy0>;
 136			pinctrl-names = "default";
 137			reg = <5>;
 138			reset-assert-us = <1000>;
 139			reset-deassert-us = <1000>;
 140			reset-gpios = <&ioexp 4 GPIO_ACTIVE_LOW>;
 141			/* Default PHY population option. */
 142			status = "okay";
 143		};
 144	};
 145};
 146
 147&fec {	/* Second ethernet */
 148	pinctrl-names = "default";
 149	pinctrl-0 = <&pinctrl_fec_rmii>;
 150	phy-handle = <&ethphy1f>;
 151	phy-mode = "rmii";
 152	fsl,magic-packet;
 153	status = "okay";
 154
 155	mdio {
 156		#address-cells = <1>;
 157		#size-cells = <0>;
 158
 159		/* Up to one PHY may be populated. */
 160		ethphy1f: ethernet-phy@2 { /* SMSC LAN8740Ai */
 161			compatible = "ethernet-phy-id0007.c110",
 162				     "ethernet-phy-ieee802.3-c22";
 163			interrupt-parent = <&gpio4>;
 164			interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
 165			pinctrl-0 = <&pinctrl_ethphy1>;
 166			pinctrl-names = "default";
 167			reg = <2>;
 168			reset-assert-us = <1000>;
 169			reset-deassert-us = <1000>;
 170			reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
 171			/* Non-default PHY population option. */
 172			status = "disabled";
 173		};
 174	};
 175};
 176
 177&flexcan1 {
 178	pinctrl-names = "default";
 179	pinctrl-0 = <&pinctrl_flexcan1>;
 180	status = "disabled";
 181};
 182
 183&flexcan2 {
 184	pinctrl-names = "default";
 185	pinctrl-0 = <&pinctrl_flexcan2>;
 186	status = "disabled";
 187};
 188
 189&flexspi {
 190	pinctrl-names = "default";
 191	pinctrl-0 = <&pinctrl_flexspi>;
 192	status = "okay";
 193
 194	flash@0 {	/* W25Q128JWPIM */
 195		compatible = "jedec,spi-nor";
 196		reg = <0>;
 197		spi-max-frequency = <80000000>;
 198		spi-tx-bus-width = <4>;
 199		spi-rx-bus-width = <4>;
 200	};
 201};
 202
 203&gpio1 {
 204	gpio-line-names =
 205		"DHCOM-G", "", "", "", "", "DHCOM-I", "DHCOM-J", "DHCOM-L",
 206		"DHCOM-B", "DHCOM-A", "", "DHCOM-H", "", "", "", "",
 207		"", "", "", "", "", "", "", "",
 208		"", "", "", "", "", "", "", "";
 209};
 210
 211&gpio2 {
 212	gpio-line-names =
 213		"", "", "", "", "", "", "", "",
 214		"", "", "", "DHCOM-K", "", "", "", "",
 215		"", "", "", "", "DHCOM-INT", "", "", "",
 216		"", "", "", "", "", "", "", "";
 217};
 218
 219&gpio3 {
 220	gpio-line-names =
 221		"", "", "", "", "", "", "", "",
 222		"", "", "", "", "", "", "SOM-HW0", "",
 223		"", "", "", "", "", "", "SOM-MEM0", "SOM-MEM1",
 224		"SOM-MEM2", "SOM-HW2", "", "", "", "", "", "";
 225};
 226
 227&gpio4 {
 228	gpio-line-names =
 229		"", "", "", "", "", "", "", "",
 230		"", "", "", "", "", "", "", "",
 231		"", "", "", "SOM-HW1", "", "", "", "",
 232		"", "", "", "DHCOM-D", "", "", "", "";
 233};
 234
 235&gpio5 {
 236	gpio-line-names =
 237		"", "", "DHCOM-C", "", "", "", "", "",
 238		"", "", "", "", "", "", "", "",
 239		"", "", "", "", "", "", "DHCOM-E", "DHCOM-F",
 240		"", "", "", "", "", "", "", "";
 241};
 242
 243&i2c3 {
 244	clock-frequency = <100000>;
 245	pinctrl-names = "default", "gpio";
 246	pinctrl-0 = <&pinctrl_i2c3>;
 247	pinctrl-1 = <&pinctrl_i2c3_gpio>;
 248	scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 249	sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 250	status = "okay";
 251
 252	tc_bridge: bridge@f {
 253		compatible = "toshiba,tc9595", "toshiba,tc358767";
 254		pinctrl-names = "default";
 255		pinctrl-0 = <&pinctrl_tc9595>;
 256		reg = <0xf>;
 257		clock-names = "ref";
 258		clocks = <&clk IMX8MP_CLK_CLKOUT2>;
 259		assigned-clocks = <&clk IMX8MP_CLK_CLKOUT2_SEL>,
 260				  <&clk IMX8MP_CLK_CLKOUT2>,
 261				  <&clk IMX8MP_AUDIO_PLL2_OUT>;
 262		assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL2_OUT>;
 263		assigned-clock-rates = <13000000>, <13000000>, <208000000>;
 264		reset-gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>;
 265		status = "disabled";
 266
 267		ports {
 268			#address-cells = <1>;
 269			#size-cells = <0>;
 270
 271			port@0 {
 272				reg = <0>;
 273
 274				tc_bridge_in: endpoint {
 275					data-lanes = <1 2 3 4>;
 276					remote-endpoint = <&dsi_out>;
 277				};
 278			};
 279		};
 280	};
 281
 282	pmic: pmic@25 {
 283		compatible = "nxp,pca9450c";
 284		reg = <0x25>;
 285		pinctrl-names = "default";
 286		pinctrl-0 = <&pinctrl_pmic>;
 287		interrupt-parent = <&gpio1>;
 288		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
 289
 290		/*
 291		 * i.MX 8M Plus Data Sheet for Consumer Products
 292		 * 3.1.4 Operating ranges
 293		 * MIMX8ML8CVNKZAB
 294		 */
 295		regulators {
 296			buck1: BUCK1 {	/* VDD_SOC (dual-phase with BUCK3) */
 297				regulator-min-microvolt = <850000>;
 298				regulator-max-microvolt = <1000000>;
 299				regulator-ramp-delay = <3125>;
 300				regulator-always-on;
 301				regulator-boot-on;
 302			};
 303
 304			buck2: BUCK2 {	/* VDD_ARM */
 305				nxp,dvs-run-voltage = <950000>;
 306				nxp,dvs-standby-voltage = <850000>;
 307				regulator-min-microvolt = <850000>;
 308				regulator-max-microvolt = <1000000>;
 309				regulator-ramp-delay = <3125>;
 310				regulator-always-on;
 311				regulator-boot-on;
 312			};
 313
 314			buck4: BUCK4 {	/* VDD_3V3 */
 315				regulator-min-microvolt = <3300000>;
 316				regulator-max-microvolt = <3300000>;
 317				regulator-always-on;
 318				regulator-boot-on;
 319			};
 320
 321			buck5: BUCK5 {	/* VDD_1V8 */
 322				regulator-min-microvolt = <1800000>;
 323				regulator-max-microvolt = <1800000>;
 324				regulator-always-on;
 325				regulator-boot-on;
 326			};
 327
 328			buck6: BUCK6 {	/* NVCC_DRAM_1V1 */
 329				regulator-min-microvolt = <1100000>;
 330				regulator-max-microvolt = <1100000>;
 331				regulator-always-on;
 332				regulator-boot-on;
 333			};
 334
 335			ldo1: LDO1 {	/* NVCC_SNVS_1V8 */
 336				regulator-min-microvolt = <1800000>;
 337				regulator-max-microvolt = <1800000>;
 338				regulator-always-on;
 339				regulator-boot-on;
 340			};
 341
 342			ldo3: LDO3 {	/* VDDA_1V8 */
 343				regulator-min-microvolt = <1800000>;
 344				regulator-max-microvolt = <1800000>;
 345				regulator-always-on;
 346				regulator-boot-on;
 347			};
 348
 349			ldo4: LDO4 {	/* PMIC_LDO4 */
 350				regulator-min-microvolt = <3300000>;
 351				regulator-max-microvolt = <3300000>;
 352			};
 353
 354			ldo5: LDO5 {	/* NVCC_SD2 */
 355				regulator-min-microvolt = <1800000>;
 356				regulator-max-microvolt = <3300000>;
 357			};
 358		};
 359	};
 360
 361	adc@48 {
 362		compatible = "ti,ads1015";
 363		reg = <0x48>;
 364		interrupts-extended = <&ioexp 7 IRQ_TYPE_EDGE_FALLING>;
 365		#address-cells = <1>;
 366		#size-cells = <0>;
 367
 368		channel@0 {	/* Voltage over AIN0 and AIN1. */
 369			reg = <0>;
 370		};
 371
 372		channel@1 {	/* Voltage over AIN0 and AIN3. */
 373			reg = <1>;
 374		};
 375
 376		channel@2 {	/* Voltage over AIN1 and AIN3. */
 377			reg = <2>;
 378		};
 379
 380		channel@3 {	/* Voltage over AIN2 and AIN3. */
 381			reg = <3>;
 382		};
 383
 384		channel@4 {	/* Voltage over AIN0 and GND. */
 385			reg = <4>;
 386		};
 387
 388		channel@5 {	/* Voltage over AIN1 and GND. */
 389			reg = <5>;
 390		};
 391
 392		channel@6 {	/* Voltage over AIN2 and GND. */
 393			reg = <6>;
 394		};
 395
 396		channel@7 {	/* Voltage over AIN3 and GND. */
 397			reg = <7>;
 398		};
 399	};
 400
 401	touchscreen@49 {
 402		compatible = "ti,tsc2004";
 403		reg = <0x49>;
 404		interrupts-extended = <&gpio4 0 IRQ_TYPE_EDGE_FALLING>;
 405		pinctrl-names = "default";
 406		pinctrl-0 = <&pinctrl_touch>;
 407		vio-supply = <&buck4>;
 408	};
 409
 410	eeprom0: eeprom@50 {	/* EEPROM with EQoS MAC address */
 411		compatible = "atmel,24c32";	/* M24C32-D */
 412		pagesize = <32>;
 413		reg = <0x50>;
 414	};
 415
 416	rv3032: rtc@51 {
 417		compatible = "microcrystal,rv3032";
 418		reg = <0x51>;
 419		interrupts-extended = <&ioexp 3 IRQ_TYPE_EDGE_FALLING>;
 420		wakeup-source;
 421	};
 422
 423	eeprom1: eeprom@53 {	/* EEPROM with FEC MAC address */
 424		compatible = "atmel,24c32";	/* M24C32-D */
 425		pagesize = <32>;
 426		reg = <0x53>;
 427	};
 428
 429	eeprom0wl: eeprom@58 {
 430		compatible = "atmel,24c32d-wl";	/* M24C32-D WL page of 0x50 */
 431		pagesize = <32>;
 432		reg = <0x58>;
 433	};
 434
 435	eeprom1wl: eeprom@5b {
 436		compatible = "atmel,24c32d-wl";	/* M24C32-D WL page of 0x53 */
 437		pagesize = <32>;
 438		reg = <0x5b>;
 439	};
 440
 441	ioexp: gpio@74 {
 442		compatible = "nxp,pca9539";
 443		reg = <0x74>;
 444		gpio-controller;
 445		#gpio-cells = <2>;
 446		interrupts-extended = <&gpio3 20 IRQ_TYPE_LEVEL_LOW>;
 447		interrupt-controller;
 448		#interrupt-cells = <2>;
 449		pinctrl-names = "default";
 450		pinctrl-0 = <&pinctrl_ioexp>;
 451		wakeup-source;
 452
 453		gpio-line-names =
 454			"BT_REG_EN", "WL_REG_EN", "VIO_SWITCHED_#EN", "RTC_#INT",
 455			"ENET_QOS_#RST", "RGB_OSZ_ENABLE", "USB1_ID", "ADC_ALTER_RDY",
 456			"DHCOM-W", "DHCOM-V", "DHCOM-U", "DHCOM-T",
 457			"BT_HOST_WAKE", "BT_DEV_WAKE", "", "";
 458	};
 459};
 460
 461&i2c4 {
 462	clock-frequency = <100000>;
 463	pinctrl-names = "default", "gpio";
 464	pinctrl-0 = <&pinctrl_i2c4>;
 465	pinctrl-1 = <&pinctrl_i2c4_gpio>;
 466	scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 467	sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 468	status = "okay";
 469};
 470
 471&i2c5 {	/* HDMI EDID bus */
 472	clock-frequency = <100000>;
 473	pinctrl-names = "default", "gpio";
 474	pinctrl-0 = <&pinctrl_i2c5>;
 475	pinctrl-1 = <&pinctrl_i2c5_gpio>;
 476	scl-gpios = <&gpio3 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 477	sda-gpios = <&gpio3 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 478	status = "okay";
 479};
 480
 481&mipi_dsi {
 482	samsung,burst-clock-frequency = <160000000>;
 483	samsung,esc-clock-frequency = <10000000>;
 484
 485	ports {
 486		port@1 {
 487			reg = <1>;
 488
 489			dsi_out: endpoint {
 490				data-lanes = <1 2 3 4>;
 491				remote-endpoint = <&tc_bridge_in>;
 492			};
 493		};
 494	};
 495};
 496
 497&pwm1 {
 498	pinctrl-0 = <&pinctrl_pwm1>;
 499	pinctrl-names = "default";
 500	status = "disabled";
 501};
 502
 503&uart1 {
 504	/* CA53 console */
 505	pinctrl-names = "default";
 506	pinctrl-0 = <&pinctrl_uart1>;
 507	status = "okay";
 508	wakeup-source;
 509};
 510
 511&uart2 {
 512	/* Bluetooth */
 513	pinctrl-names = "default";
 514	pinctrl-0 = <&pinctrl_uart2>;
 515	uart-has-rtscts;
 516	status = "okay";
 517
 518	/*
 519	 * PLL1 at 80 MHz supplies UART2 root with 80 MHz clock,
 520	 * which with 16x oversampling yields 5 Mbdps baud base,
 521	 * which can be well divided by 5/4 to achieve 4 Mbdps,
 522	 * which is exactly the maximum rate supported by muRata
 523	 * 2AE bluetooth UART.
 524	 */
 525	assigned-clocks = <&clk IMX8MP_CLK_UART2>;
 526	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
 527	assigned-clock-rates = <80000000>;
 528
 529	bluetooth {
 530		compatible = "cypress,cyw4373a0-bt";
 531		shutdown-gpios = <&ioexp 0 GPIO_ACTIVE_HIGH>;
 532		max-speed = <4000000>;
 533	};
 534};
 535
 536&uart3 {
 537	pinctrl-names = "default";
 538	pinctrl-0 = <&pinctrl_uart3>;
 539	uart-has-rtscts;
 540	status = "okay";
 541};
 542
 543&uart4 {
 544	pinctrl-names = "default";
 545	pinctrl-0 = <&pinctrl_uart4>;
 546	status = "okay";
 547};
 548
 549&usb3_phy0 {
 550	status = "okay";
 551};
 552
 553&usb3_0 {
 554	status = "okay";
 555};
 556
 557&usb_dwc3_0 {
 558	dr_mode = "otg";
 559	status = "okay";
 560};
 561
 562&usb3_phy1 {
 563	status = "okay";
 564};
 565
 566&usb3_1 {
 567	status = "okay";
 568};
 569
 570&usb_dwc3_1 {
 571	pinctrl-names = "default";
 572	pinctrl-0 = <&pinctrl_usb1_vbus>;
 573	dr_mode = "host";
 574	status = "okay";
 575};
 576
 577/* SDIO WiFi */
 578&usdhc1 {
 579	pinctrl-names = "default", "state_100mhz", "state_200mhz";
 580	pinctrl-0 = <&pinctrl_usdhc1>;
 581	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
 582	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
 583	mmc-pwrseq = <&wlan_pwrseq>;
 584	vmmc-supply = <&buck4>;
 585	bus-width = <4>;
 586	non-removable;
 587	cap-power-off-card;
 588	keep-power-in-suspend;
 589	status = "okay";
 590
 591	#address-cells = <1>;
 592	#size-cells = <0>;
 593
 594	brcmf: wifi@1 {	/* muRata 2AE */
 595		reg = <1>;
 596		compatible = "cypress,cyw4373-fmac", "brcm,bcm4329-fmac";
 597		/*
 598		 * The "host-wake" interrupt output is by default not
 599		 * connected to the SoC, but can be connected on to
 600		 * SoC pin on the carrier board.
 601		 */
 602	};
 603};
 604
 605/* SD slot */
 606&usdhc2 {
 607	pinctrl-names = "default", "state_100mhz", "state_200mhz";
 608	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
 609	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
 610	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
 611	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
 612	vmmc-supply = <&reg_usdhc2_vmmc>;
 613	vqmmc-supply = <&ldo5>;
 614	bus-width = <4>;
 615	status = "okay";
 616};
 617
 618/* eMMC */
 619&usdhc3 {
 620	pinctrl-names = "default", "state_100mhz", "state_200mhz";
 621	pinctrl-0 = <&pinctrl_usdhc3>;
 622	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 623	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 624	vmmc-supply = <&buck4>;
 625	vqmmc-supply = <&buck5>;
 626	bus-width = <8>;
 627	non-removable;
 628	status = "okay";
 629};
 630
 631&wdog1 {
 632	pinctrl-names = "default";
 633	pinctrl-0 = <&pinctrl_wdog>;
 634	fsl,ext-reset-output;
 635	status = "okay";
 636};
 637
 638&iomuxc {
 639	pinctrl-0 = <&pinctrl_hog_base
 640		     &pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c
 641		     &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f
 642		     &pinctrl_dhcom_g &pinctrl_dhcom_h &pinctrl_dhcom_i
 643		     &pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l
 644		     &pinctrl_dhcom_m &pinctrl_dhcom_n &pinctrl_dhcom_o
 645		     &pinctrl_dhcom_p &pinctrl_dhcom_q &pinctrl_dhcom_r
 646		     &pinctrl_dhcom_s &pinctrl_dhcom_int>;
 647	pinctrl-names = "default";
 648
 649	pinctrl_dhcom_a: dhcom-a-grp {
 650		fsl,pins = <
 651			/* ENET_QOS_EVENT0-OUT */
 652			MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09		0x2
 653		>;
 654	};
 655
 656	pinctrl_dhcom_b: dhcom-b-grp {
 657		fsl,pins = <
 658			/* ENET_QOS_EVENT0-IN */
 659			MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08		0x2
 660		>;
 661	};
 662
 663	pinctrl_dhcom_c: dhcom-c-grp {
 664		fsl,pins = <
 665			/* GPIO_C */
 666			MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02		0x2
 667		>;
 668	};
 669
 670	pinctrl_dhcom_d: dhcom-d-grp {
 671		fsl,pins = <
 672			/* GPIO_D */
 673			MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27		0x2
 674		>;
 675	};
 676
 677	pinctrl_dhcom_e: dhcom-e-grp {
 678		fsl,pins = <
 679			/* GPIO_E */
 680			MX8MP_IOMUXC_UART1_RXD__GPIO5_IO22		0x2
 681		>;
 682	};
 683
 684	pinctrl_dhcom_f: dhcom-f-grp {
 685		fsl,pins = <
 686			/* GPIO_F */
 687			MX8MP_IOMUXC_UART1_TXD__GPIO5_IO23		0x2
 688		>;
 689	};
 690
 691	pinctrl_dhcom_g: dhcom-g-grp {
 692		fsl,pins = <
 693			/* GPIO_G */
 694			MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00		0x2
 695		>;
 696	};
 697
 698	pinctrl_dhcom_h: dhcom-h-grp {
 699		fsl,pins = <
 700			/* GPIO_H */
 701			MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11		0x2
 702		>;
 703	};
 704
 705	pinctrl_dhcom_i: dhcom-i-grp {
 706		fsl,pins = <
 707			/* CSI1_SYNC */
 708			MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05		0x2
 709		>;
 710	};
 711
 712	pinctrl_dhcom_j: dhcom-j-grp {
 713		fsl,pins = <
 714			/* CSIx_#RST */
 715			MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06		0x2
 716		>;
 717	};
 718
 719	pinctrl_dhcom_k: dhcom-k-grp {
 720		fsl,pins = <
 721			/* CSIx_PWDN */
 722			MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11		0x2
 723		>;
 724	};
 725
 726	pinctrl_dhcom_l: dhcom-l-grp {
 727		fsl,pins = <
 728			/* CSI2_SYNC */
 729			MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07		0x2
 730		>;
 731	};
 732
 733	pinctrl_dhcom_m: dhcom-m-grp {
 734		fsl,pins = <
 735			/* CSIx_MCLK */
 736			MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05		0x2
 737		>;
 738	};
 739
 740	pinctrl_dhcom_n: dhcom-n-grp {
 741		fsl,pins = <
 742			/* CSI2_D3- */
 743			MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09		0x2
 744		>;
 745	};
 746
 747	pinctrl_dhcom_o: dhcom-o-grp {
 748		fsl,pins = <
 749			/* CSI2_D3+ */
 750			MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08		0x2
 751		>;
 752	};
 753
 754	pinctrl_dhcom_p: dhcom-p-grp {
 755		fsl,pins = <
 756			/* CSI2_D2- */
 757			MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10		0x2
 758		>;
 759	};
 760
 761	pinctrl_dhcom_q: dhcom-q-grp {
 762		fsl,pins = <
 763			/* CSI2_D2+ */
 764			MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13		0x2
 765		>;
 766	};
 767
 768	pinctrl_dhcom_r: dhcom-r-grp {
 769		fsl,pins = <
 770			/* CSI2_D1- */
 771			MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12		0x2
 772		>;
 773	};
 774
 775	pinctrl_dhcom_s: dhcom-s-grp {
 776		fsl,pins = <
 777			/* CSI2_D1+ */
 778			MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10		0x2
 779		>;
 780	};
 781
 782	pinctrl_dhcom_int: dhcom-int-grp {
 783		fsl,pins = <
 784			/* INT_HIGHEST_PRIO */
 785			MX8MP_IOMUXC_SD2_WP__GPIO2_IO20			0x2
 786		>;
 787	};
 788
 789	pinctrl_hog_base: dhcom-hog-base-grp {
 790		fsl,pins = <
 791			/* GPIOs for memory coding */
 792			MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22		0x40000080
 793			MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23		0x40000080
 794			MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24		0x40000080
 795			/* GPIOs for hardware coding */
 796			MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14		0x40000080
 797			MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19		0x40000080
 798			MX8MP_IOMUXC_SAI5_MCLK__GPIO3_IO25		0x40000080
 799		>;
 800	};
 801
 802	pinctrl_ecspi1: dhcom-ecspi1-grp {
 803		fsl,pins = <
 804			MX8MP_IOMUXC_I2C1_SCL__ECSPI1_SCLK		0x44
 805			MX8MP_IOMUXC_I2C1_SDA__ECSPI1_MOSI		0x44
 806			MX8MP_IOMUXC_I2C2_SCL__ECSPI1_MISO		0x44
 807			MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17		0x40
 808		>;
 809	};
 810
 811	pinctrl_ecspi2: dhcom-ecspi2-grp {
 812		fsl,pins = <
 813			MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK		0x44
 814			MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI		0x44
 815			MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO		0x44
 816			MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13		0x40
 817		>;
 818	};
 819
 820	pinctrl_eqos_rgmii: dhcom-eqos-rgmii-grp {	/* RGMII */
 821		fsl,pins = <
 822			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC		0x3
 823			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO		0x3
 824			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL	0x1f
 825			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x1f
 826			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0	0x1f
 827			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1	0x1f
 828			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2	0x1f
 829			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3	0x1f
 830			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x91
 831			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL	0x91
 832			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0	0x91
 833			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1	0x91
 834			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2	0x91
 835			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3	0x91
 836		>;
 837	};
 838
 839	pinctrl_eqos_rmii: dhcom-eqos-rmii-grp {	/* RMII */
 840		fsl,pins = <
 841			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC		0x3
 842			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO		0x3
 843			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL	0x1f
 844			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0	0x1f
 845			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1	0x1f
 846			MX8MP_IOMUXC_ENET_RXC__ENET_QOS_RX_ER		0x1f
 847			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL	0x91
 848			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0	0x91
 849			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1	0x91
 850			/* Clock */
 851			MX8MP_IOMUXC_ENET_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK	0x4000001f
 852		>;
 853	};
 854
 855	pinctrl_ethphy0: dhcom-ethphy0-grp {
 856		fsl,pins = <
 857			/* ENET_QOS_#INT Interrupt */
 858			MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19		0x22
 859		>;
 860	};
 861
 862	pinctrl_ethphy1: dhcom-ethphy1-grp {
 863		fsl,pins = <
 864			/* ENET1_#RST Reset */
 865			MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02		0x11
 866			/* ENET1_#INT Interrupt */
 867			MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03		0x11
 868		>;
 869	};
 870
 871	pinctrl_fec_rgmii: dhcom-fec-rgmii-grp {	/* RGMII */
 872		fsl,pins = <
 873			MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK		0x1f
 874			MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x3
 875			MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO		0x3
 876			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0		0x91
 877			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1		0x91
 878			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2		0x91
 879			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3		0x91
 880			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x91
 881			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x91
 882			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0		0x1f
 883			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1		0x1f
 884			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2		0x1f
 885			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3		0x1f
 886			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x1f
 887			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC		0x1f
 888			MX8MP_IOMUXC_SAI1_TXD6__ENET1_RX_ER		0x1f
 889		>;
 890	};
 891
 892	pinctrl_fec_rmii: dhcom-fec-rmii-grp {	/* RMII */
 893		fsl,pins = <
 894			MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x3
 895			MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO		0x3
 896			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0		0x91
 897			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1		0x91
 898			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x91
 899			MX8MP_IOMUXC_SAI1_TXD6__ENET1_RX_ER		0x91
 900			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0		0x1f
 901			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1		0x1f
 902			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x1f
 903			/* Clock */
 904			MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK		0x4000001f
 905		>;
 906	};
 907
 908	pinctrl_flexcan1: dhcom-flexcan1-grp {
 909		fsl,pins = <
 910			MX8MP_IOMUXC_SPDIF_RX__CAN1_RX			0x154
 911			MX8MP_IOMUXC_SPDIF_TX__CAN1_TX			0x154
 912		>;
 913	};
 914
 915	pinctrl_flexcan2: dhcom-flexcan2-grp {
 916		fsl,pins = <
 917			MX8MP_IOMUXC_UART3_RXD__CAN2_TX			0x154
 918			MX8MP_IOMUXC_UART3_TXD__CAN2_RX			0x154
 919		>;
 920	};
 921
 922	pinctrl_flexspi: dhcom-flexspi-grp {
 923		fsl,pins = <
 924			MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK		0x1c2
 925			MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B	0x82
 926			MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00	0x82
 927			MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01	0x82
 928			MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02	0x82
 929			MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03	0x82
 930		>;
 931	};
 932
 933	pinctrl_hdmi: dhcom-hdmi-grp {
 934		fsl,pins = <
 935			MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC		0x154
 936			MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD		0x154
 937		>;
 938	};
 939
 940	pinctrl_i2c3: dhcom-i2c3-grp {
 941		fsl,pins = <
 942			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL			0x40000084
 943			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA			0x40000084
 944		>;
 945	};
 946
 947	pinctrl_i2c3_gpio: dhcom-i2c3-gpio-grp {
 948		fsl,pins = <
 949			MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18		0x84
 950			MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19		0x84
 951		>;
 952	};
 953
 954	pinctrl_i2c4: dhcom-i2c4-grp {
 955		fsl,pins = <
 956			MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL			0x40000084
 957			MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA			0x40000084
 958		>;
 959	};
 960
 961	pinctrl_i2c4_gpio: dhcom-i2c4-gpio-grp {
 962		fsl,pins = <
 963			MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20		0x84
 964			MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21		0x84
 965		>;
 966	};
 967
 968	pinctrl_i2c5: dhcom-i2c5-grp {
 969		fsl,pins = <
 970			MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL		0x40000084
 971			MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA		0x40000084
 972		>;
 973	};
 974
 975	pinctrl_i2c5_gpio: dhcom-i2c5-gpio-grp {
 976		fsl,pins = <
 977			MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26		0x84
 978			MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27		0x84
 979		>;
 980	};
 981
 982	pinctrl_ioexp: dhcom-ioexp-grp {
 983		fsl,pins = <
 984			/* #GPIO_EXP_INT */
 985			MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20		0x22
 986		>;
 987	};
 988
 989	pinctrl_pmic: dhcom-pmic-grp {
 990		fsl,pins = <
 991			/* PMIC_nINT */
 992			MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03		0x40000090
 993		>;
 994	};
 995
 996	pinctrl_pwm1: dhcom-pwm1-grp {
 997		fsl,pins = <
 998			MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT		0x6
 999		>;
1000	};
1001
1002	pinctrl_tc9595: dhcom-tc9595-grp {
1003		fsl,pins = <
1004			/* RESET_DSIBRIDGE */
1005			MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01		0x40000146
1006			/* DSI-CONV_INT Interrupt */
1007			MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21		0x141
1008		>;
1009	};
1010
1011	pinctrl_sai3: dhcom-sai3-grp {
1012		fsl,pins = <
1013			MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC	0xd6
1014			MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK	0xd6
1015			MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00	0xd6
1016			MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00	0xd6
1017		>;
1018	};
1019
1020	pinctrl_touch: dhcom-touch-grp {
1021		fsl,pins = <
1022			/* #TOUCH_INT */
1023			MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00		0x40000080
1024		>;
1025	};
1026
1027	pinctrl_uart1: dhcom-uart1-grp {
1028		fsl,pins = <
1029			/* Console UART */
1030			MX8MP_IOMUXC_SAI2_RXC__UART1_DCE_RX		0x49
1031			MX8MP_IOMUXC_SAI2_RXFS__UART1_DCE_TX		0x49
1032			MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS		0x49
1033			MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS		0x49
1034		>;
1035	};
1036
1037	pinctrl_uart2: dhcom-uart2-grp {
1038		fsl,pins = <
1039			/* Bluetooth UART */
1040			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX		0x49
1041			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX		0x49
1042			MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS		0x49
1043			MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS		0x49
1044		>;
1045	};
1046
1047	pinctrl_uart3: dhcom-uart3-grp {
1048		fsl,pins = <
1049			MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX		0x49
1050			MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX		0x49
1051			MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS		0x49
1052			MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS		0x49
1053		>;
1054	};
1055
1056	pinctrl_uart4: dhcom-uart4-grp {
1057		fsl,pins = <
1058			MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX		0x49
1059			MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX		0x49
1060		>;
1061	};
1062
1063	pinctrl_usb1_vbus: dhcom-usb1-grp {
1064		fsl,pins = <
1065			MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR		0x6
1066			MX8MP_IOMUXC_GPIO1_IO15__USB2_OTG_OC		0x80
1067		>;
1068	};
1069
1070	pinctrl_usdhc1: dhcom-usdhc1-grp {
1071		fsl,pins = <
1072			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK		0x190
1073			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD		0x1d0
1074			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0		0x1d0
1075			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1		0x1d0
1076			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2		0x1d0
1077			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3		0x1d0
1078		>;
1079	};
1080
1081	pinctrl_usdhc1_100mhz: dhcom-usdhc1-100mhz-grp {
1082		fsl,pins = <
1083			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK		0x194
1084			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD		0x1d4
1085			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0		0x1d4
1086			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1		0x1d4
1087			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2		0x1d4
1088			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3		0x1d4
1089		>;
1090	};
1091
1092	pinctrl_usdhc1_200mhz: dhcom-usdhc1-200mhz-grp {
1093		fsl,pins = <
1094			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK		0x196
1095			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD		0x1d6
1096			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0		0x1d6
1097			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1		0x1d6
1098			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2		0x1d6
1099			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3		0x1d6
1100		>;
1101	};
1102
1103	pinctrl_usdhc2: dhcom-usdhc2-grp {
1104		fsl,pins = <
1105			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x190
1106			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d0
1107			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d0
1108			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d0
1109			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d0
1110			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d0
1111			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0xc1
1112		>;
1113	};
1114
1115	pinctrl_usdhc2_100mhz: dhcom-usdhc2-100mhz-grp {
1116		fsl,pins = <
1117			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x194
1118			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d4
1119			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d4
1120			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d4
1121			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d4
1122			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d4
1123			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0xc1
1124		>;
1125	};
1126
1127	pinctrl_usdhc2_200mhz: dhcom-usdhc2-200mhz-grp {
1128		fsl,pins = <
1129			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x196
1130			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d6
1131			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d6
1132			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d6
1133			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d6
1134			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d6
1135			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0xc1
1136		>;
1137	};
1138
1139	pinctrl_usdhc2_vmmc: dhcom-usdhc2-vmmc-grp {
1140		fsl,pins = <
1141			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19		0x20
1142		>;
1143	};
1144
1145	pinctrl_usdhc2_gpio: dhcom-usdhc2-gpio-grp {
1146		fsl,pins = <
1147			MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12		0x40000080
1148		>;
1149	};
1150
1151	pinctrl_usdhc3: dhcom-usdhc3-grp {
1152		fsl,pins = <
1153			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x190
1154			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d0
1155			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d0
1156			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d0
1157			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d0
1158			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d0
1159			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d0
1160			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d0
1161			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d0
1162			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d0
1163			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x190
1164			MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B	0x141
1165		>;
1166	};
1167
1168	pinctrl_usdhc3_100mhz: dhcom-usdhc3-100mhz-grp {
1169		fsl,pins = <
1170			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x194
1171			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d4
1172			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d4
1173			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d4
1174			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d4
1175			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d4
1176			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d4
1177			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d4
1178			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d4
1179			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d4
1180			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x194
1181			MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B	0x141
1182		>;
1183	};
1184
1185	pinctrl_usdhc3_200mhz: dhcom-usdhc3-200mhz-grp {
1186		fsl,pins = <
1187			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x196
1188			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d6
1189			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d6
1190			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d6
1191			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d6
1192			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d6
1193			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d6
1194			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d6
1195			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d6
1196			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d6
1197			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x196
1198			MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B	0x141
1199		>;
1200	};
1201
1202	pinctrl_wdog: dhcom-wdog-grp {
1203		fsl,pins = <
1204			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B		0xc6
1205		>;
1206	};
1207};