imx8mp-aristainetos3a-som-v1.dtsi

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Copyright (C) 2024 Heiko Schocher <hs@denx.de>
   4 */
   5
   6#include <dt-bindings/leds/common.h>
   7#include <dt-bindings/net/ti-dp83867.h>
   8#include <dt-bindings/phy/phy-imx8-pcie.h>
   9#include <dt-bindings/pwm/pwm.h>
  10#include "imx8mp.dtsi"
  11
  12/ {
  13	model = "ADLINK LEC-iMX8MP-Q-N-4G-32G";
  14	compatible = "abb,imx8mp-aristanetos3-som", "fsl,imx8mp";
  15
  16	aliases {
  17		ethernet0 = &eqos;
  18		ethernet1 = &fec;
  19		mmc0 = &usdhc3;	/* eMMC */
  20		mmc1 = &usdhc2;	/* MicroSD */
  21	};
  22
  23	chosen {
  24		bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200";
  25		stdout-path = &uart2;
  26	};
  27
  28	connector {
  29		compatible = "usb-c-connector";
  30		label = "USB-C";
  31
  32		port {
  33			usb_dr_connector: endpoint {
  34				remote-endpoint = <&usb3_dwc>;
  35			};
  36		};
  37	};
  38
  39	gpio-leds {
  40		compatible = "gpio-leds";
  41		pinctrl-names = "default";
  42		pinctrl-0 = <&pinctrl_gpio_led>;
  43
  44		led-0 {
  45			function = LED_FUNCTION_STATUS;
  46			color = <LED_COLOR_ID_YELLOW>;
  47			function-enumerator = <0>;
  48			gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
  49			default-state = "on";
  50		};
  51	};
  52
  53	lvds_backlight: backlight {
  54		compatible = "pwm-backlight";
  55		pinctrl-names = "default";
  56		pinctrl-0 = <&pinctrl_lvds_bklt_en>;
  57		pwms = <&pwm2 0 50000 0>;
  58		enable-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
  59		brightness-levels = <0 100>;
  60		num-interpolated-steps = <100>;
  61		default-brightness-level = <80>;
  62		status = "disabled";
  63	};
  64
  65	memory@40000000 {
  66		device_type = "memory";
  67		/* Memory size 512 MiB..8 GiB will be filled by U-Boot */
  68		reg = <0x0 0x40000000 0 0x08000000>;
  69	};
  70
  71	pcie0_refclk: clock-pcie-ref {
  72		compatible = "fixed-clock";
  73		#clock-cells = <0>;
  74		clock-frequency = <100000000>;
  75	};
  76
  77	reg_can1_stby: regulator-can1-stby {
  78		compatible = "regulator-fixed";
  79		pinctrl-names = "default";
  80		pinctrl-0 = <&pinctrl_flexcan1_reg>;
  81		gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>;
  82		enable-active-high;
  83		regulator-max-microvolt = <3300000>;
  84		regulator-min-microvolt = <3300000>;
  85		regulator-name = "can1-stby";
  86	};
  87
  88	reg_can2_stby: regulator-can2-stby {
  89		compatible = "regulator-fixed";
  90		pinctrl-names = "default";
  91		pinctrl-0 = <&pinctrl_flexcan2_reg>;
  92		enable-active-high;
  93		gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
  94		regulator-max-microvolt = <3300000>;
  95		regulator-min-microvolt = <3300000>;
  96		regulator-name = "can2-stby";
  97	};
  98
  99	reg_dp83867_2v5: regulator-enet {
 100		compatible = "regulator-fixed";
 101		enable-active-high;
 102		gpio = <&gpio7 15 GPIO_ACTIVE_HIGH>;
 103		regulator-max-microvolt = <1800000>;
 104		regulator-min-microvolt = <1800000>;
 105		regulator-name = "enet_2v5";
 106		regulator-boot-on;
 107		regulator-always-on;
 108	};
 109
 110	reg_usb1_host_vbus: regulator-usb1-vbus {
 111		compatible = "regulator-fixed";
 112		pinctrl-names = "default";
 113		pinctrl-0 = <&pinctrl_usb1_vbus>;
 114		enable-active-high;
 115		gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
 116		regulator-max-microvolt = <5000000>;
 117		regulator-min-microvolt = <5000000>;
 118		regulator-name = "usb1_host_vbus";
 119		regulator-always-on;
 120	};
 121
 122	reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
 123		compatible = "regulator-fixed";
 124		pinctrl-names = "default";
 125		pinctrl-0 = <&pinctrl_usdhc2_vmmc>;
 126		enable-active-high;
 127		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; /* SD2_RESET */
 128		regulator-max-microvolt = <3300000>;
 129		regulator-min-microvolt = <3300000>;
 130		regulator-name = "VDD_3V3_SD";
 131		off-on-delay-us = <12000>;
 132		startup-delay-us = <100>;
 133		vin-supply = <&buck4>;
 134	};
 135};
 136
 137&A53_0 {
 138	cpu-supply = <&buck2>;
 139};
 140
 141&A53_1 {
 142	cpu-supply = <&buck2>;
 143};
 144
 145&A53_2 {
 146	cpu-supply = <&buck2>;
 147};
 148
 149&A53_3 {
 150	cpu-supply = <&buck2>;
 151};
 152
 153&clk {
 154	clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
 155		 <&clk_ext3>, <&clk_ext4>;
 156	clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
 157		      "clk_ext3", "clk_ext4";
 158	assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
 159			  <&clk IMX8MP_CLK_A53_CORE>,
 160			  <&clk IMX8MP_CLK_NOC>,
 161			  <&clk IMX8MP_CLK_NOC_IO>,
 162			  <&clk IMX8MP_CLK_GIC>,
 163			  <&clk IMX8MP_CLK_AUDIO_AHB>,
 164			  <&clk IMX8MP_CLK_AUDIO_AXI_SRC>,
 165			  <&clk IMX8MP_AUDIO_PLL1>,
 166			  <&clk IMX8MP_AUDIO_PLL2>,
 167			  <&clk IMX8MP_VIDEO_PLL1>;
 168};
 169
 170&ecspi1 {
 171	pinctrl-names = "default";
 172	pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs2>;
 173	cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW &gpio1 6 GPIO_ACTIVE_LOW>;
 174	status = "okay";
 175};
 176
 177&ecspi2 {
 178	pinctrl-names = "default";
 179	pinctrl-0 = <&pinctrl_ecspi2>;
 180	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
 181	status = "okay";
 182};
 183
 184/* eth0 */
 185&eqos {
 186	pinctrl-names = "default";
 187	pinctrl-0 = <&pinctrl_eqos_rgmii>;
 188	phy-handle = <&ethphy0>;
 189	phy-mode = "rgmii-id";
 190	snps,force_thresh_dma_mode;
 191	snps,mtl-tx-config = <&mtl_tx_setup>;
 192	snps,mtl-rx-config = <&mtl_rx_setup>;
 193	status = "okay";
 194
 195	mdio {
 196		compatible = "snps,dwmac-mdio";
 197		#address-cells = <1>;
 198		#size-cells = <0>;
 199
 200		ethphy0: eqos-ethernet-phy@0 {
 201			compatible = "ethernet-phy-ieee802.3-c22";
 202			reg = <0>;
 203			ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_75_NS>;
 204			ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_75_NS>;
 205			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
 206			ti,min-output-impedance;
 207			ti,dp83867-rxctrl-strap-quirk;
 208			interrupt-parent = <&gpio4>;
 209			interrupts = <21 IRQ_TYPE_EDGE_FALLING>;
 210			reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
 211		};
 212	};
 213
 214	mtl_tx_setup: tx-queues-config {
 215		snps,tx-queues-to-use = <5>;
 216
 217		queue0 {
 218			snps,dcb-algorithm;
 219			snps,priority = <0x1>;
 220		};
 221
 222		queue1 {
 223			snps,dcb-algorithm;
 224			snps,priority = <0x2>;
 225		};
 226
 227		queue2 {
 228			snps,dcb-algorithm;
 229			snps,priority = <0x4>;
 230		};
 231
 232		queue3 {
 233			snps,dcb-algorithm;
 234			snps,priority = <0x8>;
 235		};
 236
 237		queue4 {
 238			snps,dcb-algorithm;
 239			snps,priority = <0xf0>;
 240		};
 241	};
 242
 243	mtl_rx_setup: rx-queues-config {
 244		snps,rx-queues-to-use = <5>;
 245
 246		queue0 {
 247			snps,dcb-algorithm;
 248			snps,priority = <0x1>;
 249			snps,map-to-dma-channel = <0>;
 250		};
 251
 252		queue1 {
 253			snps,dcb-algorithm;
 254			snps,priority = <0x2>;
 255			snps,map-to-dma-channel = <1>;
 256		};
 257
 258		queue2 {
 259			snps,dcb-algorithm;
 260			snps,priority = <0x4>;
 261			snps,map-to-dma-channel = <2>;
 262		};
 263
 264		queue3 {
 265			snps,dcb-algorithm;
 266			snps,priority = <0x8>;
 267			snps,map-to-dma-channel = <3>;
 268		};
 269
 270		queue4 {
 271			snps,dcb-algorithm;
 272			snps,priority = <0xf0>;
 273			snps,map-to-dma-channel = <4>;
 274		};
 275	};
 276};
 277
 278/* eth1 */
 279&fec {
 280	pinctrl-names = "default";
 281	pinctrl-0 = <&pinctrl_fec_rgmii>;
 282	phy-handle = <&ethphy1>;
 283	phy-mode = "rgmii-id";
 284	fsl,magic-packet;
 285	status = "okay";
 286
 287	mdio {
 288		#address-cells = <1>;
 289		#size-cells = <0>;
 290
 291		ethphy1: ethernet-phy@1 {
 292			compatible = "ethernet-phy-ieee802.3-c22";
 293			reg = <1>;
 294			interrupt-parent = <&gpio4>;
 295			interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
 296			reset-gpio = <&gpio4 2 GPIO_ACTIVE_LOW>;
 297			ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_75_NS>;
 298			ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_75_NS>;
 299			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
 300			ti,min-output-impedance;
 301			ti,dp83867-rxctrl-strap-quirk;
 302			eee-broken-1000t;
 303		};
 304	};
 305};
 306
 307&flexcan1 {
 308	pinctrl-names = "default";
 309	pinctrl-0 = <&pinctrl_flexcan1>;
 310	xceiver-supply = <&reg_can1_stby>;
 311	status = "disabled";
 312};
 313
 314&flexcan2 {
 315	pinctrl-names = "default";
 316	pinctrl-0 = <&pinctrl_flexcan2>;
 317	xceiver-supply = <&reg_can1_stby>;
 318	status = "disabled";
 319};
 320
 321&hdmi_blk_ctrl {
 322	status = "okay";
 323};
 324
 325&hdmi_pvi {
 326	status = "okay";
 327};
 328
 329&hdmi_tx {
 330	pinctrl-names = "default";
 331	pinctrl-0 = <&pinctrl_hdmi>;
 332	status = "okay";
 333};
 334
 335&hdmi_tx_phy {
 336	status = "okay";
 337};
 338
 339&i2c1 {
 340	clock-frequency = <100000>;
 341	pinctrl-names = "default", "gpio";
 342	pinctrl-0 = <&pinctrl_i2c1>;
 343	pinctrl-1 = <&pinctrl_i2c1_gpio>;
 344	scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
 345	sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
 346	status = "okay";
 347
 348	pmic: pmic@25 {
 349		compatible = "nxp,pca9450c";
 350		reg = <0x25>;
 351		pinctrl-names = "default";
 352		pinctrl-0 = <&pinctrl_pmic>;
 353		interrupt-parent = <&gpio1>;
 354		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
 355
 356		/*
 357		 * i.MX 8M Plus Data Sheet for Consumer Products
 358		 * 3.1.4 Operating ranges
 359		 * MIMX8ML8CVNKZAB
 360		 */
 361		regulators {
 362			buck1: BUCK1 {	/* VDD_SOC (dual-phase with BUCK3) */
 363				regulator-name = "buck1";
 364				regulator-min-microvolt = <600000>;
 365				regulator-max-microvolt = <2187500>;
 366				regulator-ramp-delay = <3125>;
 367				regulator-always-on;
 368				regulator-boot-on;
 369			};
 370
 371			buck2: BUCK2 {	/* VDD_ARM */
 372				regulator-name = "buck2";
 373				nxp,dvs-run-voltage = <950000>;
 374				nxp,dvs-standby-voltage = <850000>;
 375				regulator-min-microvolt = <600000>;
 376				regulator-max-microvolt = <2187500>;
 377				regulator-ramp-delay = <3125>;
 378				regulator-always-on;
 379				regulator-boot-on;
 380			};
 381
 382			buck4: BUCK4 {	/* VDD_3V3 */
 383				regulator-name = "buck4";
 384				regulator-min-microvolt = <600000>;
 385				regulator-max-microvolt = <3300000>;
 386				regulator-always-on;
 387				regulator-boot-on;
 388			};
 389
 390			buck5: BUCK5 {	/* VDD_1V8 */
 391				regulator-name = "buck5";
 392				regulator-min-microvolt = <600000>;
 393				regulator-max-microvolt = <3400000>;
 394				regulator-always-on;
 395				regulator-boot-on;
 396			};
 397
 398			buck6: BUCK6 {	/* NVCC_DRAM_1V1 */
 399				regulator-name = "buck6";
 400				regulator-min-microvolt = <600000>;
 401				regulator-max-microvolt = <3400000>;
 402				regulator-always-on;
 403				regulator-boot-on;
 404			};
 405
 406			ldo1: LDO1 {	/* NVCC_SNVS_1V8 */
 407				regulator-name = "ldo1";
 408				regulator-min-microvolt = <1600000>;
 409				regulator-max-microvolt = <3300000>;
 410				regulator-always-on;
 411				regulator-boot-on;
 412			};
 413
 414			ldo2: LDO2 {	/* VDDA_1V8 */
 415				regulator-name = "ldo2";
 416				regulator-min-microvolt = <800000>;
 417				regulator-max-microvolt = <1150000>;
 418				regulator-always-on;
 419				regulator-boot-on;
 420			};
 421
 422			ldo3: LDO3 {	/* VDDA_1V8 */
 423				regulator-name = "ldo3";
 424				regulator-min-microvolt = <800000>;
 425				regulator-max-microvolt = <3300000>;
 426				regulator-always-on;
 427				regulator-boot-on;
 428			};
 429
 430			ldo4: LDO4 {	/* PMIC_LDO4 */
 431				regulator-name = "ldo4";
 432				regulator-min-microvolt = <800000>;
 433				regulator-max-microvolt = <3300000>;
 434				regulator-always-on;
 435				regulator-boot-on;
 436			};
 437
 438			ldo5: LDO5 {	/* NVCC_SD2 */
 439				regulator-name = "ldo5";
 440				regulator-min-microvolt = <1800000>;
 441				regulator-max-microvolt = <3300000>;
 442			};
 443		};
 444	};
 445};
 446
 447&i2c2 {
 448	clock-frequency = <400000>;
 449	pinctrl-names = "default", "gpio";
 450	pinctrl-0 = <&pinctrl_i2c2>;
 451	pinctrl-1 = <&pinctrl_i2c2_gpio>;
 452	scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>;
 453	sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
 454	status = "okay";
 455};
 456
 457&i2c3 {
 458	clock-frequency = <100000>;
 459	pinctrl-names = "default", "gpio";
 460	pinctrl-0 = <&pinctrl_i2c3>;
 461	pinctrl-1 = <&pinctrl_i2c3_gpio>;
 462	scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
 463	sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>;
 464	status = "okay";
 465};
 466
 467&i2c5 {
 468	#address-cells = <1>;
 469	clock-frequency = <100000>;
 470	pinctrl-names = "default";
 471	pinctrl-0 = <&pinctrl_i2c5>;
 472	status = "okay";
 473};
 474
 475&i2c6 {
 476	clock-frequency = <100000>;
 477	pinctrl-names = "default", "gpio";
 478	pinctrl-0 = <&pinctrl_i2c6>;
 479	pinctrl-1 = <&pinctrl_i2c6_gpio>;
 480	scl-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
 481	sda-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
 482	status = "okay";
 483
 484	/* TPM - ST33TPHF2XI2C U2301 */
 485	tpm: tpm@2e {
 486		pinctrl-names = "default";
 487		pinctrl-0 = <&pinctrl_tpm_irq>;
 488		compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c";
 489		reg = <0x2e>;
 490
 491		label = "tpm";
 492		interrupt-parent = <&gpio3>;
 493		interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
 494		reset-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
 495		status = "okay";
 496	};
 497
 498	/* SX1509(0) U2605 */
 499	gpio6: pinctrl@3f {
 500		compatible = "semtech,sx1509q";
 501		reg = <0x3f>;
 502		#gpio-cells = <2>;
 503		#interrupt-cells = <2>;
 504		semtech,probe-reset;
 505		gpio-controller;
 506		interrupt-controller;
 507		interrupt-parent = <&gpio1>;
 508		interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
 509	};
 510
 511	/* RTC U2607 */
 512	rtc0: rtc@51 {
 513		compatible = "nxp,pcf8563";
 514		reg = <0x51>;
 515		#clock-cells = <0>;
 516	};
 517
 518	/* SX1509(1) U2606 */
 519	gpio7: pinctrl@70 {
 520		compatible = "semtech,sx1509q";
 521		reg = <0x70>;
 522		#gpio-cells = <2>;
 523		#interrupt-cells = <2>;
 524		semtech,probe-reset;
 525		gpio-controller;
 526		interrupt-controller;
 527		interrupt-parent = <&gpio4>;
 528		interrupts = <19 IRQ_TYPE_EDGE_FALLING>;
 529
 530		gpio6-cfg {
 531			pins = "gpio6";
 532			output-high;
 533		};
 534
 535		gpio7-cfg {
 536			pins = "gpio7";
 537			output-high;
 538		};
 539	};
 540};
 541
 542&irqsteer_hdmi {
 543	status = "okay";
 544};
 545
 546&lcdif1 {
 547	status = "disabled";
 548};
 549
 550&lcdif2 {
 551	status = "disabled";
 552};
 553
 554/* HDMI */
 555&lcdif3 {
 556	status = "okay";
 557
 558};
 559
 560&lvds_bridge {
 561	status = "disabled";
 562};
 563
 564&mipi_dsi {
 565	status = "disabled";
 566};
 567
 568&pcie {
 569	pinctrl-names = "default";
 570	pinctrl-0 = <&pinctrl_pcie>;
 571	reset-gpio = <&gpio4 20 GPIO_ACTIVE_LOW>;
 572	fsl,tx-deemph-gen1 = <0x1f>;
 573	fsl,max-link-speed = <3>;
 574	status = "okay";
 575};
 576
 577&pcie_phy {
 578	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
 579	clocks = <&pcie0_refclk>;
 580	clock-names = "ref";
 581	status = "okay";
 582};
 583
 584&pwm1 {
 585	pinctrl-names = "default";
 586	pinctrl-0 = <&pinctrl_pwm1>;
 587	status = "okay";
 588};
 589
 590&pwm2 {
 591	pinctrl-names = "default";
 592	pinctrl-0 = <&pinctrl_pwm2>;
 593	#pwm-cells = <3>;
 594	status = "okay";
 595};
 596
 597&snvs_pwrkey {
 598	status = "okay";
 599};
 600
 601&uart1 {
 602	pinctrl-names = "default";
 603	pinctrl-0 = <&pinctrl_uart1>;
 604	status = "okay";
 605};
 606
 607&uart2 {
 608	pinctrl-names = "default";
 609	pinctrl-0 = <&pinctrl_uart2>;
 610	status = "okay";
 611};
 612
 613&uart3 {
 614	pinctrl-names = "default";
 615	pinctrl-0 = <&pinctrl_uart3>;
 616	status = "okay";
 617};
 618
 619&uart4 {
 620	pinctrl-names = "default";
 621	pinctrl-0 = <&pinctrl_uart4>;
 622	status = "okay";
 623};
 624
 625&usb3_phy0 {
 626	status = "okay";
 627};
 628
 629&usb3_0 {
 630	status = "okay";
 631};
 632
 633&usb_dwc3_0 {
 634	adp-disable;
 635	hnp-disable;
 636	srp-disable;
 637	dr_mode = "otg";
 638	usb-role-switch;
 639	role-switch-default-mode = "peripheral";
 640	status = "okay";
 641
 642	port {
 643		usb3_dwc: endpoint {
 644			remote-endpoint = <&usb_dr_connector>;
 645		};
 646	};
 647};
 648
 649&usb3_phy1 {
 650	status = "okay";
 651};
 652
 653&usb3_1 {
 654	status = "okay";
 655};
 656
 657&usb_dwc3_1 {
 658	dr_mode = "host";
 659	status = "okay";
 660};
 661
 662&usdhc1 {
 663	pinctrl-names = "default", "state_100mhz", "state_200mhz";
 664	pinctrl-0 = <&pinctrl_usdhc1>;
 665	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
 666	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
 667	bus-width = <4>;
 668	non-removable;
 669	status = "okay";
 670};
 671
 672/* SD slot */
 673&usdhc2 {
 674	pinctrl-names = "default", "state_100mhz", "state_200mhz";
 675	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
 676	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
 677	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
 678	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
 679	vmmc-supply = <&reg_usdhc2_vmmc>;
 680	bus-width = <4>;
 681	status = "okay";
 682};
 683
 684/* eMMC */
 685&usdhc3 {
 686	pinctrl-names = "default", "state_100mhz", "state_200mhz";
 687	pinctrl-0 = <&pinctrl_usdhc3>;
 688	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 689	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 690	vmmc-supply = <&buck4>;
 691	vqmmc-supply = <&buck5>;
 692	bus-width = <8>;
 693	non-removable;
 694	status = "okay";
 695};
 696
 697&wdog1 {
 698	pinctrl-names = "default";
 699	pinctrl-0 = <&pinctrl_wdog>;
 700	fsl,ext-reset-output;
 701	status = "okay";
 702};
 703
 704&iomuxc {
 705	pinctrl_ecspi1: aristainetos3-ecspi1-grp {
 706		fsl,pins = <
 707			MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK		0x82
 708			MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI		0x82
 709			MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO		0x82
 710			MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09		0x40000
 711		>;
 712	};
 713
 714	pinctrl_ecspi1_cs2: aristainetos3-ecspi1-cs2-grp {
 715		fsl,pins = <
 716			MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06		0x40000
 717		>;
 718	};
 719
 720	pinctrl_ecspi2: aristainetos3-ecspi2-grp {
 721		fsl,pins = <
 722			MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK		0x82
 723			MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI		0x82
 724			MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO		0x82
 725			MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13		0x40000
 726		>;
 727	};
 728
 729	pinctrl_eqos_rgmii: aristainetos3-eqos-rgmii-grp {
 730		fsl,pins = <
 731			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC				0x3
 732			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO				0x3
 733			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0			0x91
 734			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1			0x91
 735			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2			0x91
 736			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3			0x91
 737			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x91
 738			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL			0x91
 739			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0			0x1f
 740			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1			0x1f
 741			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2			0x1f
 742			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3			0x1f
 743			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL			0x1f
 744			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x1f
 745			MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22				0x19
 746		>;
 747	};
 748
 749	pinctrl_fec_rgmii: aristainetos3-fec-rgmii-grp {
 750		fsl,pins = <
 751			MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x3
 752			MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO		0x3
 753			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0		0x91
 754			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1		0x91
 755			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2		0x91
 756			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3		0x91
 757			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x91
 758			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x91
 759			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0		0x1f
 760			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1		0x1f
 761			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2		0x1f
 762			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3		0x1f
 763			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x1f
 764			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC		0x1f
 765			MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02		0x19
 766		>;
 767	};
 768
 769	pinctrl_flexcan1: aristainetos3-flexcan1-grp {
 770		fsl,pins = <
 771			MX8MP_IOMUXC_SPDIF_RX__CAN1_RX			0x154
 772			MX8MP_IOMUXC_SPDIF_TX__CAN1_TX			0x154
 773		>;
 774	};
 775
 776	pinctrl_flexcan1_reg: aristainetos3-flexcan1-reg-grp {
 777		fsl,pins = <
 778			MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05  0x154
 779		>;
 780	};
 781
 782	pinctrl_flexcan2: aristainetos3-flexcan2-grp {
 783		fsl,pins = <
 784			MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX         0x154
 785			MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX         0x154
 786		>;
 787	};
 788
 789	pinctrl_flexcan2_reg: aristainetos3-flexcan2-reg-grp {
 790		fsl,pins = <
 791			MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27      0x154
 792		>;
 793	};
 794
 795	pinctrl_gpio3_hog: aristainetos3-gpio3-hog-grp {
 796		fsl,pins = <
 797			MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23	0xd6
 798		>;
 799	};
 800
 801	pinctrl_gpio_led: aristainetos3-gpio-led-grp {
 802		fsl,pins = <
 803			MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16	0x19
 804		>;
 805	};
 806
 807	pinctrl_gpio_proton2s: aristainetos3-gpio-proton2s-grp {
 808		fsl,pins = <
 809			MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07	0x19
 810		>;
 811	};
 812
 813	pinctrl_hdmi: aristainetos3-hdmi-grp {
 814		fsl,pins = <
 815			MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL	0x400001c3
 816			MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA	0x400001c3
 817			MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD		0x40000019
 818			MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC		0x40000019
 819		>;
 820	};
 821
 822	pinctrl_i2c1: aristainetos3-i2c1-grp {
 823		fsl,pins = <
 824			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL		0x400001c3
 825			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA		0x400001c3
 826		>;
 827	};
 828
 829	pinctrl_i2c1_gpio: aristainetos3-i2c1-gpio-grp {
 830		fsl,pins = <
 831			MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14	0x1c3
 832			MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15	0x1c3
 833		>;
 834	};
 835
 836	pinctrl_i2c2: aristainetos3-i2c2-grp {
 837		fsl,pins = <
 838			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL		0x400001c3
 839			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA		0x400001c3
 840		>;
 841	};
 842
 843	pinctrl_i2c2_gpio: aristainetos3-i2c2-gpio-grp {
 844		fsl,pins = <
 845			MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16	0x1c3
 846			MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17	0x1c3
 847		>;
 848	};
 849
 850	pinctrl_i2c3: aristainetos3-i2c3-grp {
 851		fsl,pins = <
 852			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL		0x400001c3
 853			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA		0x400001c3
 854		>;
 855	};
 856
 857	pinctrl_i2c3_gpio: aristainetos3-i2c3-gpio-grp {
 858		fsl,pins = <
 859			MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18	0x1c3
 860			MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19	0x1c3
 861		>;
 862	};
 863
 864	pinctrl_i2c5: aristainetos3-i2c5-grp {
 865		fsl,pins = <
 866			MX8MP_IOMUXC_SAI5_RXD0__I2C5_SCL	0x400001c3
 867			MX8MP_IOMUXC_SAI5_MCLK__I2C5_SDA	0x400001c3
 868		>;
 869	};
 870
 871	pinctrl_i2c6: aristainetos3-i2c6-grp {
 872		fsl,pins = <
 873			MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL	0x400001c3
 874			MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA		0x400001c3
 875		>;
 876	};
 877
 878	pinctrl_i2c6_gpio: aristainetos3-i2c6-gpio-grp {
 879		fsl,pins = <
 880			MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19	0x1c3
 881			MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20	0x1c3
 882		>;
 883	};
 884
 885	pinctrl_lcd0_vcc_en: aristainetos3-lcd0-vcc-en-grp {
 886		fsl,pins = <
 887			MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13	0xd6
 888		>;
 889	};
 890
 891	pinctrl_lvds_bklt_en: aristainetos3-lvds-bklt-en-grp {
 892		fsl,pins = <
 893			MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10	0xd6
 894		>;
 895	};
 896
 897	pinctrl_pcie: aristainetos3-pcie-grp {
 898		fsl,pins = <
 899			MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B	0x61
 900			MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20	0x41
 901		>;
 902	};
 903
 904	pinctrl_pmic: aristainetos3-pmic-grp {
 905		fsl,pins = <
 906			MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03	0x41
 907		>;
 908	};
 909
 910	pinctrl_pwm1: aristainetos3-pwm1-grp {
 911		fsl,pins = <
 912			MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT	0x116
 913		>;
 914	};
 915
 916	pinctrl_pwm2: aristainetos3-pwm2-grp {
 917		fsl,pins = <
 918			MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT	0x116
 919		>;
 920	};
 921
 922	pinctrl_tpm_irq: aristainetos3-tpm-irq-grp {
 923		fsl,pins = <
 924			MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14	0xd6
 925		>;
 926	};
 927
 928	pinctrl_uart1: aristainetos3-uart1-grp {
 929		fsl,pins = <
 930			MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX	0x140
 931			MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX	0x140
 932		>;
 933	};
 934
 935	pinctrl_uart2: aristainetos3-uart2-grp {
 936		fsl,pins = <
 937			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX	0x140
 938			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX	0x140
 939			MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06	0x140
 940			MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS	0x140
 941		>;
 942	};
 943
 944	pinctrl_uart3: aristainetos3-uart3-grp {
 945		fsl,pins = <
 946			MX8MP_IOMUXC_NAND_ALE__UART3_DCE_RX	0x140
 947			MX8MP_IOMUXC_NAND_CE0_B__UART3_DCE_TX	0x140
 948		>;
 949	};
 950
 951	pinctrl_uart4: aristainetos3-uart4-grp {
 952		fsl,pins = <
 953			MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX    0x140
 954			MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX    0x140
 955			MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09	0x140
 956			MX8MP_IOMUXC_NAND_DATA02__UART4_DCE_CTS 0x140
 957		>;
 958	};
 959
 960	pinctrl_usb1_vbus: aristainetos3-usb1-grp {
 961		fsl,pins = <
 962			MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14	0x19
 963		>;
 964	};
 965
 966	pinctrl_usdhc1: aristainetos3-usdhc1-grp {
 967		fsl,pins = <
 968			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x190
 969			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d0
 970			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d0
 971			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d0
 972			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d0
 973			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d0
 974		>;
 975	};
 976
 977	pinctrl_usdhc1_100mhz: aristainetos3-usdhc1-100mhz-grp {
 978		fsl,pins = <
 979			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x194
 980			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d4
 981			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d4
 982			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d4
 983			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d4
 984			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d4
 985		>;
 986	};
 987
 988	pinctrl_usdhc1_200mhz: aristainetos3-usdhc1-200mhz-grp {
 989		fsl,pins = <
 990			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x196
 991			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d6
 992			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d6
 993			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d6
 994			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d6
 995			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d6
 996		>;
 997	};
 998
 999	pinctrl_usdhc2: aristainetos3-usdhc2-grp {
1000		fsl,pins = <
1001			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x190
1002			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d0
1003			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d0
1004			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d0
1005			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d0
1006			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d0
1007			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc1
1008
1009		>;
1010	};
1011
1012	pinctrl_usdhc2_100mhz: aristainetos3-usdhc2-100mhz-grp {
1013		fsl,pins = <
1014			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x194
1015			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d4
1016			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d4
1017			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d4
1018			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d4
1019			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d4
1020			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
1021		>;
1022	};
1023
1024	pinctrl_usdhc2_200mhz: aristainetos3-usdhc2-200mhz-grp {
1025		fsl,pins = <
1026			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x196
1027			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d6
1028			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d6
1029			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d6
1030			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d6
1031			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d6
1032			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
1033		>;
1034	};
1035
1036	pinctrl_usdhc2_gpio: aristainetos3-usdhc2-gpio-grp {
1037		fsl,pins = <
1038			MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12	0x40000080
1039		>;
1040	};
1041
1042	pinctrl_usdhc2_vmmc: aristainetos3-usdhc2-vmmc-grp {
1043		fsl,pins = <
1044			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x41
1045		>;
1046	};
1047
1048	pinctrl_usdhc3: aristainetos3-usdhc3-grp {
1049		fsl,pins = <
1050			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x190
1051			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d0
1052			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d0
1053			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d0
1054			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d0
1055			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d0
1056			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d0
1057			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d0
1058			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d0
1059			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d0
1060			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x190
1061		>;
1062	};
1063
1064	pinctrl_usdhc3_100mhz: aristainetos3-usdhc3-100mhz-grp {
1065		fsl,pins = <
1066			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x194
1067			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d4
1068			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d4
1069			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d4
1070			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d4
1071			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d4
1072			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d4
1073			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d4
1074			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d4
1075			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d4
1076			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x194
1077		>;
1078	};
1079
1080	pinctrl_usdhc3_200mhz: aristainetos3-usdhc3-200mhz-grp {
1081		fsl,pins = <
1082			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x196
1083			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d6
1084			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d6
1085			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d6
1086			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d6
1087			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d6
1088			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d6
1089			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d6
1090			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d6
1091			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d6
1092			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x196
1093		>;
1094	};
1095
1096	pinctrl_watchdog_gpio: aristainetos3-wdog-gpio-grp {
1097		fsl,pins = <
1098			MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06	0x19
1099		>;
1100	};
1101
1102	pinctrl_wdog: aristainetos3-wdog-grp {
1103		fsl,pins = <
1104			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B	0xc6
1105		>;
1106	};
1107};