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imx8mn.dtsi
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linux-6.19.14/arch/arm64/boot/dts/freescale/imx8mn.dtsi
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 */ 5 6#include <dt-bindings/clock/imx8mn-clock.h> 7#include <dt-bindings/power/imx8mn-power.h> 8#include <dt-bindings/reset/imx8mq-reset.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/input/input.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/thermal/thermal.h> 13 14#include "imx8mn-pinfunc.h" 15 16/ { 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 ethernet0 = &fec1; 23 gpio0 = &gpio1; 24 gpio1 = &gpio2; 25 gpio2 = &gpio3; 26 gpio3 = &gpio4; 27 gpio4 = &gpio5; 28 i2c0 = &i2c1; 29 i2c1 = &i2c2; 30 i2c2 = &i2c3; 31 i2c3 = &i2c4; 32 mmc0 = &usdhc1; 33 mmc1 = &usdhc2; 34 mmc2 = &usdhc3; 35 serial0 = &uart1; 36 serial1 = &uart2; 37 serial2 = &uart3; 38 serial3 = &uart4; 39 spi0 = &ecspi1; 40 spi1 = &ecspi2; 41 spi2 = &ecspi3; 42 }; 43 44 cpus { 45 #address-cells = <1>; 46 #size-cells = <0>; 47 48 idle-states { 49 entry-method = "psci"; 50 51 cpu_pd_wait: cpu-pd-wait { 52 compatible = "arm,idle-state"; 53 arm,psci-suspend-param = <0x0010033>; 54 local-timer-stop; 55 entry-latency-us = <1000>; 56 exit-latency-us = <700>; 57 min-residency-us = <2700>; 58 }; 59 }; 60 61 A53_0: cpu@0 { 62 device_type = "cpu"; 63 compatible = "arm,cortex-a53"; 64 reg = <0x0>; 65 clocks = <&clk IMX8MN_CLK_ARM>; 66 enable-method = "psci"; 67 i-cache-size = <0x8000>; 68 i-cache-line-size = <64>; 69 i-cache-sets = <256>; 70 d-cache-size = <0x8000>; 71 d-cache-line-size = <64>; 72 d-cache-sets = <128>; 73 next-level-cache = <&A53_L2>; 74 operating-points-v2 = <&a53_opp_table>; 75 nvmem-cells = <&cpu_speed_grade>; 76 nvmem-cell-names = "speed_grade"; 77 cpu-idle-states = <&cpu_pd_wait>; 78 #cooling-cells = <2>; 79 }; 80 81 A53_1: cpu@1 { 82 device_type = "cpu"; 83 compatible = "arm,cortex-a53"; 84 reg = <0x1>; 85 clocks = <&clk IMX8MN_CLK_ARM>; 86 enable-method = "psci"; 87 i-cache-size = <0x8000>; 88 i-cache-line-size = <64>; 89 i-cache-sets = <256>; 90 d-cache-size = <0x8000>; 91 d-cache-line-size = <64>; 92 d-cache-sets = <128>; 93 next-level-cache = <&A53_L2>; 94 operating-points-v2 = <&a53_opp_table>; 95 cpu-idle-states = <&cpu_pd_wait>; 96 #cooling-cells = <2>; 97 }; 98 99 A53_2: cpu@2 { 100 device_type = "cpu"; 101 compatible = "arm,cortex-a53"; 102 reg = <0x2>; 103 clocks = <&clk IMX8MN_CLK_ARM>; 104 enable-method = "psci"; 105 i-cache-size = <0x8000>; 106 i-cache-line-size = <64>; 107 i-cache-sets = <256>; 108 d-cache-size = <0x8000>; 109 d-cache-line-size = <64>; 110 d-cache-sets = <128>; 111 next-level-cache = <&A53_L2>; 112 operating-points-v2 = <&a53_opp_table>; 113 cpu-idle-states = <&cpu_pd_wait>; 114 #cooling-cells = <2>; 115 }; 116 117 A53_3: cpu@3 { 118 device_type = "cpu"; 119 compatible = "arm,cortex-a53"; 120 reg = <0x3>; 121 clocks = <&clk IMX8MN_CLK_ARM>; 122 enable-method = "psci"; 123 i-cache-size = <0x8000>; 124 i-cache-line-size = <64>; 125 i-cache-sets = <256>; 126 d-cache-size = <0x8000>; 127 d-cache-line-size = <64>; 128 d-cache-sets = <128>; 129 next-level-cache = <&A53_L2>; 130 operating-points-v2 = <&a53_opp_table>; 131 cpu-idle-states = <&cpu_pd_wait>; 132 #cooling-cells = <2>; 133 }; 134 135 A53_L2: l2-cache0 { 136 compatible = "cache"; 137 cache-level = <2>; 138 cache-unified; 139 cache-size = <0x80000>; 140 cache-line-size = <64>; 141 cache-sets = <512>; 142 }; 143 }; 144 145 a53_opp_table: opp-table { 146 compatible = "operating-points-v2"; 147 opp-shared; 148 149 opp-1200000000 { 150 opp-hz = /bits/ 64 <1200000000>; 151 opp-microvolt = <850000>; 152 opp-supported-hw = <0xb00>, <0x7>; 153 clock-latency-ns = <150000>; 154 opp-suspend; 155 }; 156 157 opp-1400000000 { 158 opp-hz = /bits/ 64 <1400000000>; 159 opp-microvolt = <950000>; 160 opp-supported-hw = <0x300>, <0x7>; 161 clock-latency-ns = <150000>; 162 opp-suspend; 163 }; 164 165 opp-1500000000 { 166 opp-hz = /bits/ 64 <1500000000>; 167 opp-microvolt = <1000000>; 168 opp-supported-hw = <0x100>, <0x3>; 169 clock-latency-ns = <150000>; 170 opp-suspend; 171 }; 172 }; 173 174 osc_32k: clock-osc-32k { 175 compatible = "fixed-clock"; 176 #clock-cells = <0>; 177 clock-frequency = <32768>; 178 clock-output-names = "osc_32k"; 179 }; 180 181 osc_24m: clock-osc-24m { 182 compatible = "fixed-clock"; 183 #clock-cells = <0>; 184 clock-frequency = <24000000>; 185 clock-output-names = "osc_24m"; 186 }; 187 188 clk_ext1: clock-ext1 { 189 compatible = "fixed-clock"; 190 #clock-cells = <0>; 191 clock-frequency = <133000000>; 192 clock-output-names = "clk_ext1"; 193 }; 194 195 clk_ext2: clock-ext2 { 196 compatible = "fixed-clock"; 197 #clock-cells = <0>; 198 clock-frequency = <133000000>; 199 clock-output-names = "clk_ext2"; 200 }; 201 202 clk_ext3: clock-ext3 { 203 compatible = "fixed-clock"; 204 #clock-cells = <0>; 205 clock-frequency = <133000000>; 206 clock-output-names = "clk_ext3"; 207 }; 208 209 clk_ext4: clock-ext4 { 210 compatible = "fixed-clock"; 211 #clock-cells = <0>; 212 clock-frequency = <133000000>; 213 clock-output-names = "clk_ext4"; 214 }; 215 216 pmu { 217 compatible = "arm,cortex-a53-pmu"; 218 interrupts = <GIC_PPI 7 219 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 220 }; 221 222 psci { 223 compatible = "arm,psci-1.0"; 224 method = "smc"; 225 }; 226 227 thermal-zones { 228 cpu-thermal { 229 polling-delay-passive = <250>; 230 polling-delay = <2000>; 231 thermal-sensors = <&tmu>; 232 trips { 233 cpu_alert0: trip0 { 234 temperature = <85000>; 235 hysteresis = <2000>; 236 type = "passive"; 237 }; 238 239 cpu_crit0: trip1 { 240 temperature = <95000>; 241 hysteresis = <2000>; 242 type = "critical"; 243 }; 244 }; 245 246 cooling-maps { 247 map0 { 248 trip = <&cpu_alert0>; 249 cooling-device = 250 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 251 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 252 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 253 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 254 }; 255 }; 256 }; 257 }; 258 259 timer { 260 compatible = "arm,armv8-timer"; 261 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 262 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 263 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 264 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 265 clock-frequency = <8000000>; 266 arm,no-tick-in-suspend; 267 }; 268 269 soc: soc@0 { 270 compatible = "fsl,imx8mn-soc", "simple-bus"; 271 #address-cells = <1>; 272 #size-cells = <1>; 273 ranges = <0x0 0x0 0x0 0x3e000000>; 274 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; 275 nvmem-cells = <&imx8mn_uid>; 276 nvmem-cell-names = "soc_unique_id"; 277 278 aips1: bus@30000000 { 279 compatible = "fsl,aips-bus", "simple-bus"; 280 reg = <0x30000000 0x400000>; 281 #address-cells = <1>; 282 #size-cells = <1>; 283 ranges; 284 285 spba2: spba-bus@30000000 { 286 compatible = "fsl,spba-bus", "simple-bus"; 287 #address-cells = <1>; 288 #size-cells = <1>; 289 reg = <0x30000000 0x100000>; 290 ranges; 291 292 sai2: sai@30020000 { 293 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; 294 reg = <0x30020000 0x10000>; 295 #sound-dai-cells = <0>; 296 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 297 clocks = <&clk IMX8MN_CLK_SAI2_IPG>, 298 <&clk IMX8MN_CLK_DUMMY>, 299 <&clk IMX8MN_CLK_SAI2_ROOT>, 300 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; 301 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 302 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>; 303 dma-names = "rx", "tx"; 304 status = "disabled"; 305 }; 306 307 sai3: sai@30030000 { 308 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; 309 reg = <0x30030000 0x10000>; 310 #sound-dai-cells = <0>; 311 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 312 clocks = <&clk IMX8MN_CLK_SAI3_IPG>, 313 <&clk IMX8MN_CLK_DUMMY>, 314 <&clk IMX8MN_CLK_SAI3_ROOT>, 315 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; 316 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 317 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; 318 dma-names = "rx", "tx"; 319 status = "disabled"; 320 }; 321 322 sai5: sai@30050000 { 323 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; 324 reg = <0x30050000 0x10000>; 325 #sound-dai-cells = <0>; 326 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 327 clocks = <&clk IMX8MN_CLK_SAI5_IPG>, 328 <&clk IMX8MN_CLK_DUMMY>, 329 <&clk IMX8MN_CLK_SAI5_ROOT>, 330 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; 331 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 332 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; 333 dma-names = "rx", "tx"; 334 fsl,shared-interrupt; 335 fsl,dataline = <0 0xf 0xf>; 336 status = "disabled"; 337 }; 338 339 sai6: sai@30060000 { 340 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; 341 reg = <0x30060000 0x10000>; 342 #sound-dai-cells = <0>; 343 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 344 clocks = <&clk IMX8MN_CLK_SAI6_IPG>, 345 <&clk IMX8MN_CLK_DUMMY>, 346 <&clk IMX8MN_CLK_SAI6_ROOT>, 347 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; 348 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 349 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>; 350 dma-names = "rx", "tx"; 351 status = "disabled"; 352 }; 353 354 micfil: audio-controller@30080000 { 355 compatible = "fsl,imx8mm-micfil"; 356 reg = <0x30080000 0x10000>; 357 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 358 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 359 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 360 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 361 clocks = <&clk IMX8MN_CLK_PDM_IPG>, 362 <&clk IMX8MN_CLK_PDM_ROOT>, 363 <&clk IMX8MN_AUDIO_PLL1_OUT>, 364 <&clk IMX8MN_AUDIO_PLL2_OUT>, 365 <&clk IMX8MN_CLK_EXT3>; 366 clock-names = "ipg_clk", "ipg_clk_app", 367 "pll8k", "pll11k", "clkext3"; 368 dmas = <&sdma2 24 25 0x80000000>; 369 dma-names = "rx"; 370 #sound-dai-cells = <0>; 371 status = "disabled"; 372 }; 373 374 spdif1: spdif@30090000 { 375 compatible = "fsl,imx35-spdif"; 376 reg = <0x30090000 0x10000>; 377 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 378 clocks = <&clk IMX8MN_CLK_AUDIO_AHB>, /* core */ 379 <&clk IMX8MN_CLK_24M>, /* rxtx0 */ 380 <&clk IMX8MN_CLK_SPDIF1>, /* rxtx1 */ 381 <&clk IMX8MN_CLK_DUMMY>, /* rxtx2 */ 382 <&clk IMX8MN_CLK_DUMMY>, /* rxtx3 */ 383 <&clk IMX8MN_CLK_DUMMY>, /* rxtx4 */ 384 <&clk IMX8MN_CLK_AUDIO_AHB>, /* rxtx5 */ 385 <&clk IMX8MN_CLK_DUMMY>, /* rxtx6 */ 386 <&clk IMX8MN_CLK_DUMMY>, /* rxtx7 */ 387 <&clk IMX8MN_CLK_DUMMY>; /* spba */ 388 clock-names = "core", "rxtx0", 389 "rxtx1", "rxtx2", 390 "rxtx3", "rxtx4", 391 "rxtx5", "rxtx6", 392 "rxtx7", "spba"; 393 dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>; 394 dma-names = "rx", "tx"; 395 status = "disabled"; 396 }; 397 398 sai7: sai@300b0000 { 399 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; 400 reg = <0x300b0000 0x10000>; 401 #sound-dai-cells = <0>; 402 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 403 clocks = <&clk IMX8MN_CLK_SAI7_IPG>, 404 <&clk IMX8MN_CLK_DUMMY>, 405 <&clk IMX8MN_CLK_SAI7_ROOT>, 406 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; 407 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 408 dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>; 409 dma-names = "rx", "tx"; 410 status = "disabled"; 411 }; 412 413 easrc: easrc@300c0000 { 414 compatible = "fsl,imx8mn-easrc"; 415 reg = <0x300c0000 0x10000>; 416 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 417 clocks = <&clk IMX8MN_CLK_ASRC_ROOT>; 418 clock-names = "mem"; 419 dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>, 420 <&sdma2 18 23 0> , <&sdma2 19 23 0>, 421 <&sdma2 20 23 0> , <&sdma2 21 23 0>, 422 <&sdma2 22 23 0> , <&sdma2 23 23 0>; 423 dma-names = "ctx0_rx", "ctx0_tx", 424 "ctx1_rx", "ctx1_tx", 425 "ctx2_rx", "ctx2_tx", 426 "ctx3_rx", "ctx3_tx"; 427 firmware-name = "imx/easrc/easrc-imx8mn.bin"; 428 fsl,asrc-rate = <8000>; 429 fsl,asrc-format = <2>; 430 status = "disabled"; 431 }; 432 }; 433 434 gpio1: gpio@30200000 { 435 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 436 reg = <0x30200000 0x10000>; 437 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 438 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 439 clocks = <&clk IMX8MN_CLK_GPIO1_ROOT>; 440 gpio-controller; 441 #gpio-cells = <2>; 442 interrupt-controller; 443 #interrupt-cells = <2>; 444 gpio-ranges = <&iomuxc 0 10 30>; 445 }; 446 447 gpio2: gpio@30210000 { 448 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 449 reg = <0x30210000 0x10000>; 450 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 451 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 452 clocks = <&clk IMX8MN_CLK_GPIO2_ROOT>; 453 gpio-controller; 454 #gpio-cells = <2>; 455 interrupt-controller; 456 #interrupt-cells = <2>; 457 gpio-ranges = <&iomuxc 0 40 21>; 458 }; 459 460 gpio3: gpio@30220000 { 461 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 462 reg = <0x30220000 0x10000>; 463 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 464 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 465 clocks = <&clk IMX8MN_CLK_GPIO3_ROOT>; 466 gpio-controller; 467 #gpio-cells = <2>; 468 interrupt-controller; 469 #interrupt-cells = <2>; 470 gpio-ranges = <&iomuxc 0 61 26>; 471 }; 472 473 gpio4: gpio@30230000 { 474 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 475 reg = <0x30230000 0x10000>; 476 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 477 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 478 clocks = <&clk IMX8MN_CLK_GPIO4_ROOT>; 479 gpio-controller; 480 #gpio-cells = <2>; 481 interrupt-controller; 482 #interrupt-cells = <2>; 483 gpio-ranges = <&iomuxc 21 108 11>; 484 }; 485 486 gpio5: gpio@30240000 { 487 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 488 reg = <0x30240000 0x10000>; 489 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 490 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 491 clocks = <&clk IMX8MN_CLK_GPIO5_ROOT>; 492 gpio-controller; 493 #gpio-cells = <2>; 494 interrupt-controller; 495 #interrupt-cells = <2>; 496 gpio-ranges = <&iomuxc 0 119 30>; 497 }; 498 499 tmu: tmu@30260000 { 500 compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu"; 501 reg = <0x30260000 0x10000>; 502 clocks = <&clk IMX8MN_CLK_TMU_ROOT>; 503 nvmem-cells = <&tmu_calib>; 504 nvmem-cell-names = "calib"; 505 #thermal-sensor-cells = <0>; 506 }; 507 508 wdog1: watchdog@30280000 { 509 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt"; 510 reg = <0x30280000 0x10000>; 511 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 512 clocks = <&clk IMX8MN_CLK_WDOG1_ROOT>; 513 status = "disabled"; 514 }; 515 516 wdog2: watchdog@30290000 { 517 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt"; 518 reg = <0x30290000 0x10000>; 519 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 520 clocks = <&clk IMX8MN_CLK_WDOG2_ROOT>; 521 status = "disabled"; 522 }; 523 524 wdog3: watchdog@302a0000 { 525 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt"; 526 reg = <0x302a0000 0x10000>; 527 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 528 clocks = <&clk IMX8MN_CLK_WDOG3_ROOT>; 529 status = "disabled"; 530 }; 531 532 sdma3: dma-controller@302b0000 { 533 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; 534 reg = <0x302b0000 0x10000>; 535 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 536 clocks = <&clk IMX8MN_CLK_SDMA3_ROOT>, 537 <&clk IMX8MN_CLK_SDMA3_ROOT>; 538 clock-names = "ipg", "ahb"; 539 #dma-cells = <3>; 540 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 541 }; 542 543 sdma2: dma-controller@302c0000 { 544 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; 545 reg = <0x302c0000 0x10000>; 546 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 547 clocks = <&clk IMX8MN_CLK_SDMA2_ROOT>, 548 <&clk IMX8MN_CLK_SDMA2_ROOT>; 549 clock-names = "ipg", "ahb"; 550 #dma-cells = <3>; 551 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 552 }; 553 554 iomuxc: pinctrl@30330000 { 555 compatible = "fsl,imx8mn-iomuxc"; 556 reg = <0x30330000 0x10000>; 557 }; 558 559 gpr: syscon@30340000 { 560 compatible = "fsl,imx8mn-iomuxc-gpr", "syscon"; 561 reg = <0x30340000 0x10000>; 562 }; 563 564 ocotp: efuse@30350000 { 565 compatible = "fsl,imx8mn-ocotp", "fsl,imx8mm-ocotp", "syscon"; 566 reg = <0x30350000 0x10000>; 567 clocks = <&clk IMX8MN_CLK_OCOTP_ROOT>; 568 #address-cells = <1>; 569 #size-cells = <1>; 570 571 /* 572 * The register address below maps to the MX8M 573 * Fusemap Description Table entries this way. 574 * Assuming 575 * reg = <ADDR SIZE>; 576 * then 577 * Fuse Address = (ADDR * 4) + 0x400 578 * Note that if SIZE is greater than 4, then 579 * each subsequent fuse is located at offset 580 * +0x10 in Fusemap Description Table (e.g. 581 * reg = <0x4 0x8> describes fuses 0x410 and 582 * 0x420). 583 */ 584 imx8mn_uid: unique-id@4 { /* 0x410-0x420 */ 585 reg = <0x4 0x8>; 586 }; 587 588 cpu_speed_grade: speed-grade@10 { /* 0x440 */ 589 reg = <0x10 4>; 590 }; 591 592 tmu_calib: calib@3c { /* 0x4f0 */ 593 reg = <0x3c 4>; 594 }; 595 596 fec_mac_address: mac-address@90 { /* 0x640 */ 597 reg = <0x90 6>; 598 }; 599 }; 600 601 anatop: clock-controller@30360000 { 602 compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop"; 603 reg = <0x30360000 0x10000>; 604 #clock-cells = <1>; 605 }; 606 607 snvs: snvs@30370000 { 608 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; 609 reg = <0x30370000 0x10000>; 610 611 snvs_rtc: snvs-rtc-lp { 612 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 613 regmap = <&snvs>; 614 offset = <0x34>; 615 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 616 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 617 clocks = <&clk IMX8MN_CLK_SNVS_ROOT>; 618 clock-names = "snvs-rtc"; 619 }; 620 621 snvs_pwrkey: snvs-powerkey { 622 compatible = "fsl,sec-v4.0-pwrkey"; 623 regmap = <&snvs>; 624 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 625 clocks = <&clk IMX8MN_CLK_SNVS_ROOT>; 626 clock-names = "snvs-pwrkey"; 627 linux,keycode = <KEY_POWER>; 628 wakeup-source; 629 status = "disabled"; 630 }; 631 }; 632 633 clk: clock-controller@30380000 { 634 compatible = "fsl,imx8mn-ccm"; 635 reg = <0x30380000 0x10000>; 636 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 637 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 638 #clock-cells = <1>; 639 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, 640 <&clk_ext3>, <&clk_ext4>; 641 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", 642 "clk_ext3", "clk_ext4"; 643 assigned-clocks = <&clk IMX8MN_CLK_A53_SRC>, 644 <&clk IMX8MN_CLK_A53_CORE>, 645 <&clk IMX8MN_CLK_NOC>, 646 <&clk IMX8MN_CLK_AUDIO_AHB>, 647 <&clk IMX8MN_CLK_IPG_AUDIO_ROOT>, 648 <&clk IMX8MN_SYS_PLL3>, 649 <&clk IMX8MN_AUDIO_PLL1>, 650 <&clk IMX8MN_AUDIO_PLL2>; 651 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_800M>, 652 <&clk IMX8MN_ARM_PLL_OUT>, 653 <&clk IMX8MN_SYS_PLL3_OUT>, 654 <&clk IMX8MN_SYS_PLL1_800M>; 655 assigned-clock-rates = <0>, <0>, <0>, 656 <400000000>, 657 <400000000>, 658 <600000000>, 659 <393216000>, 660 <361267200>; 661 }; 662 663 src: reset-controller@30390000 { 664 compatible = "fsl,imx8mn-src", "fsl,imx8mq-src", "syscon"; 665 reg = <0x30390000 0x10000>; 666 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 667 #reset-cells = <1>; 668 }; 669 670 gpc: gpc@303a0000 { 671 compatible = "fsl,imx8mn-gpc"; 672 reg = <0x303a0000 0x10000>; 673 interrupt-parent = <&gic>; 674 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 675 676 pgc { 677 #address-cells = <1>; 678 #size-cells = <0>; 679 680 pgc_hsiomix: power-domain@0 { 681 #power-domain-cells = <0>; 682 reg = <IMX8MN_POWER_DOMAIN_HSIOMIX>; 683 clocks = <&clk IMX8MN_CLK_USB_BUS>; 684 }; 685 686 pgc_otg1: power-domain@1 { 687 #power-domain-cells = <0>; 688 reg = <IMX8MN_POWER_DOMAIN_OTG1>; 689 }; 690 691 pgc_gpumix: power-domain@2 { 692 #power-domain-cells = <0>; 693 reg = <IMX8MN_POWER_DOMAIN_GPUMIX>; 694 clocks = <&clk IMX8MN_CLK_GPU_CORE_ROOT>, 695 <&clk IMX8MN_CLK_GPU_SHADER>, 696 <&clk IMX8MN_CLK_GPU_BUS_ROOT>, 697 <&clk IMX8MN_CLK_GPU_AHB>; 698 }; 699 700 pgc_dispmix: power-domain@3 { 701 #power-domain-cells = <0>; 702 reg = <IMX8MN_POWER_DOMAIN_DISPMIX>; 703 clocks = <&clk IMX8MN_CLK_DISP_AXI_ROOT>, 704 <&clk IMX8MN_CLK_DISP_APB_ROOT>; 705 }; 706 707 pgc_mipi: power-domain@4 { 708 #power-domain-cells = <0>; 709 reg = <IMX8MN_POWER_DOMAIN_MIPI>; 710 power-domains = <&pgc_dispmix>; 711 }; 712 }; 713 }; 714 }; 715 716 aips2: bus@30400000 { 717 compatible = "fsl,aips-bus", "simple-bus"; 718 reg = <0x30400000 0x400000>; 719 #address-cells = <1>; 720 #size-cells = <1>; 721 ranges; 722 723 pwm1: pwm@30660000 { 724 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; 725 reg = <0x30660000 0x10000>; 726 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 727 clocks = <&clk IMX8MN_CLK_PWM1_ROOT>, 728 <&clk IMX8MN_CLK_PWM1_ROOT>; 729 clock-names = "ipg", "per"; 730 #pwm-cells = <3>; 731 status = "disabled"; 732 }; 733 734 pwm2: pwm@30670000 { 735 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; 736 reg = <0x30670000 0x10000>; 737 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 738 clocks = <&clk IMX8MN_CLK_PWM2_ROOT>, 739 <&clk IMX8MN_CLK_PWM2_ROOT>; 740 clock-names = "ipg", "per"; 741 #pwm-cells = <3>; 742 status = "disabled"; 743 }; 744 745 pwm3: pwm@30680000 { 746 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; 747 reg = <0x30680000 0x10000>; 748 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 749 clocks = <&clk IMX8MN_CLK_PWM3_ROOT>, 750 <&clk IMX8MN_CLK_PWM3_ROOT>; 751 clock-names = "ipg", "per"; 752 #pwm-cells = <3>; 753 status = "disabled"; 754 }; 755 756 pwm4: pwm@30690000 { 757 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; 758 reg = <0x30690000 0x10000>; 759 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 760 clocks = <&clk IMX8MN_CLK_PWM4_ROOT>, 761 <&clk IMX8MN_CLK_PWM4_ROOT>; 762 clock-names = "ipg", "per"; 763 #pwm-cells = <3>; 764 status = "disabled"; 765 }; 766 767 system_counter: timer@306a0000 { 768 compatible = "nxp,sysctr-timer"; 769 reg = <0x306a0000 0x20000>; 770 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 771 clocks = <&osc_24m>; 772 clock-names = "per"; 773 }; 774 }; 775 776 aips3: bus@30800000 { 777 compatible = "fsl,aips-bus", "simple-bus"; 778 reg = <0x30800000 0x400000>; 779 #address-cells = <1>; 780 #size-cells = <1>; 781 ranges; 782 783 spba1: spba-bus@30800000 { 784 compatible = "fsl,spba-bus", "simple-bus"; 785 #address-cells = <1>; 786 #size-cells = <1>; 787 reg = <0x30800000 0x100000>; 788 ranges; 789 790 ecspi1: spi@30820000 { 791 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; 792 #address-cells = <1>; 793 #size-cells = <0>; 794 reg = <0x30820000 0x10000>; 795 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 796 clocks = <&clk IMX8MN_CLK_ECSPI1_ROOT>, 797 <&clk IMX8MN_CLK_ECSPI1_ROOT>; 798 clock-names = "ipg", "per"; 799 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; 800 dma-names = "rx", "tx"; 801 status = "disabled"; 802 }; 803 804 ecspi2: spi@30830000 { 805 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; 806 #address-cells = <1>; 807 #size-cells = <0>; 808 reg = <0x30830000 0x10000>; 809 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 810 clocks = <&clk IMX8MN_CLK_ECSPI2_ROOT>, 811 <&clk IMX8MN_CLK_ECSPI2_ROOT>; 812 clock-names = "ipg", "per"; 813 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; 814 dma-names = "rx", "tx"; 815 status = "disabled"; 816 }; 817 818 ecspi3: spi@30840000 { 819 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; 820 #address-cells = <1>; 821 #size-cells = <0>; 822 reg = <0x30840000 0x10000>; 823 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 824 clocks = <&clk IMX8MN_CLK_ECSPI3_ROOT>, 825 <&clk IMX8MN_CLK_ECSPI3_ROOT>; 826 clock-names = "ipg", "per"; 827 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; 828 dma-names = "rx", "tx"; 829 status = "disabled"; 830 }; 831 832 uart1: serial@30860000 { 833 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; 834 reg = <0x30860000 0x10000>; 835 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 836 clocks = <&clk IMX8MN_CLK_UART1_ROOT>, 837 <&clk IMX8MN_CLK_UART1_ROOT>; 838 clock-names = "ipg", "per"; 839 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; 840 dma-names = "rx", "tx"; 841 status = "disabled"; 842 }; 843 844 uart3: serial@30880000 { 845 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; 846 reg = <0x30880000 0x10000>; 847 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 848 clocks = <&clk IMX8MN_CLK_UART3_ROOT>, 849 <&clk IMX8MN_CLK_UART3_ROOT>; 850 clock-names = "ipg", "per"; 851 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; 852 dma-names = "rx", "tx"; 853 status = "disabled"; 854 }; 855 856 uart2: serial@30890000 { 857 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; 858 reg = <0x30890000 0x10000>; 859 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 860 clocks = <&clk IMX8MN_CLK_UART2_ROOT>, 861 <&clk IMX8MN_CLK_UART2_ROOT>; 862 clock-names = "ipg", "per"; 863 dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>; 864 dma-names = "rx", "tx"; 865 status = "disabled"; 866 }; 867 }; 868 869 crypto: crypto@30900000 { 870 compatible = "fsl,sec-v4.0"; 871 #address-cells = <1>; 872 #size-cells = <1>; 873 reg = <0x30900000 0x40000>; 874 ranges = <0 0x30900000 0x40000>; 875 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 876 clocks = <&clk IMX8MN_CLK_AHB>, 877 <&clk IMX8MN_CLK_IPG_ROOT>; 878 clock-names = "aclk", "ipg"; 879 880 sec_jr0: jr@1000 { 881 compatible = "fsl,sec-v4.0-job-ring"; 882 reg = <0x1000 0x1000>; 883 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 884 status = "disabled"; 885 }; 886 887 sec_jr1: jr@2000 { 888 compatible = "fsl,sec-v4.0-job-ring"; 889 reg = <0x2000 0x1000>; 890 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 891 }; 892 893 sec_jr2: jr@3000 { 894 compatible = "fsl,sec-v4.0-job-ring"; 895 reg = <0x3000 0x1000>; 896 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 897 }; 898 }; 899 900 i2c1: i2c@30a20000 { 901 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; 902 #address-cells = <1>; 903 #size-cells = <0>; 904 reg = <0x30a20000 0x10000>; 905 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 906 clocks = <&clk IMX8MN_CLK_I2C1_ROOT>; 907 status = "disabled"; 908 }; 909 910 i2c2: i2c@30a30000 { 911 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; 912 #address-cells = <1>; 913 #size-cells = <0>; 914 reg = <0x30a30000 0x10000>; 915 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 916 clocks = <&clk IMX8MN_CLK_I2C2_ROOT>; 917 status = "disabled"; 918 }; 919 920 i2c3: i2c@30a40000 { 921 #address-cells = <1>; 922 #size-cells = <0>; 923 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; 924 reg = <0x30a40000 0x10000>; 925 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 926 clocks = <&clk IMX8MN_CLK_I2C3_ROOT>; 927 status = "disabled"; 928 }; 929 930 i2c4: i2c@30a50000 { 931 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; 932 #address-cells = <1>; 933 #size-cells = <0>; 934 reg = <0x30a50000 0x10000>; 935 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 936 clocks = <&clk IMX8MN_CLK_I2C4_ROOT>; 937 status = "disabled"; 938 }; 939 940 uart4: serial@30a60000 { 941 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; 942 reg = <0x30a60000 0x10000>; 943 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 944 clocks = <&clk IMX8MN_CLK_UART4_ROOT>, 945 <&clk IMX8MN_CLK_UART4_ROOT>; 946 clock-names = "ipg", "per"; 947 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; 948 dma-names = "rx", "tx"; 949 status = "disabled"; 950 }; 951 952 mu: mailbox@30aa0000 { 953 compatible = "fsl,imx8mn-mu", "fsl,imx6sx-mu"; 954 reg = <0x30aa0000 0x10000>; 955 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 956 clocks = <&clk IMX8MN_CLK_MU_ROOT>; 957 #mbox-cells = <2>; 958 }; 959 960 usdhc1: mmc@30b40000 { 961 compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 962 reg = <0x30b40000 0x10000>; 963 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 964 clocks = <&clk IMX8MN_CLK_IPG_ROOT>, 965 <&clk IMX8MN_CLK_NAND_USDHC_BUS>, 966 <&clk IMX8MN_CLK_USDHC1_ROOT>; 967 clock-names = "ipg", "ahb", "per"; 968 fsl,tuning-start-tap = <20>; 969 fsl,tuning-step = <2>; 970 bus-width = <4>; 971 status = "disabled"; 972 }; 973 974 usdhc2: mmc@30b50000 { 975 compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 976 reg = <0x30b50000 0x10000>; 977 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 978 clocks = <&clk IMX8MN_CLK_IPG_ROOT>, 979 <&clk IMX8MN_CLK_NAND_USDHC_BUS>, 980 <&clk IMX8MN_CLK_USDHC2_ROOT>; 981 clock-names = "ipg", "ahb", "per"; 982 fsl,tuning-start-tap = <20>; 983 fsl,tuning-step = <2>; 984 bus-width = <4>; 985 status = "disabled"; 986 }; 987 988 usdhc3: mmc@30b60000 { 989 compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 990 reg = <0x30b60000 0x10000>; 991 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 992 clocks = <&clk IMX8MN_CLK_IPG_ROOT>, 993 <&clk IMX8MN_CLK_NAND_USDHC_BUS>, 994 <&clk IMX8MN_CLK_USDHC3_ROOT>; 995 clock-names = "ipg", "ahb", "per"; 996 fsl,tuning-start-tap = <20>; 997 fsl,tuning-step = <2>; 998 bus-width = <4>; 999 status = "disabled"; 1000 }; 1001 1002 flexspi: spi@30bb0000 { 1003 #address-cells = <1>; 1004 #size-cells = <0>; 1005 compatible = "nxp,imx8mm-fspi"; 1006 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>; 1007 reg-names = "fspi_base", "fspi_mmap"; 1008 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1009 clocks = <&clk IMX8MN_CLK_QSPI_ROOT>, 1010 <&clk IMX8MN_CLK_QSPI_ROOT>; 1011 clock-names = "fspi_en", "fspi"; 1012 status = "disabled"; 1013 }; 1014 1015 sdma1: dma-controller@30bd0000 { 1016 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; 1017 reg = <0x30bd0000 0x10000>; 1018 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 1019 clocks = <&clk IMX8MN_CLK_SDMA1_ROOT>, 1020 <&clk IMX8MN_CLK_AHB>; 1021 clock-names = "ipg", "ahb"; 1022 #dma-cells = <3>; 1023 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1024 }; 1025 1026 fec1: ethernet@30be0000 { 1027 compatible = "fsl,imx8mn-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; 1028 reg = <0x30be0000 0x10000>; 1029 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1030 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1031 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1032 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1033 clocks = <&clk IMX8MN_CLK_ENET1_ROOT>, 1034 <&clk IMX8MN_CLK_ENET1_ROOT>, 1035 <&clk IMX8MN_CLK_ENET_TIMER>, 1036 <&clk IMX8MN_CLK_ENET_REF>, 1037 <&clk IMX8MN_CLK_ENET_PHY_REF>; 1038 clock-names = "ipg", "ahb", "ptp", 1039 "enet_clk_ref", "enet_out"; 1040 assigned-clocks = <&clk IMX8MN_CLK_ENET_AXI>, 1041 <&clk IMX8MN_CLK_ENET_TIMER>, 1042 <&clk IMX8MN_CLK_ENET_REF>, 1043 <&clk IMX8MN_CLK_ENET_PHY_REF>; 1044 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>, 1045 <&clk IMX8MN_SYS_PLL2_100M>, 1046 <&clk IMX8MN_SYS_PLL2_125M>, 1047 <&clk IMX8MN_SYS_PLL2_50M>; 1048 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; 1049 fsl,num-tx-queues = <3>; 1050 fsl,num-rx-queues = <3>; 1051 nvmem-cells = <&fec_mac_address>; 1052 nvmem-cell-names = "mac-address"; 1053 fsl,stop-mode = <&gpr 0x10 3>; 1054 status = "disabled"; 1055 }; 1056 1057 }; 1058 1059 aips4: bus@32c00000 { 1060 compatible = "fsl,aips-bus", "simple-bus"; 1061 reg = <0x32c00000 0x400000>; 1062 #address-cells = <1>; 1063 #size-cells = <1>; 1064 ranges; 1065 1066 lcdif: lcdif@32e00000 { 1067 compatible = "fsl,imx8mn-lcdif", "fsl,imx6sx-lcdif"; 1068 reg = <0x32e00000 0x10000>; 1069 clocks = <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>, 1070 <&clk IMX8MN_CLK_DISP_APB_ROOT>, 1071 <&clk IMX8MN_CLK_DISP_AXI_ROOT>; 1072 clock-names = "pix", "axi", "disp_axi"; 1073 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1074 power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_LCDIF>; 1075 status = "disabled"; 1076 1077 port { 1078 lcdif_to_dsim: endpoint { 1079 remote-endpoint = <&dsim_from_lcdif>; 1080 }; 1081 }; 1082 }; 1083 1084 mipi_dsi: dsi@32e10000 { 1085 compatible = "fsl,imx8mn-mipi-dsim", "fsl,imx8mm-mipi-dsim"; 1086 reg = <0x32e10000 0x400>; 1087 clocks = <&clk IMX8MN_CLK_DSI_CORE>, 1088 <&clk IMX8MN_CLK_DSI_PHY_REF>; 1089 clock-names = "bus_clk", "sclk_mipi"; 1090 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 1091 power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_MIPI_DSI>; 1092 status = "disabled"; 1093 1094 ports { 1095 #address-cells = <1>; 1096 #size-cells = <0>; 1097 1098 port@0 { 1099 reg = <0>; 1100 1101 dsim_from_lcdif: endpoint { 1102 remote-endpoint = <&lcdif_to_dsim>; 1103 }; 1104 }; 1105 1106 port@1 { 1107 reg = <1>; 1108 1109 mipi_dsi_out: endpoint { 1110 }; 1111 }; 1112 }; 1113 }; 1114 1115 isi: isi@32e20000 { 1116 compatible = "fsl,imx8mn-isi"; 1117 reg = <0x32e20000 0x8000>; 1118 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1119 clocks = <&clk IMX8MN_CLK_DISP_AXI_ROOT>, 1120 <&clk IMX8MN_CLK_DISP_APB_ROOT>; 1121 clock-names = "axi", "apb"; 1122 fsl,blk-ctrl = <&disp_blk_ctrl>; 1123 power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_ISI>; 1124 status = "disabled"; 1125 1126 ports { 1127 #address-cells = <1>; 1128 #size-cells = <0>; 1129 1130 port@0 { 1131 reg = <0>; 1132 isi_in: endpoint { 1133 remote-endpoint = <&mipi_csi_out>; 1134 }; 1135 }; 1136 }; 1137 }; 1138 1139 disp_blk_ctrl: blk-ctrl@32e28000 { 1140 compatible = "fsl,imx8mn-disp-blk-ctrl", "syscon"; 1141 reg = <0x32e28000 0x100>; 1142 power-domains = <&pgc_dispmix>, <&pgc_dispmix>, 1143 <&pgc_dispmix>, <&pgc_mipi>, 1144 <&pgc_mipi>; 1145 power-domain-names = "bus", "isi", 1146 "lcdif", "mipi-dsi", 1147 "mipi-csi"; 1148 clocks = <&clk IMX8MN_CLK_DISP_AXI>, 1149 <&clk IMX8MN_CLK_DISP_APB>, 1150 <&clk IMX8MN_CLK_DISP_AXI_ROOT>, 1151 <&clk IMX8MN_CLK_DISP_APB_ROOT>, 1152 <&clk IMX8MN_CLK_DISP_AXI_ROOT>, 1153 <&clk IMX8MN_CLK_DISP_APB_ROOT>, 1154 <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>, 1155 <&clk IMX8MN_CLK_DSI_CORE>, 1156 <&clk IMX8MN_CLK_DSI_PHY_REF>, 1157 <&clk IMX8MN_CLK_CSI1_PHY_REF>, 1158 <&clk IMX8MN_CLK_CAMERA_PIXEL_ROOT>; 1159 clock-names = "disp_axi", "disp_apb", 1160 "disp_axi_root", "disp_apb_root", 1161 "lcdif-axi", "lcdif-apb", "lcdif-pix", 1162 "dsi-pclk", "dsi-ref", 1163 "csi-aclk", "csi-pclk"; 1164 assigned-clocks = <&clk IMX8MN_CLK_DSI_CORE>, 1165 <&clk IMX8MN_CLK_DSI_PHY_REF>, 1166 <&clk IMX8MN_CLK_DISP_PIXEL>, 1167 <&clk IMX8MN_CLK_DISP_AXI>, 1168 <&clk IMX8MN_CLK_DISP_APB>; 1169 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>, 1170 <&clk IMX8MN_CLK_24M>, 1171 <&clk IMX8MN_VIDEO_PLL1_OUT>, 1172 <&clk IMX8MN_SYS_PLL2_1000M>, 1173 <&clk IMX8MN_SYS_PLL1_800M>; 1174 assigned-clock-rates = <266000000>, 1175 <24000000>, 1176 <24000000>, 1177 <500000000>, 1178 <200000000>; 1179 #power-domain-cells = <1>; 1180 }; 1181 1182 mipi_csi: mipi-csi@32e30000 { 1183 compatible = "fsl,imx8mm-mipi-csi2"; 1184 reg = <0x32e30000 0x1000>; 1185 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1186 assigned-clocks = <&clk IMX8MN_CLK_CAMERA_PIXEL>; 1187 assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_1000M>; 1188 assigned-clock-rates = <333000000>; 1189 clock-frequency = <333000000>; 1190 clocks = <&clk IMX8MN_CLK_DISP_APB_ROOT>, 1191 <&clk IMX8MN_CLK_CAMERA_PIXEL>, 1192 <&clk IMX8MN_CLK_CSI1_PHY_REF>, 1193 <&clk IMX8MN_CLK_DISP_AXI_ROOT>; 1194 clock-names = "pclk", "wrap", "phy", "axi"; 1195 power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_MIPI_CSI>; 1196 status = "disabled"; 1197 1198 ports { 1199 #address-cells = <1>; 1200 #size-cells = <0>; 1201 1202 port@0 { 1203 reg = <0>; 1204 }; 1205 1206 port@1 { 1207 reg = <1>; 1208 1209 mipi_csi_out: endpoint { 1210 remote-endpoint = <&isi_in>; 1211 }; 1212 }; 1213 }; 1214 }; 1215 1216 usbotg1: usb@32e40000 { 1217 compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; 1218 reg = <0x32e40000 0x200>; 1219 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1220 clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>; 1221 assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>; 1222 assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>; 1223 phys = <&usbphynop1>; 1224 fsl,usbmisc = <&usbmisc1 0>; 1225 power-domains = <&pgc_hsiomix>; 1226 status = "disabled"; 1227 }; 1228 1229 usbmisc1: usbmisc@32e40200 { 1230 compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc", 1231 "fsl,imx6q-usbmisc"; 1232 #index-cells = <1>; 1233 reg = <0x32e40200 0x200>; 1234 }; 1235 }; 1236 1237 dma_apbh: dma-controller@33000000 { 1238 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; 1239 reg = <0x33000000 0x2000>; 1240 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1241 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1242 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1243 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1244 #dma-cells = <1>; 1245 dma-channels = <4>; 1246 clocks = <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; 1247 }; 1248 1249 gpmi: nand-controller@33002000 { 1250 compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand"; 1251 #address-cells = <1>; 1252 #size-cells = <0>; 1253 reg = <0x33002000 0x2000>, <0x33004000 0x4000>; 1254 reg-names = "gpmi-nand", "bch"; 1255 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1256 interrupt-names = "bch"; 1257 clocks = <&clk IMX8MN_CLK_NAND_ROOT>, 1258 <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; 1259 clock-names = "gpmi_io", "gpmi_bch_apb"; 1260 dmas = <&dma_apbh 0>; 1261 dma-names = "rx-tx"; 1262 status = "disabled"; 1263 }; 1264 1265 gpu: gpu@38000000 { 1266 compatible = "vivante,gc"; 1267 reg = <0x38000000 0x8000>; 1268 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1269 clocks = <&clk IMX8MN_CLK_GPU_AHB>, 1270 <&clk IMX8MN_CLK_GPU_BUS_ROOT>, 1271 <&clk IMX8MN_CLK_GPU_CORE_ROOT>, 1272 <&clk IMX8MN_CLK_GPU_SHADER>; 1273 clock-names = "reg", "bus", "core", "shader"; 1274 assigned-clocks = <&clk IMX8MN_CLK_GPU_CORE>, 1275 <&clk IMX8MN_CLK_GPU_SHADER>, 1276 <&clk IMX8MN_CLK_GPU_AXI>, 1277 <&clk IMX8MN_CLK_GPU_AHB>, 1278 <&clk IMX8MN_GPU_PLL>; 1279 assigned-clock-parents = <&clk IMX8MN_GPU_PLL_OUT>, 1280 <&clk IMX8MN_GPU_PLL_OUT>, 1281 <&clk IMX8MN_SYS_PLL1_800M>, 1282 <&clk IMX8MN_SYS_PLL1_800M>; 1283 assigned-clock-rates = <400000000>, 1284 <400000000>, 1285 <800000000>, 1286 <400000000>, 1287 <1200000000>; 1288 power-domains = <&pgc_gpumix>; 1289 }; 1290 1291 gic: interrupt-controller@38800000 { 1292 compatible = "arm,gic-v3"; 1293 reg = <0x38800000 0x10000>, 1294 <0x38880000 0xc0000>; 1295 #interrupt-cells = <3>; 1296 interrupt-controller; 1297 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1298 }; 1299 1300 ddrc: memory-controller@3d400000 { 1301 compatible = "fsl,imx8mn-ddrc", "fsl,imx8m-ddrc"; 1302 reg = <0x3d400000 0x400000>; 1303 clock-names = "core", "pll", "alt", "apb"; 1304 clocks = <&clk IMX8MN_CLK_DRAM_CORE>, 1305 <&clk IMX8MN_DRAM_PLL>, 1306 <&clk IMX8MN_CLK_DRAM_ALT>, 1307 <&clk IMX8MN_CLK_DRAM_APB>; 1308 }; 1309 1310 ddr-pmu@3d800000 { 1311 compatible = "fsl,imx8mn-ddr-pmu", "fsl,imx8m-ddr-pmu"; 1312 reg = <0x3d800000 0x400000>; 1313 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1314 }; 1315 }; 1316 1317 usbphynop1: usbphynop1 { 1318 #phy-cells = <0>; 1319 compatible = "usb-nop-xceiv"; 1320 clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; 1321 assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; 1322 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>; 1323 clock-names = "main_clk"; 1324 power-domains = <&pgc_otg1>; 1325 }; 1326};
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