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imx8mn-tqma8mqnl.dtsi
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linux-6.19.14/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi
1// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) 2/* 3 * Copyright 2020-2021 TQ-Systems GmbH 4 */ 5 6#include "imx8mn.dtsi" 7 8/ { 9 model = "TQ-Systems i.MX8MN TQMa8MxNL"; 10 compatible = "tq,imx8mn-tqma8mqnl", "fsl,imx8mn"; 11 12 memory@40000000 { 13 device_type = "memory"; 14 /* our minimum RAM config will be 1024 MiB */ 15 reg = <0x00000000 0x40000000 0 0x40000000>; 16 }; 17 18 /* e-MMC IO, needed for HS modes */ 19 reg_vcc1v8: regulator-vcc1v8 { 20 compatible = "regulator-fixed"; 21 regulator-name = "TQMA8MXNL_VCC1V8"; 22 regulator-min-microvolt = <1800000>; 23 regulator-max-microvolt = <1800000>; 24 }; 25 26 reg_vcc3v3: regulator-vcc3v3 { 27 compatible = "regulator-fixed"; 28 regulator-name = "TQMA8MXNL_VCC3V3"; 29 regulator-min-microvolt = <3300000>; 30 regulator-max-microvolt = <3300000>; 31 }; 32 33 reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc { 34 compatible = "regulator-gpio"; 35 pinctrl-names = "default"; 36 pinctrl-0 = <&pinctrl_reg_usdhc2_vqmmc>; 37 regulator-name = "V_SD2"; 38 regulator-min-microvolt = <1800000>; 39 regulator-max-microvolt = <3300000>; 40 gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; 41 states = <1800000 0x1>, 42 <3300000 0x0>; 43 vin-supply = <&ldo5_reg>; 44 status = "disabled"; 45 }; 46 47 reserved-memory { 48 #address-cells = <2>; 49 #size-cells = <2>; 50 ranges; 51 52 /* global autoconfigured region for contiguous allocations */ 53 linux,cma { 54 compatible = "shared-dma-pool"; 55 reusable; 56 /* 640 MiB */ 57 size = <0 0x28000000>; 58 /* 1024 - 128 MiB, our minimum RAM config will be 1024 MiB */ 59 alloc-ranges = <0 0x40000000 0 0x78000000>; 60 linux,cma-default; 61 }; 62 }; 63}; 64 65&A53_0 { 66 cpu-supply = <&buck2_reg>; 67}; 68 69&easrc { 70 status = "okay"; 71}; 72 73&flexspi { 74 pinctrl-names = "default"; 75 pinctrl-0 = <&pinctrl_flexspi>; 76 status = "okay"; 77 78 flash0: flash@0 { 79 compatible = "jedec,spi-nor"; 80 reg = <0>; 81 spi-max-frequency = <84000000>; 82 spi-tx-bus-width = <1>; 83 spi-rx-bus-width = <4>; 84 vcc-supply = <&buck5_reg>; 85 86 partitions { 87 compatible = "fixed-partitions"; 88 #address-cells = <1>; 89 #size-cells = <1>; 90 }; 91 }; 92}; 93 94&i2c1 { 95 clock-frequency = <100000>; 96 pinctrl-names = "default", "gpio"; 97 pinctrl-0 = <&pinctrl_i2c1>; 98 pinctrl-1 = <&pinctrl_i2c1_gpio>; 99 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 100 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 101 status = "okay"; 102 103 sensor0: temperature-sensor@1b { 104 compatible = "nxp,se97b", "jedec,jc-42.4-temp"; 105 reg = <0x1b>; 106 }; 107 108 pca9450: pmic@25 { 109 compatible = "nxp,pca9450a"; 110 reg = <0x25>; 111 112 /* PMIC PCA9450 PMIC_nINT GPIO1_IO08 */ 113 pinctrl-0 = <&pinctrl_pmic>; 114 pinctrl-names = "default"; 115 interrupt-parent = <&gpio1>; 116 interrupts = <8 IRQ_TYPE_LEVEL_LOW>; 117 118 regulators { 119 /* V_0V85_SOC: 0.85 .. 0.95 */ 120 buck1_reg: BUCK1 { 121 regulator-name = "BUCK1"; 122 regulator-min-microvolt = <850000>; 123 regulator-max-microvolt = <950000>; 124 regulator-boot-on; 125 regulator-always-on; 126 regulator-ramp-delay = <3125>; 127 }; 128 129 /* VDD_ARM */ 130 buck2_reg: BUCK2 { 131 regulator-name = "BUCK2"; 132 regulator-min-microvolt = <850000>; 133 regulator-max-microvolt = <1000000>; 134 regulator-boot-on; 135 regulator-always-on; 136 nxp,dvs-run-voltage = <950000>; 137 nxp,dvs-standby-voltage = <850000>; 138 regulator-ramp-delay = <3125>; 139 }; 140 141 /* V_0V85_GPU / DRAM: shall be equal to BUCK1 for i.MX8MN */ 142 buck3_reg: BUCK3 { 143 regulator-name = "BUCK3"; 144 regulator-min-microvolt = <850000>; 145 regulator-max-microvolt = <950000>; 146 regulator-boot-on; 147 regulator-always-on; 148 regulator-ramp-delay = <3125>; 149 }; 150 151 /* VCC3V3 -> VMMC, ... must not be changed */ 152 buck4_reg: BUCK4 { 153 regulator-name = "BUCK4"; 154 regulator-min-microvolt = <3300000>; 155 regulator-max-microvolt = <3300000>; 156 regulator-boot-on; 157 regulator-always-on; 158 }; 159 160 /* V_1V8 -> VQMMC, SPI-NOR, ... must not be changed */ 161 buck5_reg: BUCK5 { 162 regulator-name = "BUCK5"; 163 regulator-min-microvolt = <1800000>; 164 regulator-max-microvolt = <1800000>; 165 regulator-boot-on; 166 regulator-always-on; 167 }; 168 169 /* V_1V1 -> RAM, ... must not be changed */ 170 buck6_reg: BUCK6 { 171 regulator-name = "BUCK6"; 172 regulator-min-microvolt = <1100000>; 173 regulator-max-microvolt = <1100000>; 174 regulator-boot-on; 175 regulator-always-on; 176 }; 177 178 /* V_1V8_SNVS */ 179 ldo1_reg: LDO1 { 180 regulator-name = "LDO1"; 181 regulator-min-microvolt = <1800000>; 182 regulator-max-microvolt = <1800000>; 183 regulator-boot-on; 184 regulator-always-on; 185 }; 186 187 /* V_0V8_SNVS */ 188 ldo2_reg: LDO2 { 189 regulator-name = "LDO2"; 190 regulator-min-microvolt = <800000>; 191 regulator-max-microvolt = <850000>; 192 regulator-boot-on; 193 regulator-always-on; 194 }; 195 196 /* V_1V8_ANA */ 197 ldo3_reg: LDO3 { 198 regulator-name = "LDO3"; 199 regulator-min-microvolt = <1800000>; 200 regulator-max-microvolt = <1800000>; 201 regulator-boot-on; 202 regulator-always-on; 203 }; 204 205 /* V_0V9_MIPI */ 206 ldo4_reg: LDO4 { 207 regulator-name = "LDO4"; 208 regulator-min-microvolt = <900000>; 209 regulator-max-microvolt = <900000>; 210 regulator-boot-on; 211 regulator-always-on; 212 }; 213 214 /* VCC SD IO - switched using SD2 VSELECT */ 215 ldo5_reg: LDO5 { 216 regulator-name = "LDO5"; 217 regulator-min-microvolt = <1800000>; 218 regulator-max-microvolt = <3300000>; 219 }; 220 }; 221 }; 222 223 pcf85063: rtc@51 { 224 compatible = "nxp,pcf85063a"; 225 reg = <0x51>; 226 quartz-load-femtofarads = <7000>; 227 }; 228 229 eeprom1: eeprom@53 { 230 compatible = "nxp,se97b", "atmel,24c02"; 231 read-only; 232 reg = <0x53>; 233 pagesize = <16>; 234 vcc-supply = <®_vcc3v3>; 235 }; 236 237 eeprom0: eeprom@57 { 238 compatible = "atmel,24c64"; 239 reg = <0x57>; 240 pagesize = <32>; 241 vcc-supply = <®_vcc3v3>; 242 }; 243}; 244 245&mipi_dsi { 246 vddcore-supply = <&ldo4_reg>; 247 vddio-supply = <&ldo3_reg>; 248}; 249 250&usdhc2 { 251 vqmmc-supply = <®_usdhc2_vqmmc>; 252}; 253 254&usdhc3 { 255 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 256 pinctrl-0 = <&pinctrl_usdhc3>; 257 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 258 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 259 bus-width = <8>; 260 non-removable; 261 no-sd; 262 no-sdio; 263 vmmc-supply = <®_vcc3v3>; 264 vqmmc-supply = <®_vcc1v8>; 265 status = "okay"; 266}; 267 268/* 269 * Attention: 270 * wdog reset is routed to PMIC, PMIC must be preconfigured to force POR 271 * without LDO for SNVS. GPIO1_IO02 must not be used as GPIO. 272 */ 273&wdog1 { 274 pinctrl-names = "default"; 275 pinctrl-0 = <&pinctrl_wdog>; 276 fsl,ext-reset-output; 277 status = "okay"; 278}; 279 280&iomuxc { 281 pinctrl_flexspi: flexspigrp { 282 fsl,pins = <MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x84>, 283 <MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x84>, 284 <MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x84>, 285 <MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x84>, 286 <MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x84>, 287 <MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x84>; 288 }; 289 290 pinctrl_i2c1: i2c1grp { 291 fsl,pins = <MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c4>, 292 <MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c4>; 293 }; 294 295 pinctrl_i2c1_gpio: i2c1gpiogrp { 296 fsl,pins = <MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c4>, 297 <MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c4>; 298 }; 299 300 pinctrl_pmic: pmicgrp { 301 fsl,pins = <MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x84>; 302 }; 303 304 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 305 fsl,pins = <MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x84>; 306 }; 307 308 pinctrl_reg_usdhc2_vqmmc: regusdhc2vqmmcgrp { 309 fsl,pins = <MX8MN_IOMUXC_GPIO1_IO04_GPIO1_IO4 0xc0>; 310 }; 311 312 pinctrl_usdhc3: usdhc3grp { 313 fsl,pins = <MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d4>, 314 <MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>, 315 <MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>, 316 <MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>, 317 <MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>, 318 <MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>, 319 <MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4>, 320 <MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4>, 321 <MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4>, 322 <MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4>, 323 <MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x84>, 324 <MX8MN_IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x84>; 325 }; 326 327 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 328 fsl,pins = <MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d2>, 329 <MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>, 330 <MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>, 331 <MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>, 332 <MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>, 333 <MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>, 334 <MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4>, 335 <MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4>, 336 <MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4>, 337 <MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4>, 338 <MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x84>, 339 <MX8MN_IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x84>; 340 }; 341 342 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 343 fsl,pins = <MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d6>, 344 <MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>, 345 <MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>, 346 <MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>, 347 <MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>, 348 <MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>, 349 <MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4>, 350 <MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4>, 351 <MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4>, 352 <MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4>, 353 <MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x84>, 354 <MX8MN_IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x84>; 355 }; 356 357 pinctrl_wdog: wdoggrp { 358 fsl,pins = <MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x84>; 359 }; 360};
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