imx8mn-bsh-smm-s2-display.dtsi

  1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2/*
  3 * Copyright 2021 BSH
  4 */
  5
  6/ {
  7	chosen {
  8		#address-cells = <2>;
  9		#size-cells = <2>;
 10		ranges;
 11
 12		framebuffer-panel0 {
 13			compatible = "simple-framebuffer";
 14			clocks = <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>, /* lcdif */
 15				 <&clk IMX8MN_CLK_DISP_APB_ROOT>,
 16				 <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
 17				 <&clk IMX8MN_VIDEO_PLL1>,
 18				 <&clk IMX8MN_CLK_DISP_AXI_ROOT>, /* pgc_dispmix */
 19				 <&clk IMX8MN_CLK_DISP_APB_ROOT>,
 20				 <&clk IMX8MN_CLK_DISP_AXI>,
 21				 <&clk IMX8MN_CLK_DISP_APB>,
 22				 <&clk IMX8MN_SYS_PLL2_1000M>,
 23				 <&clk IMX8MN_SYS_PLL1_800M>,
 24				 <&clk IMX8MN_CLK_DSI_CORE>, /* mipi_disi */
 25				 <&clk IMX8MN_CLK_DSI_PHY_REF>;
 26
 27			power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_LCDIF>,
 28					<&disp_blk_ctrl IMX8MN_DISPBLK_PD_MIPI_DSI>;
 29			dvdd-supply = <&reg_3v3_dvdd>;
 30			avdd-supply = <&reg_v3v3_avdd>;
 31			status = "disabled";
 32		};
 33	};
 34
 35	backlight: backlight {
 36		compatible = "pwm-backlight";
 37		pwms = <&pwm1 0 700000 0>;	/* 700000 ns = 1337Hz */
 38		brightness-levels = <0 100>;
 39		num-interpolated-steps = <100>;
 40		default-brightness-level = <50>;
 41		status = "okay";
 42	};
 43
 44	reg_3v3_dvdd: regulator-3v3-O3 {
 45		compatible = "regulator-fixed";
 46		pinctrl-names = "default";
 47		pinctrl-0 = <&pinctrl_dvdd>;
 48		regulator-name = "3v3-dvdd-supply";
 49		regulator-min-microvolt = <3300000>;
 50		regulator-max-microvolt = <3300000>;
 51		gpio = <&gpio1 7 GPIO_ACTIVE_LOW>;
 52	};
 53
 54	reg_v3v3_avdd: regulator-3v3-O2 {
 55		compatible = "regulator-fixed";
 56		pinctrl-names = "default";
 57		pinctrl-0 = <&pinctrl_avdd>;
 58		regulator-name = "3v3-avdd-supply";
 59		regulator-min-microvolt = <3300000>;
 60		regulator-max-microvolt = <3300000>;
 61		gpio = <&gpio1 5 GPIO_ACTIVE_LOW>;
 62	};
 63};
 64
 65&pwm1 {
 66	pinctrl-names = "default";
 67	pinctrl-0 = <&pinctrl_bl>;
 68	status = "okay";
 69};
 70
 71&lcdif {
 72	assigned-clocks = <&clk IMX8MN_VIDEO_PLL1>;
 73	assigned-clock-rates = <594000000>;
 74	status = "okay";
 75};
 76
 77&pgc_dispmix {
 78	assigned-clocks = <&clk IMX8MN_CLK_DISP_AXI>, <&clk IMX8MN_CLK_DISP_APB>;
 79	assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_1000M>, <&clk IMX8MN_SYS_PLL1_800M>;
 80	assigned-clock-rates = <500000000>, <200000000>;
 81};
 82
 83&mipi_dsi {
 84	#address-cells = <1>;
 85	#size-cells = <0>;
 86	samsung,esc-clock-frequency = <20000000>;
 87	samsung,pll-clock-frequency = <12000000>;
 88	status = "okay";
 89
 90	panel@0 {
 91		compatible = "sharp,ls068b3sx02", "syna,r63353";
 92		pinctrl-names = "default";
 93		pinctrl-0 = <&pinctrl_panel>;
 94		reg = <0>;
 95
 96		backlight = <&backlight>;
 97		dvdd-supply = <&reg_3v3_dvdd>;
 98		avdd-supply = <&reg_v3v3_avdd>;
 99		reset-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
100
101		port {
102			panel_in: endpoint {
103				remote-endpoint = <&mipi_dsi_out>;
104			};
105		};
106
107	};
108
109	ports {
110		port@1 {
111			reg = <1>;
112
113			mipi_dsi_out: endpoint {
114				remote-endpoint = <&panel_in>;
115			};
116		};
117	};
118};
119
120&gpu {
121	status = "okay";
122};
123
124&iomuxc {
125	pinctrl_avdd: avddgrp {
126		fsl,pins = <
127			MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5	0x16	/* VDD 3V3_VO2 */
128		>;
129	};
130
131	/* This is for both PWM and voltage regulators for display */
132	pinctrl_bl: blgrp {
133		fsl,pins = <
134			MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT	0x16
135		>;
136	};
137
138	pinctrl_dvdd: dvddgrp {
139		fsl,pins = <
140			MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7	0x16	/* VDD 3V3_VO3 */
141		>;
142	};
143
144	pinctrl_panel: panelgrp {
145		fsl,pins = <
146			MX8MN_IOMUXC_SAI3_RXC_GPIO4_IO29	0x16	/* panel reset */
147		>;
148	};
149};