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imx8mm.dtsi
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linux-6.19.14/arch/arm64/boot/dts/freescale/imx8mm.dtsi
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 */ 5 6#include <dt-bindings/clock/imx8mm-clock.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/input/input.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/power/imx8mm-power.h> 11#include <dt-bindings/reset/imx8mq-reset.h> 12#include <dt-bindings/thermal/thermal.h> 13 14#include "imx8mm-pinfunc.h" 15 16/ { 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 ethernet0 = &fec1; 23 gpio0 = &gpio1; 24 gpio1 = &gpio2; 25 gpio2 = &gpio3; 26 gpio3 = &gpio4; 27 gpio4 = &gpio5; 28 i2c0 = &i2c1; 29 i2c1 = &i2c2; 30 i2c2 = &i2c3; 31 i2c3 = &i2c4; 32 mmc0 = &usdhc1; 33 mmc1 = &usdhc2; 34 mmc2 = &usdhc3; 35 serial0 = &uart1; 36 serial1 = &uart2; 37 serial2 = &uart3; 38 serial3 = &uart4; 39 spi0 = &ecspi1; 40 spi1 = &ecspi2; 41 spi2 = &ecspi3; 42 }; 43 44 cpus { 45 #address-cells = <1>; 46 #size-cells = <0>; 47 48 idle-states { 49 entry-method = "psci"; 50 51 cpu_pd_wait: cpu-pd-wait { 52 compatible = "arm,idle-state"; 53 arm,psci-suspend-param = <0x0010033>; 54 local-timer-stop; 55 entry-latency-us = <1000>; 56 exit-latency-us = <700>; 57 min-residency-us = <2700>; 58 }; 59 }; 60 61 A53_0: cpu@0 { 62 device_type = "cpu"; 63 compatible = "arm,cortex-a53"; 64 reg = <0x0>; 65 clocks = <&clk IMX8MM_CLK_ARM>; 66 enable-method = "psci"; 67 i-cache-size = <0x8000>; 68 i-cache-line-size = <64>; 69 i-cache-sets = <256>; 70 d-cache-size = <0x8000>; 71 d-cache-line-size = <64>; 72 d-cache-sets = <128>; 73 next-level-cache = <&A53_L2>; 74 operating-points-v2 = <&a53_opp_table>; 75 nvmem-cells = <&cpu_speed_grade>; 76 nvmem-cell-names = "speed_grade"; 77 cpu-idle-states = <&cpu_pd_wait>; 78 #cooling-cells = <2>; 79 }; 80 81 A53_1: cpu@1 { 82 device_type = "cpu"; 83 compatible = "arm,cortex-a53"; 84 reg = <0x1>; 85 clocks = <&clk IMX8MM_CLK_ARM>; 86 enable-method = "psci"; 87 i-cache-size = <0x8000>; 88 i-cache-line-size = <64>; 89 i-cache-sets = <256>; 90 d-cache-size = <0x8000>; 91 d-cache-line-size = <64>; 92 d-cache-sets = <128>; 93 next-level-cache = <&A53_L2>; 94 operating-points-v2 = <&a53_opp_table>; 95 cpu-idle-states = <&cpu_pd_wait>; 96 #cooling-cells = <2>; 97 }; 98 99 A53_2: cpu@2 { 100 device_type = "cpu"; 101 compatible = "arm,cortex-a53"; 102 reg = <0x2>; 103 clocks = <&clk IMX8MM_CLK_ARM>; 104 enable-method = "psci"; 105 i-cache-size = <0x8000>; 106 i-cache-line-size = <64>; 107 i-cache-sets = <256>; 108 d-cache-size = <0x8000>; 109 d-cache-line-size = <64>; 110 d-cache-sets = <128>; 111 next-level-cache = <&A53_L2>; 112 operating-points-v2 = <&a53_opp_table>; 113 cpu-idle-states = <&cpu_pd_wait>; 114 #cooling-cells = <2>; 115 }; 116 117 A53_3: cpu@3 { 118 device_type = "cpu"; 119 compatible = "arm,cortex-a53"; 120 reg = <0x3>; 121 clocks = <&clk IMX8MM_CLK_ARM>; 122 enable-method = "psci"; 123 i-cache-size = <0x8000>; 124 i-cache-line-size = <64>; 125 i-cache-sets = <256>; 126 d-cache-size = <0x8000>; 127 d-cache-line-size = <64>; 128 d-cache-sets = <128>; 129 next-level-cache = <&A53_L2>; 130 operating-points-v2 = <&a53_opp_table>; 131 cpu-idle-states = <&cpu_pd_wait>; 132 #cooling-cells = <2>; 133 }; 134 135 A53_L2: l2-cache0 { 136 compatible = "cache"; 137 cache-level = <2>; 138 cache-unified; 139 cache-size = <0x80000>; 140 cache-line-size = <64>; 141 cache-sets = <512>; 142 }; 143 }; 144 145 a53_opp_table: opp-table { 146 compatible = "operating-points-v2"; 147 opp-shared; 148 149 opp-1200000000 { 150 opp-hz = /bits/ 64 <1200000000>; 151 opp-microvolt = <850000>; 152 opp-supported-hw = <0xe>, <0x7>; 153 clock-latency-ns = <150000>; 154 opp-suspend; 155 }; 156 157 opp-1600000000 { 158 opp-hz = /bits/ 64 <1600000000>; 159 opp-microvolt = <950000>; 160 opp-supported-hw = <0xc>, <0x7>; 161 clock-latency-ns = <150000>; 162 opp-suspend; 163 }; 164 165 opp-1800000000 { 166 opp-hz = /bits/ 64 <1800000000>; 167 opp-microvolt = <1000000>; 168 opp-supported-hw = <0x8>, <0x3>; 169 clock-latency-ns = <150000>; 170 opp-suspend; 171 }; 172 }; 173 174 osc_32k: clock-osc-32k { 175 compatible = "fixed-clock"; 176 #clock-cells = <0>; 177 clock-frequency = <32768>; 178 clock-output-names = "osc_32k"; 179 }; 180 181 osc_24m: clock-osc-24m { 182 compatible = "fixed-clock"; 183 #clock-cells = <0>; 184 clock-frequency = <24000000>; 185 clock-output-names = "osc_24m"; 186 }; 187 188 clk_ext1: clock-ext1 { 189 compatible = "fixed-clock"; 190 #clock-cells = <0>; 191 clock-frequency = <133000000>; 192 clock-output-names = "clk_ext1"; 193 }; 194 195 clk_ext2: clock-ext2 { 196 compatible = "fixed-clock"; 197 #clock-cells = <0>; 198 clock-frequency = <133000000>; 199 clock-output-names = "clk_ext2"; 200 }; 201 202 clk_ext3: clock-ext3 { 203 compatible = "fixed-clock"; 204 #clock-cells = <0>; 205 clock-frequency = <133000000>; 206 clock-output-names = "clk_ext3"; 207 }; 208 209 clk_ext4: clock-ext4 { 210 compatible = "fixed-clock"; 211 #clock-cells = <0>; 212 clock-frequency = <133000000>; 213 clock-output-names = "clk_ext4"; 214 }; 215 216 psci { 217 compatible = "arm,psci-1.0"; 218 method = "smc"; 219 }; 220 221 pmu { 222 compatible = "arm,cortex-a53-pmu"; 223 interrupts = <GIC_PPI 7 224 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 225 }; 226 227 timer { 228 compatible = "arm,armv8-timer"; 229 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */ 230 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */ 231 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */ 232 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */ 233 clock-frequency = <8000000>; 234 arm,no-tick-in-suspend; 235 }; 236 237 thermal-zones { 238 cpu-thermal { 239 polling-delay-passive = <250>; 240 polling-delay = <2000>; 241 thermal-sensors = <&tmu>; 242 trips { 243 cpu_alert0: trip0 { 244 temperature = <85000>; 245 hysteresis = <2000>; 246 type = "passive"; 247 }; 248 249 cpu_crit0: trip1 { 250 temperature = <95000>; 251 hysteresis = <2000>; 252 type = "critical"; 253 }; 254 }; 255 256 cooling-maps { 257 map0 { 258 trip = <&cpu_alert0>; 259 cooling-device = 260 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 261 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 262 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 263 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 264 }; 265 }; 266 }; 267 }; 268 269 usbphynop1: usbphynop1 { 270 #phy-cells = <0>; 271 compatible = "usb-nop-xceiv"; 272 clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; 273 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; 274 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; 275 clock-names = "main_clk"; 276 power-domains = <&pgc_otg1>; 277 }; 278 279 usbphynop2: usbphynop2 { 280 #phy-cells = <0>; 281 compatible = "usb-nop-xceiv"; 282 clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; 283 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; 284 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; 285 clock-names = "main_clk"; 286 power-domains = <&pgc_otg2>; 287 }; 288 289 soc: soc@0 { 290 compatible = "fsl,imx8mm-soc", "simple-bus"; 291 #address-cells = <1>; 292 #size-cells = <1>; 293 ranges = <0x0 0x0 0x0 0x3e000000>; 294 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; 295 nvmem-cells = <&imx8mm_uid>; 296 nvmem-cell-names = "soc_unique_id"; 297 298 aips1: bus@30000000 { 299 compatible = "fsl,aips-bus", "simple-bus"; 300 reg = <0x30000000 0x400000>; 301 #address-cells = <1>; 302 #size-cells = <1>; 303 ranges = <0x30000000 0x30000000 0x400000>; 304 305 spba2: spba-bus@30000000 { 306 compatible = "fsl,spba-bus", "simple-bus"; 307 #address-cells = <1>; 308 #size-cells = <1>; 309 reg = <0x30000000 0x100000>; 310 ranges; 311 312 sai1: sai@30010000 { 313 #sound-dai-cells = <0>; 314 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 315 reg = <0x30010000 0x10000>; 316 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 317 clocks = <&clk IMX8MM_CLK_SAI1_IPG>, 318 <&clk IMX8MM_CLK_SAI1_ROOT>, 319 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; 320 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 321 dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>; 322 dma-names = "rx", "tx"; 323 status = "disabled"; 324 }; 325 326 sai2: sai@30020000 { 327 #sound-dai-cells = <0>; 328 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 329 reg = <0x30020000 0x10000>; 330 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 331 clocks = <&clk IMX8MM_CLK_SAI2_IPG>, 332 <&clk IMX8MM_CLK_SAI2_ROOT>, 333 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; 334 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 335 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>; 336 dma-names = "rx", "tx"; 337 status = "disabled"; 338 }; 339 340 sai3: sai@30030000 { 341 #sound-dai-cells = <0>; 342 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 343 reg = <0x30030000 0x10000>; 344 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 345 clocks = <&clk IMX8MM_CLK_SAI3_IPG>, 346 <&clk IMX8MM_CLK_SAI3_ROOT>, 347 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; 348 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 349 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; 350 dma-names = "rx", "tx"; 351 status = "disabled"; 352 }; 353 354 sai5: sai@30050000 { 355 #sound-dai-cells = <0>; 356 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 357 reg = <0x30050000 0x10000>; 358 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 359 clocks = <&clk IMX8MM_CLK_SAI5_IPG>, 360 <&clk IMX8MM_CLK_SAI5_ROOT>, 361 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; 362 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 363 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; 364 dma-names = "rx", "tx"; 365 status = "disabled"; 366 }; 367 368 sai6: sai@30060000 { 369 #sound-dai-cells = <0>; 370 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 371 reg = <0x30060000 0x10000>; 372 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 373 clocks = <&clk IMX8MM_CLK_SAI6_IPG>, 374 <&clk IMX8MM_CLK_SAI6_ROOT>, 375 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; 376 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 377 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>; 378 dma-names = "rx", "tx"; 379 status = "disabled"; 380 }; 381 382 micfil: audio-controller@30080000 { 383 compatible = "fsl,imx8mm-micfil"; 384 reg = <0x30080000 0x10000>; 385 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 386 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 387 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 388 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 389 clocks = <&clk IMX8MM_CLK_PDM_IPG>, 390 <&clk IMX8MM_CLK_PDM_ROOT>, 391 <&clk IMX8MM_AUDIO_PLL1_OUT>, 392 <&clk IMX8MM_AUDIO_PLL2_OUT>, 393 <&clk IMX8MM_CLK_EXT3>; 394 clock-names = "ipg_clk", "ipg_clk_app", 395 "pll8k", "pll11k", "clkext3"; 396 dmas = <&sdma2 24 25 0x80000000>; 397 dma-names = "rx"; 398 #sound-dai-cells = <0>; 399 status = "disabled"; 400 }; 401 402 spdif1: spdif@30090000 { 403 compatible = "fsl,imx35-spdif"; 404 reg = <0x30090000 0x10000>; 405 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 406 clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, /* core */ 407 <&clk IMX8MM_CLK_24M>, /* rxtx0 */ 408 <&clk IMX8MM_CLK_SPDIF1>, /* rxtx1 */ 409 <&clk IMX8MM_CLK_DUMMY>, /* rxtx2 */ 410 <&clk IMX8MM_CLK_DUMMY>, /* rxtx3 */ 411 <&clk IMX8MM_CLK_DUMMY>, /* rxtx4 */ 412 <&clk IMX8MM_CLK_AUDIO_AHB>, /* rxtx5 */ 413 <&clk IMX8MM_CLK_DUMMY>, /* rxtx6 */ 414 <&clk IMX8MM_CLK_DUMMY>, /* rxtx7 */ 415 <&clk IMX8MM_CLK_DUMMY>; /* spba */ 416 clock-names = "core", "rxtx0", 417 "rxtx1", "rxtx2", 418 "rxtx3", "rxtx4", 419 "rxtx5", "rxtx6", 420 "rxtx7", "spba"; 421 dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>; 422 dma-names = "rx", "tx"; 423 status = "disabled"; 424 }; 425 }; 426 427 gpio1: gpio@30200000 { 428 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 429 reg = <0x30200000 0x10000>; 430 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 431 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 432 clocks = <&clk IMX8MM_CLK_GPIO1_ROOT>; 433 gpio-controller; 434 #gpio-cells = <2>; 435 interrupt-controller; 436 #interrupt-cells = <2>; 437 gpio-ranges = <&iomuxc 0 10 30>; 438 }; 439 440 gpio2: gpio@30210000 { 441 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 442 reg = <0x30210000 0x10000>; 443 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 444 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 445 clocks = <&clk IMX8MM_CLK_GPIO2_ROOT>; 446 gpio-controller; 447 #gpio-cells = <2>; 448 interrupt-controller; 449 #interrupt-cells = <2>; 450 gpio-ranges = <&iomuxc 0 40 21>; 451 }; 452 453 gpio3: gpio@30220000 { 454 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 455 reg = <0x30220000 0x10000>; 456 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 457 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 458 clocks = <&clk IMX8MM_CLK_GPIO3_ROOT>; 459 gpio-controller; 460 #gpio-cells = <2>; 461 interrupt-controller; 462 #interrupt-cells = <2>; 463 gpio-ranges = <&iomuxc 0 61 26>; 464 }; 465 466 gpio4: gpio@30230000 { 467 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 468 reg = <0x30230000 0x10000>; 469 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 470 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 471 clocks = <&clk IMX8MM_CLK_GPIO4_ROOT>; 472 gpio-controller; 473 #gpio-cells = <2>; 474 interrupt-controller; 475 #interrupt-cells = <2>; 476 gpio-ranges = <&iomuxc 0 87 32>; 477 }; 478 479 gpio5: gpio@30240000 { 480 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 481 reg = <0x30240000 0x10000>; 482 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 483 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 484 clocks = <&clk IMX8MM_CLK_GPIO5_ROOT>; 485 gpio-controller; 486 #gpio-cells = <2>; 487 interrupt-controller; 488 #interrupt-cells = <2>; 489 gpio-ranges = <&iomuxc 0 119 30>; 490 }; 491 492 tmu: tmu@30260000 { 493 compatible = "fsl,imx8mm-tmu"; 494 reg = <0x30260000 0x10000>; 495 clocks = <&clk IMX8MM_CLK_TMU_ROOT>; 496 nvmem-cells = <&tmu_calib>; 497 nvmem-cell-names = "calib"; 498 #thermal-sensor-cells = <0>; 499 }; 500 501 wdog1: watchdog@30280000 { 502 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt"; 503 reg = <0x30280000 0x10000>; 504 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 505 clocks = <&clk IMX8MM_CLK_WDOG1_ROOT>; 506 status = "disabled"; 507 }; 508 509 wdog2: watchdog@30290000 { 510 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt"; 511 reg = <0x30290000 0x10000>; 512 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 513 clocks = <&clk IMX8MM_CLK_WDOG2_ROOT>; 514 status = "disabled"; 515 }; 516 517 wdog3: watchdog@302a0000 { 518 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt"; 519 reg = <0x302a0000 0x10000>; 520 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 521 clocks = <&clk IMX8MM_CLK_WDOG3_ROOT>; 522 status = "disabled"; 523 }; 524 525 sdma2: dma-controller@302c0000 { 526 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma"; 527 reg = <0x302c0000 0x10000>; 528 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 529 clocks = <&clk IMX8MM_CLK_SDMA2_ROOT>, 530 <&clk IMX8MM_CLK_SDMA2_ROOT>; 531 clock-names = "ipg", "ahb"; 532 #dma-cells = <3>; 533 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 534 }; 535 536 sdma3: dma-controller@302b0000 { 537 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma"; 538 reg = <0x302b0000 0x10000>; 539 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 540 clocks = <&clk IMX8MM_CLK_SDMA3_ROOT>, 541 <&clk IMX8MM_CLK_SDMA3_ROOT>; 542 clock-names = "ipg", "ahb"; 543 #dma-cells = <3>; 544 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 545 }; 546 547 iomuxc: pinctrl@30330000 { 548 compatible = "fsl,imx8mm-iomuxc"; 549 reg = <0x30330000 0x10000>; 550 }; 551 552 gpr: syscon@30340000 { 553 compatible = "fsl,imx8mm-iomuxc-gpr", "syscon"; 554 reg = <0x30340000 0x10000>; 555 }; 556 557 ocotp: efuse@30350000 { 558 compatible = "fsl,imx8mm-ocotp", "syscon"; 559 reg = <0x30350000 0x10000>; 560 clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>; 561 /* For nvmem subnodes */ 562 #address-cells = <1>; 563 #size-cells = <1>; 564 565 /* 566 * The register address below maps to the MX8M 567 * Fusemap Description Table entries this way. 568 * Assuming 569 * reg = <ADDR SIZE>; 570 * then 571 * Fuse Address = (ADDR * 4) + 0x400 572 * Note that if SIZE is greater than 4, then 573 * each subsequent fuse is located at offset 574 * +0x10 in Fusemap Description Table (e.g. 575 * reg = <0x4 0x8> describes fuses 0x410 and 576 * 0x420). 577 */ 578 imx8mm_uid: unique-id@4 { /* 0x410-0x420 */ 579 reg = <0x4 0x8>; 580 }; 581 582 cpu_speed_grade: speed-grade@10 { /* 0x440 */ 583 reg = <0x10 4>; 584 }; 585 586 tmu_calib: calib@3c { /* 0x4f0 */ 587 reg = <0x3c 4>; 588 }; 589 590 fec_mac_address: mac-address@90 { /* 0x640 */ 591 reg = <0x90 6>; 592 }; 593 }; 594 595 anatop: clock-controller@30360000 { 596 compatible = "fsl,imx8mm-anatop"; 597 reg = <0x30360000 0x10000>; 598 #clock-cells = <1>; 599 }; 600 601 snvs: snvs@30370000 { 602 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; 603 reg = <0x30370000 0x10000>; 604 605 snvs_rtc: snvs-rtc-lp { 606 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 607 regmap = <&snvs>; 608 offset = <0x34>; 609 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 610 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 611 clocks = <&clk IMX8MM_CLK_SNVS_ROOT>; 612 clock-names = "snvs-rtc"; 613 }; 614 615 snvs_pwrkey: snvs-powerkey { 616 compatible = "fsl,sec-v4.0-pwrkey"; 617 regmap = <&snvs>; 618 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 619 clocks = <&clk IMX8MM_CLK_SNVS_ROOT>; 620 clock-names = "snvs-pwrkey"; 621 linux,keycode = <KEY_POWER>; 622 wakeup-source; 623 status = "disabled"; 624 }; 625 626 snvs_lpgpr: snvs-lpgpr { 627 compatible = "fsl,imx8mm-snvs-lpgpr", 628 "fsl,imx7d-snvs-lpgpr"; 629 }; 630 }; 631 632 clk: clock-controller@30380000 { 633 compatible = "fsl,imx8mm-ccm"; 634 reg = <0x30380000 0x10000>; 635 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 636 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 637 #clock-cells = <1>; 638 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, 639 <&clk_ext3>, <&clk_ext4>; 640 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", 641 "clk_ext3", "clk_ext4"; 642 assigned-clocks = <&clk IMX8MM_CLK_A53_SRC>, 643 <&clk IMX8MM_CLK_A53_CORE>, 644 <&clk IMX8MM_CLK_NOC>, 645 <&clk IMX8MM_CLK_AUDIO_AHB>, 646 <&clk IMX8MM_CLK_IPG_AUDIO_ROOT>, 647 <&clk IMX8MM_SYS_PLL3>, 648 <&clk IMX8MM_AUDIO_PLL1>; 649 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>, 650 <&clk IMX8MM_ARM_PLL_OUT>, 651 <&clk IMX8MM_SYS_PLL3_OUT>, 652 <&clk IMX8MM_SYS_PLL1_800M>; 653 assigned-clock-rates = <0>, <0>, <0>, 654 <400000000>, 655 <400000000>, 656 <750000000>, 657 <393216000>; 658 }; 659 660 src: reset-controller@30390000 { 661 compatible = "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon"; 662 reg = <0x30390000 0x10000>; 663 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 664 #reset-cells = <1>; 665 }; 666 667 gpc: gpc@303a0000 { 668 compatible = "fsl,imx8mm-gpc"; 669 reg = <0x303a0000 0x10000>; 670 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 671 interrupt-parent = <&gic>; 672 interrupt-controller; 673 #interrupt-cells = <3>; 674 675 pgc { 676 #address-cells = <1>; 677 #size-cells = <0>; 678 679 pgc_hsiomix: power-domain@0 { 680 #power-domain-cells = <0>; 681 reg = <IMX8MM_POWER_DOMAIN_HSIOMIX>; 682 clocks = <&clk IMX8MM_CLK_USB_BUS>; 683 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>; 684 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; 685 }; 686 687 pgc_pcie: power-domain@1 { 688 #power-domain-cells = <0>; 689 reg = <IMX8MM_POWER_DOMAIN_PCIE>; 690 power-domains = <&pgc_hsiomix>; 691 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>; 692 }; 693 694 pgc_otg1: power-domain@2 { 695 #power-domain-cells = <0>; 696 reg = <IMX8MM_POWER_DOMAIN_OTG1>; 697 }; 698 699 pgc_otg2: power-domain@3 { 700 #power-domain-cells = <0>; 701 reg = <IMX8MM_POWER_DOMAIN_OTG2>; 702 }; 703 704 pgc_gpumix: power-domain@4 { 705 #power-domain-cells = <0>; 706 reg = <IMX8MM_POWER_DOMAIN_GPUMIX>; 707 clocks = <&clk IMX8MM_CLK_GPU_BUS_ROOT>, 708 <&clk IMX8MM_CLK_GPU_AHB>; 709 assigned-clocks = <&clk IMX8MM_CLK_GPU_AXI>, 710 <&clk IMX8MM_CLK_GPU_AHB>; 711 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>, 712 <&clk IMX8MM_SYS_PLL1_800M>; 713 assigned-clock-rates = <800000000>, <400000000>; 714 }; 715 716 pgc_gpu: power-domain@5 { 717 #power-domain-cells = <0>; 718 reg = <IMX8MM_POWER_DOMAIN_GPU>; 719 clocks = <&clk IMX8MM_CLK_GPU_AHB>, 720 <&clk IMX8MM_CLK_GPU_BUS_ROOT>, 721 <&clk IMX8MM_CLK_GPU2D_ROOT>, 722 <&clk IMX8MM_CLK_GPU3D_ROOT>; 723 resets = <&src IMX8MQ_RESET_GPU_RESET>; 724 power-domains = <&pgc_gpumix>; 725 }; 726 727 pgc_vpumix: power-domain@6 { 728 #power-domain-cells = <0>; 729 reg = <IMX8MM_POWER_DOMAIN_VPUMIX>; 730 clocks = <&clk IMX8MM_CLK_VPU_DEC_ROOT>; 731 assigned-clocks = <&clk IMX8MM_CLK_VPU_BUS>; 732 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>; 733 }; 734 735 pgc_vpu_g1: power-domain@7 { 736 #power-domain-cells = <0>; 737 reg = <IMX8MM_POWER_DOMAIN_VPUG1>; 738 }; 739 740 pgc_vpu_g2: power-domain@8 { 741 #power-domain-cells = <0>; 742 reg = <IMX8MM_POWER_DOMAIN_VPUG2>; 743 }; 744 745 pgc_vpu_h1: power-domain@9 { 746 #power-domain-cells = <0>; 747 reg = <IMX8MM_POWER_DOMAIN_VPUH1>; 748 }; 749 750 pgc_dispmix: power-domain@10 { 751 #power-domain-cells = <0>; 752 reg = <IMX8MM_POWER_DOMAIN_DISPMIX>; 753 clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>, 754 <&clk IMX8MM_CLK_DISP_AXI_ROOT>; 755 assigned-clocks = <&clk IMX8MM_CLK_DISP_AXI>, 756 <&clk IMX8MM_CLK_DISP_APB>; 757 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>, 758 <&clk IMX8MM_SYS_PLL1_800M>; 759 assigned-clock-rates = <500000000>, <200000000>; 760 }; 761 762 pgc_mipi: power-domain@11 { 763 #power-domain-cells = <0>; 764 reg = <IMX8MM_POWER_DOMAIN_MIPI>; 765 }; 766 }; 767 }; 768 }; 769 770 aips2: bus@30400000 { 771 compatible = "fsl,aips-bus", "simple-bus"; 772 reg = <0x30400000 0x400000>; 773 #address-cells = <1>; 774 #size-cells = <1>; 775 ranges = <0x30400000 0x30400000 0x400000>; 776 777 pwm1: pwm@30660000 { 778 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; 779 reg = <0x30660000 0x10000>; 780 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 781 clocks = <&clk IMX8MM_CLK_PWM1_ROOT>, 782 <&clk IMX8MM_CLK_PWM1_ROOT>; 783 clock-names = "ipg", "per"; 784 #pwm-cells = <3>; 785 status = "disabled"; 786 }; 787 788 pwm2: pwm@30670000 { 789 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; 790 reg = <0x30670000 0x10000>; 791 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 792 clocks = <&clk IMX8MM_CLK_PWM2_ROOT>, 793 <&clk IMX8MM_CLK_PWM2_ROOT>; 794 clock-names = "ipg", "per"; 795 #pwm-cells = <3>; 796 status = "disabled"; 797 }; 798 799 pwm3: pwm@30680000 { 800 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; 801 reg = <0x30680000 0x10000>; 802 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 803 clocks = <&clk IMX8MM_CLK_PWM3_ROOT>, 804 <&clk IMX8MM_CLK_PWM3_ROOT>; 805 clock-names = "ipg", "per"; 806 #pwm-cells = <3>; 807 status = "disabled"; 808 }; 809 810 pwm4: pwm@30690000 { 811 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; 812 reg = <0x30690000 0x10000>; 813 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 814 clocks = <&clk IMX8MM_CLK_PWM4_ROOT>, 815 <&clk IMX8MM_CLK_PWM4_ROOT>; 816 clock-names = "ipg", "per"; 817 #pwm-cells = <3>; 818 status = "disabled"; 819 }; 820 821 system_counter: timer@306a0000 { 822 compatible = "nxp,sysctr-timer"; 823 reg = <0x306a0000 0x20000>; 824 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 825 clocks = <&osc_24m>; 826 clock-names = "per"; 827 }; 828 }; 829 830 aips3: bus@30800000 { 831 compatible = "fsl,aips-bus", "simple-bus"; 832 reg = <0x30800000 0x400000>; 833 #address-cells = <1>; 834 #size-cells = <1>; 835 ranges = <0x30800000 0x30800000 0x400000>, 836 <0x8000000 0x8000000 0x10000000>; 837 838 spba1: spba-bus@30800000 { 839 compatible = "fsl,spba-bus", "simple-bus"; 840 #address-cells = <1>; 841 #size-cells = <1>; 842 reg = <0x30800000 0x100000>; 843 ranges; 844 845 ecspi1: spi@30820000 { 846 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; 847 #address-cells = <1>; 848 #size-cells = <0>; 849 reg = <0x30820000 0x10000>; 850 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 851 clocks = <&clk IMX8MM_CLK_ECSPI1_ROOT>, 852 <&clk IMX8MM_CLK_ECSPI1_ROOT>; 853 clock-names = "ipg", "per"; 854 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; 855 dma-names = "rx", "tx"; 856 status = "disabled"; 857 }; 858 859 ecspi2: spi@30830000 { 860 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; 861 #address-cells = <1>; 862 #size-cells = <0>; 863 reg = <0x30830000 0x10000>; 864 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 865 clocks = <&clk IMX8MM_CLK_ECSPI2_ROOT>, 866 <&clk IMX8MM_CLK_ECSPI2_ROOT>; 867 clock-names = "ipg", "per"; 868 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; 869 dma-names = "rx", "tx"; 870 status = "disabled"; 871 }; 872 873 ecspi3: spi@30840000 { 874 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; 875 #address-cells = <1>; 876 #size-cells = <0>; 877 reg = <0x30840000 0x10000>; 878 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 879 clocks = <&clk IMX8MM_CLK_ECSPI3_ROOT>, 880 <&clk IMX8MM_CLK_ECSPI3_ROOT>; 881 clock-names = "ipg", "per"; 882 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; 883 dma-names = "rx", "tx"; 884 status = "disabled"; 885 }; 886 887 uart1: serial@30860000 { 888 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; 889 reg = <0x30860000 0x10000>; 890 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 891 clocks = <&clk IMX8MM_CLK_UART1_ROOT>, 892 <&clk IMX8MM_CLK_UART1_ROOT>; 893 clock-names = "ipg", "per"; 894 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; 895 dma-names = "rx", "tx"; 896 status = "disabled"; 897 }; 898 899 uart3: serial@30880000 { 900 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; 901 reg = <0x30880000 0x10000>; 902 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 903 clocks = <&clk IMX8MM_CLK_UART3_ROOT>, 904 <&clk IMX8MM_CLK_UART3_ROOT>; 905 clock-names = "ipg", "per"; 906 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; 907 dma-names = "rx", "tx"; 908 status = "disabled"; 909 }; 910 911 uart2: serial@30890000 { 912 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; 913 reg = <0x30890000 0x10000>; 914 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 915 clocks = <&clk IMX8MM_CLK_UART2_ROOT>, 916 <&clk IMX8MM_CLK_UART2_ROOT>; 917 clock-names = "ipg", "per"; 918 dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>; 919 dma-names = "rx", "tx"; 920 status = "disabled"; 921 }; 922 }; 923 924 crypto: crypto@30900000 { 925 compatible = "fsl,sec-v4.0"; 926 #address-cells = <1>; 927 #size-cells = <1>; 928 reg = <0x30900000 0x40000>; 929 ranges = <0 0x30900000 0x40000>; 930 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 931 clocks = <&clk IMX8MM_CLK_AHB>, 932 <&clk IMX8MM_CLK_IPG_ROOT>; 933 clock-names = "aclk", "ipg"; 934 935 sec_jr0: jr@1000 { 936 compatible = "fsl,sec-v4.0-job-ring"; 937 reg = <0x1000 0x1000>; 938 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 939 status = "disabled"; 940 }; 941 942 sec_jr1: jr@2000 { 943 compatible = "fsl,sec-v4.0-job-ring"; 944 reg = <0x2000 0x1000>; 945 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 946 }; 947 948 sec_jr2: jr@3000 { 949 compatible = "fsl,sec-v4.0-job-ring"; 950 reg = <0x3000 0x1000>; 951 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 952 }; 953 }; 954 955 i2c1: i2c@30a20000 { 956 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; 957 #address-cells = <1>; 958 #size-cells = <0>; 959 reg = <0x30a20000 0x10000>; 960 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 961 clocks = <&clk IMX8MM_CLK_I2C1_ROOT>; 962 status = "disabled"; 963 }; 964 965 i2c2: i2c@30a30000 { 966 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; 967 #address-cells = <1>; 968 #size-cells = <0>; 969 reg = <0x30a30000 0x10000>; 970 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 971 clocks = <&clk IMX8MM_CLK_I2C2_ROOT>; 972 status = "disabled"; 973 }; 974 975 i2c3: i2c@30a40000 { 976 #address-cells = <1>; 977 #size-cells = <0>; 978 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; 979 reg = <0x30a40000 0x10000>; 980 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 981 clocks = <&clk IMX8MM_CLK_I2C3_ROOT>; 982 status = "disabled"; 983 }; 984 985 i2c4: i2c@30a50000 { 986 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; 987 #address-cells = <1>; 988 #size-cells = <0>; 989 reg = <0x30a50000 0x10000>; 990 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 991 clocks = <&clk IMX8MM_CLK_I2C4_ROOT>; 992 status = "disabled"; 993 }; 994 995 uart4: serial@30a60000 { 996 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; 997 reg = <0x30a60000 0x10000>; 998 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 999 clocks = <&clk IMX8MM_CLK_UART4_ROOT>, 1000 <&clk IMX8MM_CLK_UART4_ROOT>; 1001 clock-names = "ipg", "per"; 1002 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; 1003 dma-names = "rx", "tx"; 1004 status = "disabled"; 1005 }; 1006 1007 mu: mailbox@30aa0000 { 1008 compatible = "fsl,imx8mm-mu", "fsl,imx6sx-mu"; 1009 reg = <0x30aa0000 0x10000>; 1010 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1011 clocks = <&clk IMX8MM_CLK_MU_ROOT>; 1012 #mbox-cells = <2>; 1013 }; 1014 1015 usdhc1: mmc@30b40000 { 1016 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 1017 reg = <0x30b40000 0x10000>; 1018 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1019 clocks = <&clk IMX8MM_CLK_IPG_ROOT>, 1020 <&clk IMX8MM_CLK_NAND_USDHC_BUS>, 1021 <&clk IMX8MM_CLK_USDHC1_ROOT>; 1022 clock-names = "ipg", "ahb", "per"; 1023 fsl,tuning-start-tap = <20>; 1024 fsl,tuning-step = <2>; 1025 bus-width = <4>; 1026 status = "disabled"; 1027 }; 1028 1029 usdhc2: mmc@30b50000 { 1030 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 1031 reg = <0x30b50000 0x10000>; 1032 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1033 clocks = <&clk IMX8MM_CLK_IPG_ROOT>, 1034 <&clk IMX8MM_CLK_NAND_USDHC_BUS>, 1035 <&clk IMX8MM_CLK_USDHC2_ROOT>; 1036 clock-names = "ipg", "ahb", "per"; 1037 fsl,tuning-start-tap = <20>; 1038 fsl,tuning-step = <2>; 1039 bus-width = <4>; 1040 status = "disabled"; 1041 }; 1042 1043 usdhc3: mmc@30b60000 { 1044 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 1045 reg = <0x30b60000 0x10000>; 1046 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 1047 clocks = <&clk IMX8MM_CLK_IPG_ROOT>, 1048 <&clk IMX8MM_CLK_NAND_USDHC_BUS>, 1049 <&clk IMX8MM_CLK_USDHC3_ROOT>; 1050 clock-names = "ipg", "ahb", "per"; 1051 fsl,tuning-start-tap = <20>; 1052 fsl,tuning-step = <2>; 1053 bus-width = <4>; 1054 status = "disabled"; 1055 }; 1056 1057 flexspi: spi@30bb0000 { 1058 #address-cells = <1>; 1059 #size-cells = <0>; 1060 compatible = "nxp,imx8mm-fspi"; 1061 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>; 1062 reg-names = "fspi_base", "fspi_mmap"; 1063 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1064 clocks = <&clk IMX8MM_CLK_QSPI_ROOT>, 1065 <&clk IMX8MM_CLK_QSPI_ROOT>; 1066 clock-names = "fspi_en", "fspi"; 1067 status = "disabled"; 1068 }; 1069 1070 sdma1: dma-controller@30bd0000 { 1071 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma"; 1072 reg = <0x30bd0000 0x10000>; 1073 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 1074 clocks = <&clk IMX8MM_CLK_SDMA1_ROOT>, 1075 <&clk IMX8MM_CLK_AHB>; 1076 clock-names = "ipg", "ahb"; 1077 #dma-cells = <3>; 1078 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1079 }; 1080 1081 fec1: ethernet@30be0000 { 1082 compatible = "fsl,imx8mm-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; 1083 reg = <0x30be0000 0x10000>; 1084 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1085 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1086 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1087 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1088 clocks = <&clk IMX8MM_CLK_ENET1_ROOT>, 1089 <&clk IMX8MM_CLK_ENET1_ROOT>, 1090 <&clk IMX8MM_CLK_ENET_TIMER>, 1091 <&clk IMX8MM_CLK_ENET_REF>, 1092 <&clk IMX8MM_CLK_ENET_PHY_REF>; 1093 clock-names = "ipg", "ahb", "ptp", 1094 "enet_clk_ref", "enet_out"; 1095 assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>, 1096 <&clk IMX8MM_CLK_ENET_TIMER>, 1097 <&clk IMX8MM_CLK_ENET_REF>, 1098 <&clk IMX8MM_CLK_ENET_PHY_REF>; 1099 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, 1100 <&clk IMX8MM_SYS_PLL2_100M>, 1101 <&clk IMX8MM_SYS_PLL2_125M>, 1102 <&clk IMX8MM_SYS_PLL2_50M>; 1103 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; 1104 fsl,num-tx-queues = <3>; 1105 fsl,num-rx-queues = <3>; 1106 nvmem-cells = <&fec_mac_address>; 1107 nvmem-cell-names = "mac-address"; 1108 fsl,stop-mode = <&gpr 0x10 3>; 1109 status = "disabled"; 1110 }; 1111 1112 }; 1113 1114 aips4: bus@32c00000 { 1115 compatible = "fsl,aips-bus", "simple-bus"; 1116 reg = <0x32c00000 0x400000>; 1117 #address-cells = <1>; 1118 #size-cells = <1>; 1119 ranges = <0x32c00000 0x32c00000 0x400000>; 1120 1121 lcdif: lcdif@32e00000 { 1122 compatible = "fsl,imx8mm-lcdif", "fsl,imx6sx-lcdif"; 1123 reg = <0x32e00000 0x10000>; 1124 clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>, 1125 <&clk IMX8MM_CLK_DISP_APB_ROOT>, 1126 <&clk IMX8MM_CLK_DISP_AXI_ROOT>; 1127 clock-names = "pix", "axi", "disp_axi"; 1128 assigned-clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>, 1129 <&clk IMX8MM_CLK_DISP_AXI>, 1130 <&clk IMX8MM_CLK_DISP_APB>; 1131 assigned-clock-parents = <&clk IMX8MM_VIDEO_PLL1_OUT>, 1132 <&clk IMX8MM_SYS_PLL2_1000M>, 1133 <&clk IMX8MM_SYS_PLL1_800M>; 1134 assigned-clock-rates = <24000000>, <500000000>, <200000000>; 1135 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1136 power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_LCDIF>; 1137 status = "disabled"; 1138 1139 port { 1140 lcdif_to_dsim: endpoint { 1141 remote-endpoint = <&dsim_from_lcdif>; 1142 }; 1143 }; 1144 }; 1145 1146 mipi_dsi: dsi@32e10000 { 1147 compatible = "fsl,imx8mm-mipi-dsim"; 1148 reg = <0x32e10000 0x400>; 1149 clocks = <&clk IMX8MM_CLK_DSI_CORE>, 1150 <&clk IMX8MM_CLK_DSI_PHY_REF>; 1151 clock-names = "bus_clk", "sclk_mipi"; 1152 assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>; 1153 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>; 1154 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 1155 power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_DSI>; 1156 status = "disabled"; 1157 1158 ports { 1159 #address-cells = <1>; 1160 #size-cells = <0>; 1161 1162 port@0 { 1163 reg = <0>; 1164 1165 dsim_from_lcdif: endpoint { 1166 remote-endpoint = <&lcdif_to_dsim>; 1167 }; 1168 }; 1169 1170 port@1 { 1171 reg = <1>; 1172 1173 mipi_dsi_out: endpoint { 1174 }; 1175 }; 1176 }; 1177 }; 1178 1179 csi: csi@32e20000 { 1180 compatible = "fsl,imx8mm-csi", "fsl,imx7-csi"; 1181 reg = <0x32e20000 0x1000>; 1182 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1183 clocks = <&clk IMX8MM_CLK_CSI1_ROOT>; 1184 clock-names = "mclk"; 1185 power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_CSI_BRIDGE>; 1186 status = "disabled"; 1187 1188 port { 1189 csi_in: endpoint { 1190 remote-endpoint = <&imx8mm_mipi_csi_out>; 1191 }; 1192 }; 1193 }; 1194 1195 disp_blk_ctrl: blk-ctrl@32e28000 { 1196 compatible = "fsl,imx8mm-disp-blk-ctrl", "syscon"; 1197 reg = <0x32e28000 0x100>; 1198 power-domains = <&pgc_dispmix>, <&pgc_dispmix>, 1199 <&pgc_dispmix>, <&pgc_mipi>, 1200 <&pgc_mipi>; 1201 power-domain-names = "bus", "csi-bridge", 1202 "lcdif", "mipi-dsi", 1203 "mipi-csi"; 1204 clocks = <&clk IMX8MM_CLK_DISP_AXI_ROOT>, 1205 <&clk IMX8MM_CLK_DISP_APB_ROOT>, 1206 <&clk IMX8MM_CLK_CSI1_ROOT>, 1207 <&clk IMX8MM_CLK_DISP_AXI_ROOT>, 1208 <&clk IMX8MM_CLK_DISP_APB_ROOT>, 1209 <&clk IMX8MM_CLK_DISP_ROOT>, 1210 <&clk IMX8MM_CLK_DSI_CORE>, 1211 <&clk IMX8MM_CLK_DSI_PHY_REF>, 1212 <&clk IMX8MM_CLK_CSI1_CORE>, 1213 <&clk IMX8MM_CLK_CSI1_PHY_REF>; 1214 clock-names = "csi-bridge-axi","csi-bridge-apb", 1215 "csi-bridge-core", "lcdif-axi", 1216 "lcdif-apb", "lcdif-pix", 1217 "dsi-pclk", "dsi-ref", 1218 "csi-aclk", "csi-pclk"; 1219 #power-domain-cells = <1>; 1220 }; 1221 1222 mipi_csi: mipi-csi@32e30000 { 1223 compatible = "fsl,imx8mm-mipi-csi2"; 1224 reg = <0x32e30000 0x1000>; 1225 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1226 assigned-clocks = <&clk IMX8MM_CLK_CSI1_CORE>; 1227 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>; 1228 1229 clock-frequency = <333000000>; 1230 clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>, 1231 <&clk IMX8MM_CLK_CSI1_ROOT>, 1232 <&clk IMX8MM_CLK_CSI1_PHY_REF>, 1233 <&clk IMX8MM_CLK_DISP_AXI_ROOT>; 1234 clock-names = "pclk", "wrap", "phy", "axi"; 1235 power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_CSI>; 1236 status = "disabled"; 1237 1238 ports { 1239 #address-cells = <1>; 1240 #size-cells = <0>; 1241 1242 port@0 { 1243 reg = <0>; 1244 }; 1245 1246 port@1 { 1247 reg = <1>; 1248 1249 imx8mm_mipi_csi_out: endpoint { 1250 remote-endpoint = <&csi_in>; 1251 }; 1252 }; 1253 }; 1254 }; 1255 1256 usbotg1: usb@32e40000 { 1257 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; 1258 reg = <0x32e40000 0x200>; 1259 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1260 clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; 1261 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>; 1262 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; 1263 phys = <&usbphynop1>; 1264 fsl,usbmisc = <&usbmisc1 0>; 1265 power-domains = <&pgc_hsiomix>; 1266 status = "disabled"; 1267 }; 1268 1269 usbmisc1: usbmisc@32e40200 { 1270 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc", 1271 "fsl,imx6q-usbmisc"; 1272 #index-cells = <1>; 1273 reg = <0x32e40200 0x200>; 1274 }; 1275 1276 usbotg2: usb@32e50000 { 1277 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; 1278 reg = <0x32e50000 0x200>; 1279 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1280 clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; 1281 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>; 1282 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; 1283 phys = <&usbphynop2>; 1284 fsl,usbmisc = <&usbmisc2 0>; 1285 power-domains = <&pgc_hsiomix>; 1286 status = "disabled"; 1287 }; 1288 1289 usbmisc2: usbmisc@32e50200 { 1290 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc", 1291 "fsl,imx6q-usbmisc"; 1292 #index-cells = <1>; 1293 reg = <0x32e50200 0x200>; 1294 }; 1295 1296 pcie_phy: pcie-phy@32f00000 { 1297 compatible = "fsl,imx8mm-pcie-phy"; 1298 reg = <0x32f00000 0x10000>; 1299 clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; 1300 clock-names = "ref"; 1301 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; 1302 assigned-clock-rates = <100000000>; 1303 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_100M>; 1304 resets = <&src IMX8MQ_RESET_PCIEPHY>; 1305 reset-names = "pciephy"; 1306 #phy-cells = <0>; 1307 status = "disabled"; 1308 }; 1309 }; 1310 1311 dma_apbh: dma-controller@33000000 { 1312 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; 1313 reg = <0x33000000 0x2000>; 1314 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1315 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1316 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1317 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1318 #dma-cells = <1>; 1319 dma-channels = <4>; 1320 clocks = <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; 1321 }; 1322 1323 gpmi: nand-controller@33002000 { 1324 compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand"; 1325 #address-cells = <1>; 1326 #size-cells = <0>; 1327 reg = <0x33002000 0x2000>, <0x33004000 0x4000>; 1328 reg-names = "gpmi-nand", "bch"; 1329 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1330 interrupt-names = "bch"; 1331 clocks = <&clk IMX8MM_CLK_NAND_ROOT>, 1332 <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; 1333 clock-names = "gpmi_io", "gpmi_bch_apb"; 1334 dmas = <&dma_apbh 0>; 1335 dma-names = "rx-tx"; 1336 status = "disabled"; 1337 }; 1338 1339 pcie0: pcie@33800000 { 1340 compatible = "fsl,imx8mm-pcie"; 1341 reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>; 1342 reg-names = "dbi", "config"; 1343 #address-cells = <3>; 1344 #size-cells = <2>; 1345 device_type = "pci"; 1346 bus-range = <0x00 0xff>; 1347 ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */ 1348 <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ 1349 num-lanes = <1>; 1350 num-viewport = <4>; 1351 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1352 interrupt-names = "msi"; 1353 #interrupt-cells = <1>; 1354 interrupt-map-mask = <0 0 0 0x7>; 1355 interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1356 <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1357 <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1358 <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1359 fsl,max-link-speed = <2>; 1360 linux,pci-domain = <0>; 1361 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, 1362 <&clk IMX8MM_CLK_PCIE1_PHY>, 1363 <&clk IMX8MM_CLK_PCIE1_AUX>; 1364 clock-names = "pcie", "pcie_bus", "pcie_aux"; 1365 power-domains = <&pgc_pcie>; 1366 resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, 1367 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; 1368 reset-names = "apps", "turnoff"; 1369 phys = <&pcie_phy>; 1370 phy-names = "pcie-phy"; 1371 status = "disabled"; 1372 }; 1373 1374 pcie0_ep: pcie-ep@33800000 { 1375 compatible = "fsl,imx8mm-pcie-ep"; 1376 reg = <0x33800000 0x100000>, 1377 <0x18000000 0x8000000>, 1378 <0x33900000 0x100000>, 1379 <0x33b00000 0x100000>; 1380 reg-names = "dbi", "addr_space", "dbi2", "atu"; 1381 num-lanes = <1>; 1382 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1383 interrupt-names = "dma"; 1384 fsl,max-link-speed = <2>; 1385 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, 1386 <&clk IMX8MM_CLK_PCIE1_PHY>, 1387 <&clk IMX8MM_CLK_PCIE1_AUX>; 1388 clock-names = "pcie", "pcie_bus", "pcie_aux"; 1389 power-domains = <&pgc_pcie>; 1390 resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, 1391 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; 1392 reset-names = "apps", "turnoff"; 1393 phys = <&pcie_phy>; 1394 phy-names = "pcie-phy"; 1395 num-ib-windows = <4>; 1396 num-ob-windows = <4>; 1397 status = "disabled"; 1398 }; 1399 1400 gpu_3d: gpu@38000000 { 1401 compatible = "vivante,gc"; 1402 reg = <0x38000000 0x8000>; 1403 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1404 clocks = <&clk IMX8MM_CLK_GPU_AHB>, 1405 <&clk IMX8MM_CLK_GPU_BUS_ROOT>, 1406 <&clk IMX8MM_CLK_GPU3D_ROOT>, 1407 <&clk IMX8MM_CLK_GPU3D_ROOT>; 1408 clock-names = "reg", "bus", "core", "shader"; 1409 assigned-clocks = <&clk IMX8MM_CLK_GPU3D_CORE>, 1410 <&clk IMX8MM_GPU_PLL_OUT>; 1411 assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>; 1412 assigned-clock-rates = <0>, <800000000>; 1413 power-domains = <&pgc_gpu>; 1414 }; 1415 1416 gpu_2d: gpu@38008000 { 1417 compatible = "vivante,gc"; 1418 reg = <0x38008000 0x8000>; 1419 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1420 clocks = <&clk IMX8MM_CLK_GPU_AHB>, 1421 <&clk IMX8MM_CLK_GPU_BUS_ROOT>, 1422 <&clk IMX8MM_CLK_GPU2D_ROOT>; 1423 clock-names = "reg", "bus", "core"; 1424 assigned-clocks = <&clk IMX8MM_CLK_GPU2D_CORE>, 1425 <&clk IMX8MM_GPU_PLL_OUT>; 1426 assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>; 1427 assigned-clock-rates = <0>, <800000000>; 1428 power-domains = <&pgc_gpu>; 1429 }; 1430 1431 vpu_g1: video-codec@38300000 { 1432 compatible = "nxp,imx8mm-vpu-g1"; 1433 reg = <0x38300000 0x10000>; 1434 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1435 clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>; 1436 power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G1>; 1437 }; 1438 1439 vpu_g2: video-codec@38310000 { 1440 compatible = "nxp,imx8mq-vpu-g2"; 1441 reg = <0x38310000 0x10000>; 1442 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1443 clocks = <&clk IMX8MM_CLK_VPU_G2_ROOT>; 1444 power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G2>; 1445 }; 1446 1447 vpu_blk_ctrl: blk-ctrl@38330000 { 1448 compatible = "fsl,imx8mm-vpu-blk-ctrl", "syscon"; 1449 reg = <0x38330000 0x100>; 1450 power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>, 1451 <&pgc_vpu_g2>, <&pgc_vpu_h1>; 1452 power-domain-names = "bus", "g1", "g2", "h1"; 1453 clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>, 1454 <&clk IMX8MM_CLK_VPU_G2_ROOT>, 1455 <&clk IMX8MM_CLK_VPU_H1_ROOT>; 1456 clock-names = "g1", "g2", "h1"; 1457 assigned-clocks = <&clk IMX8MM_CLK_VPU_G1>, 1458 <&clk IMX8MM_CLK_VPU_G2>; 1459 assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>, 1460 <&clk IMX8MM_VPU_PLL_OUT>; 1461 assigned-clock-rates = <600000000>, 1462 <600000000>; 1463 #power-domain-cells = <1>; 1464 }; 1465 1466 gic: interrupt-controller@38800000 { 1467 compatible = "arm,gic-v3"; 1468 reg = <0x38800000 0x10000>, /* GIC Dist */ 1469 <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */ 1470 #address-cells = <0>; 1471 #interrupt-cells = <3>; 1472 interrupt-controller; 1473 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1474 }; 1475 1476 ddrc: memory-controller@3d400000 { 1477 compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc"; 1478 reg = <0x3d400000 0x400000>; 1479 clock-names = "core", "pll", "alt", "apb"; 1480 clocks = <&clk IMX8MM_CLK_DRAM_CORE>, 1481 <&clk IMX8MM_DRAM_PLL>, 1482 <&clk IMX8MM_CLK_DRAM_ALT>, 1483 <&clk IMX8MM_CLK_DRAM_APB>; 1484 }; 1485 1486 ddr-pmu@3d800000 { 1487 compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu"; 1488 reg = <0x3d800000 0x400000>; 1489 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1490 }; 1491 }; 1492};
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