imx8mm-venice-gw700x.dtsi

  1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2/*
  3 * Copyright 2020 Gateworks Corporation
  4 */
  5
  6#include <dt-bindings/gpio/gpio.h>
  7#include <dt-bindings/input/linux-event-codes.h>
  8#include <dt-bindings/leds/common.h>
  9#include <dt-bindings/net/ti-dp83867.h>
 10
 11/ {
 12	aliases {
 13		rtc0 = &gsc_rtc;
 14		rtc1 = &snvs_rtc;
 15	};
 16
 17	memory@40000000 {
 18		device_type = "memory";
 19		reg = <0x0 0x40000000 0 0x80000000>;
 20	};
 21
 22	gpio-keys {
 23		compatible = "gpio-keys";
 24
 25		key-user-pb {
 26			label = "user_pb";
 27			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
 28			linux,code = <BTN_0>;
 29		};
 30
 31		key-user-pb1x {
 32			label = "user_pb1x";
 33			linux,code = <BTN_1>;
 34			interrupt-parent = <&gsc>;
 35			interrupts = <0>;
 36		};
 37
 38		key-erased {
 39			label = "key_erased";
 40			linux,code = <BTN_2>;
 41			interrupt-parent = <&gsc>;
 42			interrupts = <1>;
 43		};
 44
 45		key-eeprom-wp {
 46			label = "eeprom_wp";
 47			linux,code = <BTN_3>;
 48			interrupt-parent = <&gsc>;
 49			interrupts = <2>;
 50		};
 51
 52		key-tamper {
 53			label = "tamper";
 54			linux,code = <BTN_4>;
 55			interrupt-parent = <&gsc>;
 56			interrupts = <5>;
 57		};
 58
 59		switch-hold {
 60			label = "switch_hold";
 61			linux,code = <BTN_5>;
 62			interrupt-parent = <&gsc>;
 63			interrupts = <7>;
 64		};
 65	};
 66};
 67
 68&A53_0 {
 69	cpu-supply = <&buck3_reg>;
 70};
 71
 72&A53_1 {
 73	cpu-supply = <&buck3_reg>;
 74};
 75
 76&A53_2 {
 77	cpu-supply = <&buck3_reg>;
 78};
 79
 80&A53_3 {
 81	cpu-supply = <&buck3_reg>;
 82};
 83
 84&ddrc {
 85	operating-points-v2 = <&ddrc_opp_table>;
 86
 87	ddrc_opp_table: opp-table {
 88		compatible = "operating-points-v2";
 89
 90		opp-25000000 {
 91			opp-hz = /bits/ 64 <25000000>;
 92		};
 93
 94		opp-100000000 {
 95			opp-hz = /bits/ 64 <100000000>;
 96		};
 97
 98		opp-750000000 {
 99			opp-hz = /bits/ 64 <750000000>;
100		};
101	};
102};
103
104&fec1 {
105	pinctrl-names = "default";
106	pinctrl-0 = <&pinctrl_fec1>;
107	phy-mode = "rgmii-id";
108	phy-handle = <&ethphy0>;
109	status = "okay";
110
111	mdio {
112		#address-cells = <1>;
113		#size-cells = <0>;
114
115		ethphy0: ethernet-phy@0 {
116			compatible = "ethernet-phy-ieee802.3-c22";
117			reg = <0>;
118			ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
119			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
120			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
121			tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
122			rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
123
124			leds {
125				#address-cells = <1>;
126				#size-cells = <0>;
127
128				led@1 {
129					reg = <1>;
130					color = <LED_COLOR_ID_AMBER>;
131					function = LED_FUNCTION_LAN;
132					default-state = "keep";
133				};
134
135				led@2 {
136					reg = <2>;
137					color = <LED_COLOR_ID_GREEN>;
138					function = LED_FUNCTION_LAN;
139					default-state = "keep";
140				};
141			};
142		};
143	};
144};
145
146&i2c1 {
147	clock-frequency = <100000>;
148	pinctrl-names = "default", "gpio";
149	pinctrl-0 = <&pinctrl_i2c1>;
150	pinctrl-1 = <&pinctrl_i2c1_gpio>;
151	scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
152	sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
153	status = "okay";
154
155	gsc: gsc@20 {
156		compatible = "gw,gsc";
157		reg = <0x20>;
158		pinctrl-0 = <&pinctrl_gsc>;
159		interrupt-parent = <&gpio2>;
160		interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
161		interrupt-controller;
162		#interrupt-cells = <1>;
163		#address-cells = <1>;
164		#size-cells = <0>;
165
166		adc {
167			compatible = "gw,gsc-adc";
168			#address-cells = <1>;
169			#size-cells = <0>;
170
171			channel@6 {
172				gw,mode = <0>;
173				reg = <0x06>;
174				label = "temp";
175			};
176
177			channel@8 {
178				gw,mode = <3>;
179				reg = <0x08>;
180				label = "vdd_bat";
181			};
182
183			channel@16 {
184				gw,mode = <4>;
185				reg = <0x16>;
186				label = "fan_tach";
187			};
188
189			channel@82 {
190				gw,mode = <2>;
191				reg = <0x82>;
192				label = "vdd_vin";
193				gw,voltage-divider-ohms = <22100 1000>;
194			};
195
196			channel@84 {
197				gw,mode = <2>;
198				reg = <0x84>;
199				label = "vdd_adc1";
200				gw,voltage-divider-ohms = <10000 10000>;
201			};
202
203			channel@86 {
204				gw,mode = <2>;
205				reg = <0x86>;
206				label = "vdd_adc2";
207				gw,voltage-divider-ohms = <10000 10000>;
208			};
209
210			channel@88 {
211				gw,mode = <2>;
212				reg = <0x88>;
213				label = "vdd_dram";
214			};
215
216			channel@8c {
217				gw,mode = <2>;
218				reg = <0x8c>;
219				label = "vdd_1p2";
220			};
221
222			channel@8e {
223				gw,mode = <2>;
224				reg = <0x8e>;
225				label = "vdd_1p0";
226			};
227
228			channel@90 {
229				gw,mode = <2>;
230				reg = <0x90>;
231				label = "vdd_2p5";
232				gw,voltage-divider-ohms = <10000 10000>;
233			};
234
235			channel@92 {
236				gw,mode = <2>;
237				reg = <0x92>;
238				label = "vdd_3p3";
239				gw,voltage-divider-ohms = <10000 10000>;
240			};
241
242			channel@98 {
243				gw,mode = <2>;
244				reg = <0x98>;
245				label = "vdd_0p95";
246			};
247
248			channel@9a {
249				gw,mode = <2>;
250				reg = <0x9a>;
251				label = "vdd_1p8";
252			};
253
254			channel@a2 {
255				gw,mode = <2>;
256				reg = <0xa2>;
257				label = "vdd_gsc";
258				gw,voltage-divider-ohms = <10000 10000>;
259			};
260		};
261
262		fan-controller@0 {
263			compatible = "gw,gsc-fan";
264			reg = <0x0a>;
265		};
266	};
267
268	gpio: gpio@23 {
269		compatible = "nxp,pca9555";
270		reg = <0x23>;
271		gpio-controller;
272		#gpio-cells = <2>;
273		interrupt-parent = <&gsc>;
274		interrupts = <4>;
275	};
276
277	eeprom@50 {
278		compatible = "atmel,24c02";
279		reg = <0x50>;
280		pagesize = <16>;
281	};
282
283	eeprom@51 {
284		compatible = "atmel,24c02";
285		reg = <0x51>;
286		pagesize = <16>;
287	};
288
289	eeprom@52 {
290		compatible = "atmel,24c02";
291		reg = <0x52>;
292		pagesize = <16>;
293	};
294
295	eeprom@53 {
296		compatible = "atmel,24c02";
297		reg = <0x53>;
298		pagesize = <16>;
299	};
300
301	gsc_rtc: rtc@68 {
302		compatible = "dallas,ds1672";
303		reg = <0x68>;
304	};
305
306	pmic@69 {
307		compatible = "mps,mp5416";
308		reg = <0x69>;
309
310		regulators {
311			/* vdd_0p95: DRAM/GPU/VPU */
312			buck1 {
313				regulator-name = "buck1";
314				regulator-min-microvolt = <800000>;
315				regulator-max-microvolt = <1000000>;
316				regulator-min-microamp = <3800000>;
317				regulator-max-microamp = <6800000>;
318				regulator-boot-on;
319				regulator-always-on;
320			};
321
322			/* vdd_soc */
323			buck2 {
324				regulator-name = "buck2";
325				regulator-min-microvolt = <800000>;
326				regulator-max-microvolt = <900000>;
327				regulator-min-microamp = <2200000>;
328				regulator-max-microamp = <5200000>;
329				regulator-boot-on;
330				regulator-always-on;
331			};
332
333			/* vdd_arm */
334			buck3_reg: buck3 {
335				regulator-name = "buck3";
336				regulator-min-microvolt = <800000>;
337				regulator-max-microvolt = <1000000>;
338				regulator-min-microamp = <3800000>;
339				regulator-max-microamp = <6800000>;
340				regulator-always-on;
341			};
342
343			/* vdd_1p8 */
344			buck4 {
345				regulator-name = "buck4";
346				regulator-min-microvolt = <1800000>;
347				regulator-max-microvolt = <1800000>;
348				regulator-min-microamp = <2200000>;
349				regulator-max-microamp = <5200000>;
350				regulator-boot-on;
351				regulator-always-on;
352			};
353
354			/* nvcc_snvs_1p8 */
355			ldo1 {
356				regulator-name = "ldo1";
357				regulator-min-microvolt = <1800000>;
358				regulator-max-microvolt = <1800000>;
359				regulator-boot-on;
360				regulator-always-on;
361			};
362
363			/* vdd_snvs_0p8 */
364			ldo2 {
365				regulator-name = "ldo2";
366				regulator-min-microvolt = <800000>;
367				regulator-max-microvolt = <800000>;
368				regulator-boot-on;
369				regulator-always-on;
370			};
371
372			/* vdd_0p9 */
373			ldo3 {
374				regulator-name = "ldo3";
375				regulator-min-microvolt = <900000>;
376				regulator-max-microvolt = <900000>;
377				regulator-boot-on;
378				regulator-always-on;
379			};
380
381			/* vdd_1p8 */
382			ldo4 {
383				regulator-name = "ldo4";
384				regulator-min-microvolt = <1800000>;
385				regulator-max-microvolt = <1800000>;
386				regulator-boot-on;
387				regulator-always-on;
388			};
389		};
390	};
391};
392
393&i2c2 {
394	clock-frequency = <400000>;
395	pinctrl-names = "default", "gpio";
396	pinctrl-0 = <&pinctrl_i2c2>;
397	pinctrl-1 = <&pinctrl_i2c2_gpio>;
398	scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
399	sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
400	status = "okay";
401
402	eeprom@52 {
403		compatible = "atmel,24c32";
404		reg = <0x52>;
405		pagesize = <32>;
406	};
407};
408
409/* console */
410&uart2 {
411	pinctrl-names = "default";
412	pinctrl-0 = <&pinctrl_uart2>;
413	status = "okay";
414};
415
416/* eMMC */
417&usdhc3 {
418	pinctrl-names = "default", "state_100mhz", "state_200mhz";
419	pinctrl-0 = <&pinctrl_usdhc3>;
420	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
421	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
422	assigned-clocks = <&clk IMX8MM_CLK_USDHC3>;
423	assigned-clock-rates = <400000000>;
424	bus-width = <8>;
425	non-removable;
426	status = "okay";
427};
428
429&wdog1 {
430	pinctrl-names = "default";
431	pinctrl-0 = <&pinctrl_wdog>;
432	fsl,ext-reset-output;
433	status = "okay";
434};
435
436&iomuxc {
437	pinctrl_fec1: fec1grp {
438		fsl,pins = <
439			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3
440			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
441			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
442			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
443			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
444			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
445			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
446			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
447			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
448			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
449			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x0
450			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
451			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
452			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
453			MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0			0x19
454		>;
455	};
456
457	pinctrl_gsc: gscgrp {
458		fsl,pins = <
459			MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6	0x159
460		>;
461	};
462
463	pinctrl_i2c1: i2c1grp {
464		fsl,pins = <
465			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL		0x400001c3
466			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA		0x400001c3
467		>;
468	};
469
470	pinctrl_i2c1_gpio: i2c1gpiogrp {
471		fsl,pins = <
472			MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14	0x400001c3
473			MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15	0x400001c3
474		>;
475	};
476
477	pinctrl_i2c2: i2c2grp {
478		fsl,pins = <
479			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL		0x400001c3
480			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA		0x400001c3
481		>;
482	};
483
484	pinctrl_i2c2_gpio: i2c2gpiogrp {
485		fsl,pins = <
486			MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16	0x400001c3
487			MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17	0x400001c3
488		>;
489	};
490
491	pinctrl_uart2: uart2grp {
492		fsl,pins = <
493			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140
494			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140
495		>;
496	};
497
498	pinctrl_usdhc3: usdhc3grp {
499		fsl,pins = <
500			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x190
501			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d0
502			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d0
503			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d0
504			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d0
505			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d0
506			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d0
507			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d0
508			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d0
509			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d0
510			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x190
511		>;
512	};
513
514	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
515		fsl,pins = <
516			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x194
517			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d4
518			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d4
519			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d4
520			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d4
521			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d4
522			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d4
523			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d4
524			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d4
525			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d4
526			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x194
527		>;
528	};
529
530	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
531		fsl,pins = <
532			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x196
533			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d6
534			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d6
535			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d6
536			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d6
537			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d6
538			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d6
539			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d6
540			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d6
541			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d6
542			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x196
543		>;
544	};
545
546	pinctrl_wdog: wdoggrp {
547		fsl,pins = <
548			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0xc6
549		>;
550	};
551};