FILE
imx8mm-phycore-som.dtsi
File preview with syntax highlighting.
linux-6.19.14/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi
1// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) 2/* 3 * Copyright (C) 2022 PHYTEC Messtechnik GmbH 4 */ 5 6#include "imx8mm.dtsi" 7#include <dt-bindings/net/ti-dp83867.h> 8 9/ { 10 model = "PHYTEC phyCORE-i.MX8MM"; 11 compatible = "phytec,imx8mm-phycore-som", "fsl,imx8mm"; 12 13 aliases { 14 rtc0 = &rv3028; 15 rtc1 = &snvs_rtc; 16 }; 17 18 memory@40000000 { 19 device_type = "memory"; 20 reg = <0x0 0x40000000 0 0x80000000>; 21 }; 22 23 reg_vdd_3v3_s: regulator-vdd-3v3-s { 24 compatible = "regulator-fixed"; 25 regulator-always-on; 26 regulator-boot-on; 27 regulator-max-microvolt = <3300000>; 28 regulator-min-microvolt = <3300000>; 29 regulator-name = "VDD_3V3_S"; 30 }; 31}; 32 33&A53_0 { 34 cpu-supply = <®_vdd_arm>; 35}; 36 37&A53_1 { 38 cpu-supply = <®_vdd_arm>; 39}; 40 41&A53_2 { 42 cpu-supply = <®_vdd_arm>; 43}; 44 45&A53_3 { 46 cpu-supply = <®_vdd_arm>; 47}; 48 49&ddrc { 50 operating-points-v2 = <&ddrc_opp_table>; 51 52 ddrc_opp_table: opp-table { 53 compatible = "operating-points-v2"; 54 55 opp-25000000 { 56 opp-hz = /bits/ 64 <25000000>; 57 }; 58 59 opp-100000000 { 60 opp-hz = /bits/ 64 <100000000>; 61 }; 62 63 opp-750000000 { 64 opp-hz = /bits/ 64 <750000000>; 65 }; 66 }; 67}; 68 69/* Ethernet */ 70&fec1 { 71 phy-mode = "rgmii-id"; 72 phy-handle = <ðphy0>; 73 pinctrl-names = "default"; 74 pinctrl-0 = <&pinctrl_fec1>; 75 status = "okay"; 76 77 mdio { 78 #address-cells = <1>; 79 #size-cells = <0>; 80 81 ethphy0: ethernet-phy@0 { 82 compatible = "ethernet-phy-ieee802.3-c22"; 83 enet-phy-lane-no-swap; 84 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; 85 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 86 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 87 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 88 reg = <0>; 89 reset-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; 90 reset-assert-us = <1000>; 91 reset-deassert-us = <1000>; 92 }; 93 }; 94}; 95 96/* SPI Flash */ 97&flexspi { 98 pinctrl-names = "default"; 99 pinctrl-0 = <&pinctrl_flexspi0>; 100 status = "okay"; 101 102 som_flash: flash@0 { 103 #address-cells = <1>; 104 #size-cells = <1>; 105 compatible = "jedec,spi-nor"; 106 reg = <0>; 107 spi-max-frequency = <80000000>; 108 spi-rx-bus-width = <4>; 109 spi-tx-bus-width = <1>; 110 }; 111}; 112 113&gpio1 { 114 gpio-line-names = "", "", "WDOG_INT", "X_RTC_INT", 115 "", "", "", "RESET_ETHPHY", 116 "", "", "nENABLE_FLATLINK"; 117}; 118 119/* I2C1 */ 120&i2c1 { 121 clock-frequency = <400000>; 122 pinctrl-names = "default","gpio"; 123 pinctrl-0 = <&pinctrl_i2c1>; 124 pinctrl-1 = <&pinctrl_i2c1_gpio>; 125 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 126 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 127 status = "okay"; 128 129 pmic@8 { 130 compatible = "nxp,pf8121a"; 131 reg = <0x08>; 132 133 regulators { 134 reg_nvcc_sd1: ldo1 { 135 regulator-always-on; 136 regulator-boot-on; 137 regulator-max-microvolt = <3300000>; 138 regulator-min-microvolt = <3300000>; 139 regulator-name = "NVCC_SD1 (LDO1)"; 140 141 regulator-state-mem { 142 regulator-off-in-suspend; 143 }; 144 }; 145 146 reg_nvcc_sd2: ldo2 { 147 regulator-always-on; 148 regulator-boot-on; 149 regulator-max-microvolt = <3300000>; 150 regulator-min-microvolt = <1800000>; 151 regulator-name = "NVCC_SD2 (LDO2)"; 152 153 regulator-state-mem { 154 regulator-off-in-suspend; 155 }; 156 }; 157 158 reg_vcc_enet: ldo3 { 159 regulator-always-on; 160 regulator-boot-on; 161 regulator-max-microvolt = <2500000>; 162 regulator-min-microvolt = <2500000>; 163 regulator-name = "VCC_ENET_2V5 (LDO3)"; 164 165 regulator-state-mem { 166 regulator-on-in-suspend; 167 regulator-suspend-max-microvolt = <2500000>; 168 regulator-suspend-min-microvolt = <2500000>; 169 }; 170 }; 171 172 reg_vdda_1v8: ldo4 { 173 regulator-always-on; 174 regulator-boot-on; 175 regulator-max-microvolt = <1800000>; 176 regulator-min-microvolt = <1500000>; 177 regulator-name = "VDDA_1V8 (LDO4)"; 178 179 regulator-state-mem { 180 regulator-on-in-suspend; 181 regulator-suspend-min-microvolt = <1500000>; 182 regulator-suspend-max-microvolt = <1500000>; 183 }; 184 }; 185 186 reg_soc_vdda_phy: buck1 { 187 regulator-always-on; 188 regulator-boot-on; 189 regulator-max-microvolt = <900000>; 190 regulator-min-microvolt = <400000>; 191 regulator-name = "VDD_SOC_VDDA_PHY_0P8 (BUCK1)"; 192 193 regulator-state-mem { 194 regulator-on-in-suspend; 195 regulator-suspend-min-microvolt = <400000>; 196 regulator-suspend-max-microvolt = <400000>; 197 }; 198 }; 199 200 reg_vdd_gpu_dram: buck2 { 201 regulator-always-on; 202 regulator-boot-on; 203 regulator-max-microvolt = <1000000>; 204 regulator-min-microvolt = <1000000>; 205 regulator-name = "VDD_GPU_DRAM (BUCK2)"; 206 207 regulator-state-mem { 208 regulator-on-in-suspend; 209 regulator-suspend-max-microvolt = <1000000>; 210 regulator-suspend-min-microvolt = <1000000>; 211 }; 212 }; 213 214 reg_vdd_vpu: buck3 { 215 regulator-always-on; 216 regulator-boot-on; 217 regulator-max-microvolt = <1000000>; 218 regulator-min-microvolt = <400000>; 219 regulator-name = "VDD_VPU (BUCK3)"; 220 221 regulator-state-mem { 222 regulator-off-in-suspend; 223 }; 224 }; 225 226 reg_vdd_mipi: buck4 { 227 regulator-always-on; 228 regulator-boot-on; 229 regulator-max-microvolt = <1050000>; 230 regulator-min-microvolt = <900000>; 231 regulator-name = "VDD_MIPI_0P9 (BUCK4)"; 232 233 regulator-state-mem { 234 regulator-off-in-suspend; 235 }; 236 }; 237 238 reg_vdd_arm: buck5 { 239 regulator-always-on; 240 regulator-boot-on; 241 regulator-max-microvolt = <1050000>; 242 regulator-min-microvolt = <400000>; 243 regulator-name = "VDD_ARM (BUCK5)"; 244 245 regulator-state-mem { 246 regulator-off-in-suspend; 247 }; 248 }; 249 250 reg_vdd_1v8: buck6 { 251 regulator-always-on; 252 regulator-boot-on; 253 regulator-max-microvolt = <1800000>; 254 regulator-min-microvolt = <1800000>; 255 regulator-name = "VDD_1V8 (BUCK6)"; 256 257 regulator-state-mem { 258 regulator-on-in-suspend; 259 regulator-suspend-max-microvolt = <1800000>; 260 regulator-suspend-min-microvolt = <1800000>; 261 }; 262 }; 263 264 reg_nvcc_dram: buck7 { 265 regulator-always-on; 266 regulator-boot-on; 267 regulator-max-microvolt = <1100000>; 268 regulator-min-microvolt = <1100000>; 269 regulator-name = "NVCC_DRAM_1P1V (BUCK7)"; 270 }; 271 272 reg_vsnvs: vsnvs { 273 regulator-always-on; 274 regulator-boot-on; 275 regulator-max-microvolt = <1800000>; 276 regulator-min-microvolt = <1800000>; 277 regulator-name = "NVCC_SNVS_1P8 (VSNVS)"; 278 }; 279 }; 280 }; 281 282 sn65dsi83: bridge@2d { 283 compatible = "ti,sn65dsi83"; 284 enable-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; 285 pinctrl-names = "default"; 286 pinctrl-0 = <&pinctrl_sn65dsi83>; 287 reg = <0x2d>; 288 vcc-supply = <®_vdd_1v8>; 289 status = "disabled"; 290 ports { 291 #address-cells = <1>; 292 #size-cells = <0>; 293 294 port@0 { 295 reg = <0>; 296 bridge_in: endpoint { 297 remote-endpoint = <&mipi_dsi_out>; 298 data-lanes = <1 2 3 4>; 299 }; 300 }; 301 302 port@2 { 303 reg = <2>; 304 bridge_out: endpoint {}; 305 }; 306 }; 307 }; 308 309 /* EEPROM */ 310 eeprom@51 { 311 compatible = "atmel,24c32"; 312 pagesize = <32>; 313 reg = <0x51>; 314 vcc-supply = <®_vdd_3v3_s>; 315 }; 316 317 /* RTC */ 318 rv3028: rtc@52 { 319 compatible = "microcrystal,rv3028"; 320 reg = <0x52>; 321 }; 322}; 323 324&mipi_dsi { 325 samsung,esc-clock-frequency = <10000000>; 326}; 327 328&mipi_dsi_out { 329 remote-endpoint = <&bridge_in>; 330}; 331 332/* eMMC */ 333&usdhc3 { 334 assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>; 335 assigned-clock-rates = <400000000>; 336 bus-width = <8>; 337 keep-power-in-suspend; 338 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 339 pinctrl-0 = <&pinctrl_usdhc3>; 340 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 341 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 342 non-removable; 343 status = "okay"; 344}; 345 346/* Watchdog */ 347&wdog1 { 348 fsl,ext-reset-output; 349 pinctrl-names = "default"; 350 pinctrl-0 = <&pinctrl_wdog>; 351 status = "okay"; 352}; 353 354&iomuxc { 355 pinctrl_fec1: fec1grp { 356 fsl,pins = < 357 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x2 358 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x2 359 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x90 360 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x90 361 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x90 362 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x90 363 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x90 364 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x90 365 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x16 366 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x16 367 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x12 368 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x12 369 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x12 370 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x12 371 MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x10 372 >; 373 }; 374 375 pinctrl_flexspi0: flexspi0grp { 376 fsl,pins = < 377 MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 378 MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 379 MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 380 MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 381 MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 382 MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 383 >; 384 }; 385 386 pinctrl_i2c1: i2c1grp { 387 fsl,pins = < 388 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c0 389 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c0 390 >; 391 }; 392 393 pinctrl_i2c1_gpio: i2c1gpiogrp { 394 fsl,pins = < 395 MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x1e0 396 MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x1e0 397 >; 398 }; 399 400 pinctrl_sn65dsi83: sn65dsi83grp { 401 fsl,pins = < 402 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x0 403 >; 404 }; 405 406 pinctrl_usdhc3: usdhc3grp { 407 fsl,pins = < 408 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 409 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 410 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 411 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 412 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 413 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 414 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 415 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 416 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 417 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 418 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 419 >; 420 }; 421 422 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 423 fsl,pins = < 424 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 425 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 426 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 427 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 428 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 429 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 430 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 431 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 432 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 433 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 434 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 435 >; 436 }; 437 438 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 439 fsl,pins = < 440 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 441 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 442 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 443 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 444 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 445 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 446 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 447 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 448 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 449 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 450 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 451 >; 452 }; 453 454 pinctrl_wdog: wdoggrp { 455 fsl,pins = < 456 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x26 457 >; 458 }; 459};
~/
Read-only file preview.