imx8mm-kontron-bl-lte.dtso

  1// SPDX-License-Identifier: GPL-2.0+ OR MIT
  2/*
  3 * Copyright (C) 2025 Kontron Electronics GmbH
  4 */
  5
  6/dts-v1/;
  7/plugin/;
  8
  9#include <dt-bindings/gpio/gpio.h>
 10#include <dt-bindings/input/input.h>
 11#include <dt-bindings/interrupt-controller/irq.h>
 12#include <dt-bindings/leds/common.h>
 13#include "imx8mm-pinfunc.h"
 14
 15&{/} {
 16	compatible = "kontron,imx8mm-bl", "kontron,imx8mm-sl", "fsl,imx8mm";
 17
 18	gpio-keys {
 19		compatible = "gpio-keys";
 20		pinctrl-names = "default";
 21		pinctrl-0 = <&pinctrl_gpio_keys>;
 22
 23		key-user {
 24			label = "user";
 25			linux,code = <BTN_0>;
 26			gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
 27		};
 28	};
 29
 30	leds {
 31		compatible = "gpio-leds";
 32		pinctrl-names = "default";
 33		pinctrl-0 = <&pinctrl_gpio_led_lte>;
 34
 35		lte-led1-b {
 36			label = "lte-led1-blue";
 37			color = <LED_COLOR_ID_BLUE>;
 38			gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>;
 39		};
 40
 41		lte-led1-g {
 42			label = "lte-led1-green";
 43			color = <LED_COLOR_ID_GREEN>;
 44			gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
 45		};
 46
 47		lte-led1-r {
 48			label = "lte-led1-red";
 49			color = <LED_COLOR_ID_RED>;
 50			gpios = <&gpio5 23 GPIO_ACTIVE_HIGH>;
 51		};
 52
 53		lte-led2-b {
 54			label = "lte-led2-blue";
 55			color = <LED_COLOR_ID_BLUE>;
 56			gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>;
 57		};
 58
 59		lte-led2-g {
 60			label = "lte-led2-green";
 61			color = <LED_COLOR_ID_GREEN>;
 62			gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>;
 63		};
 64
 65		lte-led2-r {
 66			label = "lte-led2-red";
 67			color = <LED_COLOR_ID_RED>;
 68			gpios = <&gpio5 24 GPIO_ACTIVE_HIGH>;
 69		};
 70	};
 71};
 72
 73&ecspi3 {
 74	status = "disabled";
 75};
 76
 77&i2c2 {
 78	#address-cells = <1>;
 79	#size-cells = <0>;
 80	clock-frequency = <400000>;
 81	pinctrl-names = "default";
 82	pinctrl-0 = <&pinctrl_i2c2>;
 83	status = "okay";
 84
 85	tpm@2e {
 86		compatible = "infineon,slb9673", "tcg,tpm-tis-i2c";
 87		pinctrl-names = "default";
 88		pinctrl-0 = <&pinctrl_tpm>;
 89		reg = <0x2e>;
 90		interrupt-parent = <&gpio3>;
 91		interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
 92	};
 93};
 94
 95&gpio3 {
 96	pinctrl-names = "default";
 97	pinctrl-0 = <&pinctrl_gpio3>;
 98	gpio-line-names = "", "", "", "",
 99			  "", "", "", "",
100			  "", "", "VDD_IO_REF", "TPM_PIRQ#",
101			  "TPM_RESET# ", "", "", "",
102			  "", "LTE_LED1_B", "LTE_LED1_G", "",
103			  "";
104
105	vdd-io-ref-hog {
106		gpio-hog;
107		gpios = <10 GPIO_ACTIVE_HIGH>;
108		line-name = "VDD_IO_REF";
109		output-high;
110	};
111
112	tpm-reset-hog {
113		gpio-hog;
114		gpios = <12 GPIO_ACTIVE_LOW>;
115		line-name = "TPM_RESET#";
116		output-low;
117	};
118};
119
120&gpio4 {
121	pinctrl-names = "default";
122	pinctrl-0 = <&pinctrl_gpio4>;
123	gpio-line-names = "", "", "LTE_RESET", "",
124			  "", "", "", "",
125			  "", "", "", "LTE_PWRKEY",
126			  "", "", "", "",
127			  "", "", "", "",
128			  "LTE_PWR_EN";
129};
130
131&gpio5 {
132	gpio-line-names = "", "", "", "",
133			  "", "", "", "",
134			  "", "", "", "",
135			  "", "", "", "",
136			  "", "", "", "",
137			  "", "", "LTE_LED2_G", "LTE_LED1_R",
138			  "LTE_LED2_R", "LTE_LED2_B";
139};
140
141&iomuxc {
142	pinctrl_gpio3: gpio3grp {
143		fsl,pins = <
144			MX8MM_IOMUXC_NAND_DATA04_GPIO3_IO10		0x19 /* VDD_IO_REF */
145		>;
146	};
147
148	pinctrl_gpio4: gpio4grp {
149		fsl,pins = <
150			MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2		0x19 /* LTE_RESET */
151			MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 		0x19 /* LTE_PWRKEY */
152			MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20		0x19 /* LTE_PWR_EN */
153		>;
154	};
155
156	pinctrl_gpio_keys: gpiokeysgrp {
157		fsl,pins = <
158			MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12		0x19 /* Pushbutton */
159		>;
160	};
161
162	pinctrl_gpio_led_lte: gpioledltegrp {
163		fsl,pins = <
164			MX8MM_IOMUXC_NAND_WE_B_GPIO3_IO17		0x19 /* LTE_LED1_B */
165			MX8MM_IOMUXC_NAND_WP_B_GPIO3_IO18		0x19 /* LTE_LED1_G */
166			MX8MM_IOMUXC_UART1_TXD_GPIO5_IO23		0x19 /* LTE_LED1_R */
167			MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25		0x19 /* LTE_LED2_B */
168			MX8MM_IOMUXC_UART1_RXD_GPIO5_IO22		0x19 /* LTE_LED2_G */
169			MX8MM_IOMUXC_UART2_RXD_GPIO5_IO24		0x19 /* LTE_LED2_R */
170		>;
171	};
172
173	pinctrl_i2c2: i2c2grp {
174		fsl,pins = <
175			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL			0x40000083 /* I2C_A_SCL */
176			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA			0x40000083 /* I2C_A_SDA */
177		>;
178	};
179
180	pinctrl_tpm: tpmgrp {
181		fsl,pins = <
182			MX8MM_IOMUXC_NAND_DATA05_GPIO3_IO11		0x19 /* TPM_PIRQ# */
183			MX8MM_IOMUXC_NAND_DATA06_GPIO3_IO12		0x39 /* TPM_RESET# */
184		>;
185	};
186};