imx8mm-evk.dtsi

  1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2/*
  3 * Copyright 2020 NXP
  4 */
  5
  6/dts-v1/;
  7
  8#include <dt-bindings/phy/phy-imx8-pcie.h>
  9#include <dt-bindings/usb/pd.h>
 10#include "imx8mm.dtsi"
 11
 12/ {
 13	chosen {
 14		stdout-path = &uart2;
 15	};
 16
 17	memory@40000000 {
 18		device_type = "memory";
 19		reg = <0x0 0x40000000 0 0x80000000>;
 20	};
 21
 22	hdmi-connector {
 23		compatible = "hdmi-connector";
 24		label = "hdmi";
 25		type = "a";
 26
 27		port {
 28			hdmi_connector_in: endpoint {
 29				remote-endpoint = <&adv7535_out>;
 30			};
 31		};
 32	};
 33
 34	leds {
 35		compatible = "gpio-leds";
 36		pinctrl-names = "default";
 37		pinctrl-0 = <&pinctrl_gpio_led>;
 38
 39		status {
 40			label = "status";
 41			gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
 42			default-state = "on";
 43		};
 44	};
 45
 46	pcie0_refclk: pcie0-refclk {
 47		compatible = "fixed-clock";
 48		#clock-cells = <0>;
 49		clock-frequency = <100000000>;
 50	};
 51
 52	reg_pcie0: regulator-pcie {
 53		compatible = "regulator-fixed";
 54		pinctrl-names = "default";
 55		pinctrl-0 = <&pinctrl_pcie0_reg>;
 56		regulator-name = "MPCIE_3V3";
 57		regulator-min-microvolt = <3300000>;
 58		regulator-max-microvolt = <3300000>;
 59		gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
 60		enable-active-high;
 61	};
 62
 63	reg_usdhc2_vmmc: regulator-usdhc2 {
 64		compatible = "regulator-fixed";
 65		pinctrl-names = "default";
 66		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
 67		regulator-name = "VSD_3V3";
 68		regulator-min-microvolt = <3300000>;
 69		regulator-max-microvolt = <3300000>;
 70		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
 71		off-on-delay-us = <20000>;
 72		enable-active-high;
 73	};
 74
 75	reg_1v5: regulator-1v5 {
 76		compatible = "regulator-fixed";
 77		regulator-name = "VDD_1V5";
 78		regulator-min-microvolt = <1500000>;
 79		regulator-max-microvolt = <1500000>;
 80	};
 81
 82	reg_1v8: regulator-1v8 {
 83		compatible = "regulator-fixed";
 84		regulator-name = "VDD_1V8";
 85		regulator-min-microvolt = <1800000>;
 86		regulator-max-microvolt = <1800000>;
 87	};
 88
 89	reg_vddext_3v3: regulator-vddext-3v3 {
 90		compatible = "regulator-fixed";
 91		regulator-name = "VDDEXT_3V3";
 92		regulator-min-microvolt = <3300000>;
 93		regulator-max-microvolt = <3300000>;
 94	};
 95
 96	backlight: backlight {
 97		compatible = "pwm-backlight";
 98		pwms = <&pwm1 0 5000000 0>;
 99		brightness-levels = <0 255>;
100		num-interpolated-steps = <255>;
101		default-brightness-level = <250>;
102	};
103
104	ir-receiver {
105		compatible = "gpio-ir-receiver";
106		gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
107		pinctrl-names = "default";
108		pinctrl-0 = <&pinctrl_ir>;
109		linux,autosuspend-period = <125>;
110	};
111
112	audio_codec_bt_sco: audio-codec-bt-sco {
113		compatible = "linux,bt-sco";
114		#sound-dai-cells = <1>;
115	};
116
117	wm8524: audio-codec {
118		#sound-dai-cells = <0>;
119		compatible = "wlf,wm8524";
120		pinctrl-names = "default";
121		pinctrl-0 = <&pinctrl_gpio_wlf>;
122		wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
123	};
124
125	sound-bt-sco {
126		compatible = "simple-audio-card";
127		simple-audio-card,name = "bt-sco-audio";
128		simple-audio-card,format = "dsp_a";
129		simple-audio-card,bitclock-inversion;
130		simple-audio-card,frame-master = <&btcpu>;
131		simple-audio-card,bitclock-master = <&btcpu>;
132
133		btcpu: simple-audio-card,cpu {
134			sound-dai = <&sai2>;
135			dai-tdm-slot-num = <2>;
136			dai-tdm-slot-width = <16>;
137		};
138
139		simple-audio-card,codec {
140			sound-dai = <&audio_codec_bt_sco 1>;
141		};
142	};
143
144	sound-wm8524 {
145		compatible = "simple-audio-card";
146		simple-audio-card,name = "wm8524-audio";
147		simple-audio-card,format = "i2s";
148		simple-audio-card,frame-master = <&cpudai>;
149		simple-audio-card,bitclock-master = <&cpudai>;
150		simple-audio-card,mclk-fs = <256>;
151		simple-audio-card,widgets =
152			"Line", "Left Line Out Jack",
153			"Line", "Right Line Out Jack";
154		simple-audio-card,routing =
155			"Left Line Out Jack", "LINEVOUTL",
156			"Right Line Out Jack", "LINEVOUTR";
157
158		cpudai: simple-audio-card,cpu {
159			sound-dai = <&sai3>;
160			dai-tdm-slot-num = <2>;
161			dai-tdm-slot-width = <32>;
162			system-clock-direction-out;
163		};
164
165		simple-audio-card,codec {
166			sound-dai = <&wm8524>;
167		};
168	};
169
170	sound-micfil {
171		compatible = "fsl,imx-audio-card";
172		model = "micfil-audio";
173
174		pri-dai-link {
175			link-name = "micfil hifi";
176			format = "i2s";
177
178			cpu {
179				sound-dai = <&micfil>;
180			};
181		};
182	};
183
184	spdif_out: spdif-out {
185		compatible = "linux,spdif-dit";
186		#sound-dai-cells = <0>;
187	};
188
189	spdif_in: spdif-in {
190		compatible = "linux,spdif-dir";
191		#sound-dai-cells = <0>;
192	};
193
194	sound-spdif {
195		compatible = "fsl,imx-audio-spdif";
196		model = "imx-spdif";
197		audio-cpu = <&spdif1>;
198		audio-codec = <&spdif_out>, <&spdif_in>;
199	};
200};
201
202&A53_0 {
203	cpu-supply = <&buck2_reg>;
204};
205
206&A53_1 {
207	cpu-supply = <&buck2_reg>;
208};
209
210&A53_2 {
211	cpu-supply = <&buck2_reg>;
212};
213
214&A53_3 {
215	cpu-supply = <&buck2_reg>;
216};
217
218&fec1 {
219	pinctrl-names = "default";
220	pinctrl-0 = <&pinctrl_fec1>;
221	phy-mode = "rgmii-id";
222	phy-handle = <&ethphy0>;
223	fsl,magic-packet;
224	status = "okay";
225
226	mdio {
227		#address-cells = <1>;
228		#size-cells = <0>;
229
230		ethphy0: ethernet-phy@0 {
231			compatible = "ethernet-phy-ieee802.3-c22";
232			reg = <0>;
233			reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
234			reset-assert-us = <10000>;
235			qca,disable-smarteee;
236			vddio-supply = <&vddio>;
237
238			vddio: vddio-regulator {
239				regulator-min-microvolt = <1800000>;
240				regulator-max-microvolt = <1800000>;
241			};
242		};
243	};
244};
245
246&i2c1 {
247	clock-frequency = <400000>;
248	pinctrl-names = "default";
249	pinctrl-0 = <&pinctrl_i2c1>;
250	status = "okay";
251
252	pmic@4b {
253		compatible = "rohm,bd71847";
254		reg = <0x4b>;
255		pinctrl-names = "default";
256		pinctrl-0 = <&pinctrl_pmic>;
257		interrupt-parent = <&gpio1>;
258		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
259		rohm,reset-snvs-powered;
260
261		#clock-cells = <0>;
262		clocks = <&osc_32k>;
263		clock-output-names = "clk-32k-out";
264
265		regulators {
266			buck1_reg: BUCK1 {
267				regulator-name = "buck1";
268				regulator-min-microvolt = <700000>;
269				regulator-max-microvolt = <1300000>;
270				regulator-boot-on;
271				regulator-always-on;
272				regulator-ramp-delay = <1250>;
273			};
274
275			buck2_reg: BUCK2 {
276				regulator-name = "buck2";
277				regulator-min-microvolt = <700000>;
278				regulator-max-microvolt = <1300000>;
279				regulator-boot-on;
280				regulator-always-on;
281				regulator-ramp-delay = <1250>;
282				rohm,dvs-run-voltage = <1000000>;
283				rohm,dvs-idle-voltage = <900000>;
284			};
285
286			buck3_reg: BUCK3 {
287				// BUCK5 in datasheet
288				regulator-name = "buck3";
289				regulator-min-microvolt = <700000>;
290				regulator-max-microvolt = <1350000>;
291				regulator-boot-on;
292				regulator-always-on;
293			};
294
295			buck4_reg: BUCK4 {
296				// BUCK6 in datasheet
297				regulator-name = "buck4";
298				regulator-min-microvolt = <3000000>;
299				regulator-max-microvolt = <3300000>;
300				regulator-boot-on;
301				regulator-always-on;
302			};
303
304			buck5_reg: BUCK5 {
305				// BUCK7 in datasheet
306				regulator-name = "buck5";
307				regulator-min-microvolt = <1605000>;
308				regulator-max-microvolt = <1995000>;
309				regulator-boot-on;
310				regulator-always-on;
311			};
312
313			buck6_reg: BUCK6 {
314				// BUCK8 in datasheet
315				regulator-name = "buck6";
316				regulator-min-microvolt = <800000>;
317				regulator-max-microvolt = <1400000>;
318				regulator-boot-on;
319				regulator-always-on;
320			};
321
322			ldo1_reg: LDO1 {
323				regulator-name = "ldo1";
324				regulator-min-microvolt = <1600000>;
325				regulator-max-microvolt = <3300000>;
326				regulator-boot-on;
327				regulator-always-on;
328			};
329
330			ldo2_reg: LDO2 {
331				regulator-name = "ldo2";
332				regulator-min-microvolt = <800000>;
333				regulator-max-microvolt = <900000>;
334				regulator-boot-on;
335				regulator-always-on;
336			};
337
338			ldo3_reg: LDO3 {
339				regulator-name = "ldo3";
340				regulator-min-microvolt = <1800000>;
341				regulator-max-microvolt = <3300000>;
342				regulator-boot-on;
343				regulator-always-on;
344			};
345
346			ldo4_reg: LDO4 {
347				regulator-name = "ldo4";
348				regulator-min-microvolt = <900000>;
349				regulator-max-microvolt = <1800000>;
350				regulator-boot-on;
351				regulator-always-on;
352			};
353
354			ldo6_reg: LDO6 {
355				regulator-name = "ldo6";
356				regulator-min-microvolt = <900000>;
357				regulator-max-microvolt = <1800000>;
358				regulator-boot-on;
359				regulator-always-on;
360			};
361		};
362	};
363};
364
365&i2c2 {
366	clock-frequency = <400000>;
367	pinctrl-names = "default";
368	pinctrl-0 = <&pinctrl_i2c2>;
369	status = "okay";
370
371	hdmi@3d {
372		compatible = "adi,adv7535";
373		reg = <0x3d>;
374		interrupt-parent = <&gpio1>;
375		interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
376		adi,dsi-lanes = <4>;
377		avdd-supply = <&buck5_reg>;
378		dvdd-supply = <&buck5_reg>;
379		pvdd-supply = <&buck5_reg>;
380		a2vdd-supply = <&buck5_reg>;
381		v3p3-supply = <&reg_vddext_3v3>;
382		v1p2-supply = <&buck5_reg>;
383
384		ports {
385			#address-cells = <1>;
386			#size-cells = <0>;
387
388			port@0 {
389				reg = <0>;
390
391				adv7535_in: endpoint {
392					remote-endpoint = <&dsi_out>;
393				};
394			};
395
396			port@1 {
397				reg = <1>;
398
399				adv7535_out: endpoint {
400					remote-endpoint = <&hdmi_connector_in>;
401				};
402			};
403
404		};
405	};
406
407	ptn5110: tcpc@50 {
408		compatible = "nxp,ptn5110", "tcpci";
409		pinctrl-names = "default";
410		pinctrl-0 = <&pinctrl_typec1>;
411		reg = <0x50>;
412		interrupt-parent = <&gpio2>;
413		interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
414		status = "okay";
415
416		typec1_con: connector {
417			compatible = "usb-c-connector";
418			label = "USB-C";
419			power-role = "dual";
420			data-role = "dual";
421			try-power-role = "sink";
422			source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
423			sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
424				     PDO_VAR(5000, 20000, 3000)>;
425			op-sink-microwatt = <15000000>;
426			self-powered;
427
428			port {
429				typec1_dr_sw: endpoint {
430					remote-endpoint = <&usb1_drd_sw>;
431				};
432			};
433		};
434	};
435};
436
437
438&csi {
439	status = "okay";
440};
441
442&i2c3 {
443	clock-frequency = <400000>;
444	pinctrl-names = "default";
445	pinctrl-0 = <&pinctrl_i2c3>;
446	status = "okay";
447
448	pca6416: gpio@20 {
449		compatible = "nxp,pca6416";
450		reg = <0x20>;
451		gpio-controller;
452		#gpio-cells = <2>;
453		vcc-supply = <&buck4_reg>;
454	};
455
456	camera@3c {
457		compatible = "ovti,ov5640";
458		reg = <0x3c>;
459		pinctrl-names = "default";
460		pinctrl-0 = <&pinctrl_camera>;
461		clocks = <&clk IMX8MM_CLK_CLKO1>;
462		clock-names = "xclk";
463		assigned-clocks = <&clk IMX8MM_CLK_CLKO1>;
464		assigned-clock-parents = <&clk IMX8MM_CLK_24M>;
465		assigned-clock-rates = <24000000>;
466		powerdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
467		reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
468		DOVDD-supply = <&buck5_reg>;
469		AVDD-supply = <&reg_1v8>;
470		DVDD-supply = <&reg_1v5>;
471
472		port {
473			ov5640_to_mipi_csi2: endpoint {
474				remote-endpoint = <&imx8mm_mipi_csi_in>;
475				clock-lanes = <0>;
476				data-lanes = <1 2>;
477			};
478		};
479	};
480};
481
482&lcdif {
483	status = "okay";
484};
485
486&micfil {
487	#sound-dai-cells = <0>;
488	pinctrl-names = "default";
489	pinctrl-0 = <&pinctrl_pdm>;
490	assigned-clocks = <&clk IMX8MM_CLK_PDM>;
491	assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
492	assigned-clock-rates = <196608000>;
493	status = "okay";
494};
495
496&mipi_csi {
497	status = "okay";
498
499	ports {
500		port@0 {
501			imx8mm_mipi_csi_in: endpoint {
502				remote-endpoint = <&ov5640_to_mipi_csi2>;
503				data-lanes = <1 2>;
504			};
505		};
506	};
507};
508
509&mipi_dsi {
510	samsung,esc-clock-frequency = <10000000>;
511	status = "okay";
512
513	ports {
514		port@1 {
515			reg = <1>;
516
517			dsi_out: endpoint {
518				remote-endpoint = <&adv7535_in>;
519				data-lanes = <1 2 3 4>;
520			};
521		};
522	};
523};
524
525&pcie_phy {
526	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
527	fsl,tx-deemph-gen1 = <0x2d>;
528	fsl,tx-deemph-gen2 = <0xf>;
529	clocks = <&pcie0_refclk>;
530	status = "okay";
531};
532
533&pcie0 {
534	pinctrl-names = "default";
535	pinctrl-0 = <&pinctrl_pcie0>;
536	reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
537	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
538		 <&clk IMX8MM_CLK_PCIE1_AUX>;
539	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
540			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
541	assigned-clock-rates = <10000000>, <250000000>;
542	assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
543				 <&clk IMX8MM_SYS_PLL2_250M>;
544	vpcie-supply = <&reg_pcie0>;
545	supports-clkreq;
546	status = "okay";
547};
548
549&pcie0_ep {
550	pinctrl-names = "default";
551	pinctrl-0 = <&pinctrl_pcie0>;
552	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
553		 <&clk IMX8MM_CLK_PCIE1_AUX>;
554	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
555			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
556	assigned-clock-rates = <10000000>, <250000000>;
557	assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
558				 <&clk IMX8MM_SYS_PLL2_250M>;
559	status = "disabled";
560};
561
562&sai2 {
563	#sound-dai-cells = <0>;
564	pinctrl-names = "default";
565	pinctrl-0 = <&pinctrl_sai2>;
566	assigned-clocks = <&clk IMX8MM_CLK_SAI2>;
567	assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
568	assigned-clock-rates = <24576000>;
569	status = "okay";
570};
571
572&sai3 {
573	pinctrl-names = "default";
574	pinctrl-0 = <&pinctrl_sai3>;
575	assigned-clocks = <&clk IMX8MM_AUDIO_PLL1>,
576			  <&clk IMX8MM_AUDIO_PLL2>,
577			  <&clk IMX8MM_CLK_SAI3>;
578	assigned-clock-parents = <0>, <0>, <&clk IMX8MM_AUDIO_PLL1_OUT>;
579	assigned-clock-rates = <393216000>, <361267200>, <24576000>;
580	fsl,sai-mclk-direction-output;
581	clocks = <&clk IMX8MM_CLK_SAI3_IPG>, <&clk IMX8MM_CLK_DUMMY>,
582		<&clk IMX8MM_CLK_SAI3_ROOT>, <&clk IMX8MM_CLK_DUMMY>,
583		<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>,
584		<&clk IMX8MM_AUDIO_PLL2_OUT>;
585	clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";
586	status = "okay";
587};
588
589&snvs_pwrkey {
590	status = "okay";
591};
592
593&spdif1 {
594	pinctrl-names = "default";
595	pinctrl-0 = <&pinctrl_spdif1>;
596	assigned-clocks = <&clk IMX8MM_CLK_SPDIF1>;
597	assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
598	assigned-clock-rates = <24576000>;
599	clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_24M>,
600		 <&clk IMX8MM_CLK_SPDIF1>, <&clk IMX8MM_CLK_DUMMY>,
601		 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>,
602		 <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_DUMMY>,
603		 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>,
604		 <&clk IMX8MM_AUDIO_PLL1_OUT>, <&clk IMX8MM_AUDIO_PLL2_OUT>;
605	clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3",
606		      "rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba",
607		      "pll8k", "pll11k";
608	status = "okay";
609};
610
611&uart2 { /* console */
612	pinctrl-names = "default";
613	pinctrl-0 = <&pinctrl_uart2>;
614	status = "okay";
615};
616
617&usbphynop1 {
618	wakeup-source;
619};
620
621&usbotg1 {
622	dr_mode = "otg";
623	hnp-disable;
624	srp-disable;
625	adp-disable;
626	usb-role-switch;
627	disable-over-current;
628	samsung,picophy-pre-emp-curr-control = <3>;
629	samsung,picophy-dc-vol-level-adjust = <7>;
630	status = "okay";
631
632	port {
633		usb1_drd_sw: endpoint {
634			remote-endpoint = <&typec1_dr_sw>;
635		};
636	};
637};
638
639&usdhc2 {
640	assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
641	assigned-clock-rates = <200000000>;
642	pinctrl-names = "default", "state_100mhz", "state_200mhz";
643	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
644	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
645	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
646	cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
647	bus-width = <4>;
648	vmmc-supply = <&reg_usdhc2_vmmc>;
649	status = "okay";
650};
651
652&wdog1 {
653	pinctrl-names = "default";
654	pinctrl-0 = <&pinctrl_wdog>;
655	fsl,ext-reset-output;
656	status = "okay";
657};
658
659&pwm1 {
660	pinctrl-names = "default";
661	pinctrl-0 = <&pinctrl_backlight>;
662	status = "okay";
663};
664
665&iomuxc {
666	pinctrl_fec1: fec1grp {
667		fsl,pins = <
668			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3
669			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
670			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
671			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
672			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
673			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
674			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
675			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
676			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
677			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
678			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
679			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
680			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
681			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
682			MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22		0x19
683		>;
684	};
685
686	pinctrl_gpio_led: gpioledgrp {
687		fsl,pins = <
688			MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16	0x19
689		>;
690	};
691
692	pinctrl_ir: irgrp {
693		fsl,pins = <
694			MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13              0x4f
695		>;
696	};
697
698	pinctrl_gpio_wlf: gpiowlfgrp {
699		fsl,pins = <
700			MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21	0xd6
701		>;
702	};
703
704	pinctrl_i2c1: i2c1grp {
705		fsl,pins = <
706			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL			0x400001c3
707			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA			0x400001c3
708		>;
709	};
710
711	pinctrl_i2c2: i2c2grp {
712		fsl,pins = <
713			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL			0x400001c3
714			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA			0x400001c3
715		>;
716	};
717
718	pinctrl_i2c3: i2c3grp {
719		fsl,pins = <
720			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL			0x400001c3
721			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA			0x400001c3
722		>;
723	};
724
725	pinctrl_pcie0: pcie0grp {
726		fsl,pins = <
727			MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B    0x61
728			MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21       0x41
729		>;
730	};
731
732	pinctrl_pcie0_reg: pcie0reggrp {
733		fsl,pins = <
734			MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5       0x41
735		>;
736	};
737
738	pinctrl_pdm: pdmgrp {
739		fsl,pins = <
740			MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK        0xd6
741			MX8MM_IOMUXC_SAI5_RXC_PDM_CLK           0xd6
742			MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC     0xd6
743			MX8MM_IOMUXC_SAI5_RXD0_PDM_DATA0        0xd6
744			MX8MM_IOMUXC_SAI5_RXD1_PDM_DATA1        0xd6
745			MX8MM_IOMUXC_SAI5_RXD2_PDM_DATA2        0xd6
746			MX8MM_IOMUXC_SAI5_RXD3_PDM_DATA3        0xd6
747		>;
748	};
749
750	pinctrl_pmic: pmicirqgrp {
751		fsl,pins = <
752			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x141
753		>;
754	};
755
756	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
757		fsl,pins = <
758			MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
759		>;
760	};
761
762	pinctrl_sai2: sai2grp {
763		fsl,pins = <
764			MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK      0xd6
765			MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC     0xd6
766			MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0    0xd6
767			MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0    0xd6
768		>;
769	};
770
771	pinctrl_sai3: sai3grp {
772		fsl,pins = <
773			MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC     0xd6
774			MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK      0xd6
775			MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK        0xd6
776			MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0     0xd6
777		>;
778	};
779
780	pinctrl_spdif1: spdif1grp {
781		fsl,pins = <
782			MX8MM_IOMUXC_SPDIF_TX_SPDIF1_OUT	0xd6
783			MX8MM_IOMUXC_SPDIF_RX_SPDIF1_IN		0xd6
784		>;
785	};
786
787	pinctrl_typec1: typec1grp {
788		fsl,pins = <
789			MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11	0x159
790		>;
791	};
792
793	pinctrl_uart2: uart2grp {
794		fsl,pins = <
795			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140
796			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140
797		>;
798	};
799
800	pinctrl_usdhc2_gpio: usdhc2grpgpiogrp {
801		fsl,pins = <
802			MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15	0x1c4
803		>;
804	};
805
806	pinctrl_usdhc2: usdhc2grp {
807		fsl,pins = <
808			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x190
809			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0
810			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
811			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
812			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
813			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
814			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
815		>;
816	};
817
818	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
819		fsl,pins = <
820			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x194
821			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4
822			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4
823			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4
824			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4
825			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4
826			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
827		>;
828	};
829
830	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
831		fsl,pins = <
832			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x196
833			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6
834			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6
835			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6
836			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6
837			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6
838			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
839		>;
840	};
841
842	pinctrl_wdog: wdoggrp {
843		fsl,pins = <
844			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0x166
845		>;
846	};
847
848	pinctrl_backlight: backlightgrp {
849		fsl,pins = <
850			MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT	0x06
851		>;
852	};
853
854	pinctrl_camera: cameragrp {
855		fsl,pins = <
856			MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6		0x19
857			MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7		0x19
858			MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1	0x59
859		>;
860	};
861};