imx8dxl-ss-conn.dtsi

  1// SPDX-License-Identifier: GPL-2.0+
  2/*
  3 * Copyright 2019~2020, 2022 NXP
  4 */
  5
  6/delete-node/ &enet1_lpcg;
  7/delete-node/ &fec2;
  8/delete-node/ &usbotg3;
  9/delete-node/ &usb3_phy;
 10/delete-node/ &usb3_lpcg;
 11
 12/ {
 13	conn_enet0_root_clk: clock-conn-enet0-root {
 14		compatible = "fixed-clock";
 15		#clock-cells = <0>;
 16		clock-frequency = <250000000>;
 17		clock-output-names = "conn_enet0_root_clk";
 18	};
 19
 20	clk_dummy: clock-dummy {
 21		compatible = "fixed-clock";
 22		#clock-cells = <0>;
 23		clock-frequency = <0>;
 24		clock-output-names = "clk_dummy";
 25	};
 26};
 27
 28&conn_subsys {
 29	eqos: ethernet@5b050000 {
 30		compatible = "nxp,imx8dxl-dwmac-eqos", "snps,dwmac-5.10a";
 31		reg = <0x5b050000 0x10000>;
 32		interrupt-parent = <&gic>;
 33		interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
 34			     <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
 35		interrupt-names = "macirq", "eth_wake_irq";
 36		clocks = <&eqos_lpcg IMX_LPCG_CLK_4>,
 37			 <&eqos_lpcg IMX_LPCG_CLK_6>,
 38			 <&eqos_lpcg IMX_LPCG_CLK_0>,
 39			 <&eqos_lpcg IMX_LPCG_CLK_5>,
 40			 <&eqos_lpcg IMX_LPCG_CLK_2>;
 41		clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem";
 42		assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>;
 43		assigned-clock-rates = <125000000>;
 44		power-domains = <&pd IMX_SC_R_ENET_1>;
 45		status = "disabled";
 46	};
 47
 48	usbotg2: usb@5b0e0000 {
 49		compatible = "fsl,imx8dxl-usb", "fsl,imx7ulp-usb", "fsl,imx6ul-usb";
 50		reg = <0x5b0e0000 0x200>;
 51		interrupt-parent = <&gic>;
 52		interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
 53		fsl,usbphy = <&usbphy2>;
 54		fsl,usbmisc = <&usbmisc2 0>;
 55		/*
 56		 * usbotg1 and usbotg2 share one clcok.
 57		 * scu firmware disables the access to the clock and keeps
 58		 * it always on in case other core (M4) uses one of these.
 59		 */
 60		clocks = <&clk_dummy>;
 61		ahb-burst-config = <0x0>;
 62		tx-burst-size-dword = <0x10>;
 63		rx-burst-size-dword = <0x10>;
 64		power-domains = <&pd IMX_SC_R_USB_1>;
 65		status = "disabled";
 66	};
 67
 68	usbmisc2: usbmisc@5b0e0200 {
 69		#index-cells = <1>;
 70		compatible = "fsl,imx7ulp-usbmisc", "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
 71		reg = <0x5b0e0200 0x200>;
 72	};
 73
 74	usbphy2: usbphy@5b110000 {
 75		compatible = "fsl,imx8dxl-usbphy", "fsl,imx7ulp-usbphy";
 76		reg = <0x5b110000 0x1000>;
 77		clocks = <&usb2_2_lpcg IMX_LPCG_CLK_7>;
 78		power-domains = <&pd IMX_SC_R_USB_1_PHY>;
 79		status = "disabled";
 80	};
 81
 82	eqos_lpcg: clock-controller@5b240000 {
 83		compatible = "fsl,imx8qxp-lpcg";
 84		reg = <0x5b240000 0x10000>;
 85		#clock-cells = <1>;
 86		clocks = <&conn_enet0_root_clk>,
 87			 <&conn_axi_clk>,
 88			 <&conn_axi_clk>,
 89			 <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
 90			 <&conn_ipg_clk>;
 91		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_2>,
 92				<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
 93				<IMX_LPCG_CLK_6>;
 94		clock-output-names = "eqos_ptp",
 95				     "eqos_mem_clk",
 96				     "eqos_aclk",
 97				     "eqos_clk",
 98				     "eqos_csr_clk";
 99		power-domains = <&pd IMX_SC_R_ENET_1>;
100	};
101
102	usb2_2_lpcg: clock-controller@5b280000 {
103		compatible = "fsl,imx8qxp-lpcg";
104		reg = <0x5b280000 0x10000>;
105		#clock-cells = <1>;
106		clock-indices = <IMX_LPCG_CLK_7>;
107		clocks = <&conn_ipg_clk>;
108		clock-output-names = "usboh3_2_phy_ipg_clk";
109		power-domains = <&pd IMX_SC_R_USB_1_PHY>;
110	};
111
112};
113
114&dma_apbh {
115	interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
116		     <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
117		     <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
118		     <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
119};
120
121&enet0_lpcg {
122	clocks = <&conn_enet0_root_clk>,
123		 <&conn_enet0_root_clk>,
124		 <&conn_axi_clk>,
125		 <&clk IMX_SC_R_ENET_0 IMX_SC_C_TXCLK>,
126		 <&conn_ipg_clk>,
127		 <&conn_ipg_clk>;
128};
129
130&fec1 {
131	compatible = "fsl,imx8dxl-fec", "fsl,imx8qm-fec", "fsl,imx6sx-fec";
132	interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
133		     <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
134		     <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
135		     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
136	assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>;
137	assigned-clock-rates = <125000000>;
138};
139
140&gpmi {
141	interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
142};
143
144&usbphy1 {
145	compatible = "fsl,imx8dxl-usbphy", "fsl,imx7ulp-usbphy";
146};
147
148&usdhc1 {
149	compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc";
150	interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
151};
152
153&usdhc2 {
154	compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc";
155	interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
156};
157
158&usdhc3 {
159	compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc";
160	interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
161};
162
163&usbotg1 {
164	interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
165	/*
166	 * usbotg1 and usbotg2 share one clock
167	 * scfw disable clock access and keep it always on
168	 * in case other core (M4) use one of these.
169	 */
170	clocks = <&clk_dummy>;
171};