imx8-ss-mipi1.dtsi

  1// SPDX-License-Identifier: GPL-2.0-only and MIT
  2
  3/*
  4 * Copyright 2024 NXP
  5 */
  6
  7mipi1_subsys: bus@57220000 {
  8	compatible = "simple-bus";
  9	interrupt-parent = <&irqsteer_mipi1>;
 10	#address-cells = <1>;
 11	#size-cells = <1>;
 12	ranges = <0x57220000 0x0 0x57220000 0x10000>;
 13
 14	irqsteer_mipi1: interrupt-controller@57220000 {
 15		compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer";
 16		reg = <0x57220000 0x1000>;
 17		interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 18		interrupt-controller;
 19		interrupt-parent = <&gic>;
 20		#interrupt-cells = <1>;
 21		clocks = <&mipi1_lis_lpcg IMX_LPCG_CLK_0>;
 22		clock-names = "ipg";
 23		power-domains = <&pd IMX_SC_R_MIPI_1>;
 24		fsl,channel = <0>;
 25		fsl,num-irqs = <32>;
 26	};
 27
 28	mipi1_lis_lpcg: clock-controller@57223000 {
 29		compatible = "fsl,imx8qxp-lpcg";
 30		reg = <0x57223000 0x4>;
 31		#clock-cells = <1>;
 32		clocks = <&dsi_ipg_clk>;
 33		clock-indices = <IMX_LPCG_CLK_0>;
 34		clock-output-names = "mipi1_lis_lpcg_ipg_clk";
 35		power-domains = <&pd IMX_SC_R_MIPI_1>;
 36	};
 37
 38	mipi1_pwm_lpcg: clock-controller@5722300c {
 39		compatible = "fsl,imx8qxp-lpcg";
 40		reg = <0x5722300c 0x4>;
 41		#clock-cells = <1>;
 42		clocks = <&clk IMX_SC_R_MIPI_1_PWM_0 IMX_SC_PM_CLK_PER>,
 43			 <&dsi_ipg_clk>;
 44		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
 45		clock-output-names = "mipi1_pwm_lpcg_clk",
 46				     "mipi1_pwm_lpcg_ipg_clk";
 47		power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>;
 48	};
 49
 50	mipi1_i2c0_lpcg_clk: clock-controller@5722301c {
 51		compatible = "fsl,imx8qxp-lpcg";
 52		reg = <0x5722301c 0x4>;
 53		#clock-cells = <1>;
 54		clocks = <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_MISC2>;
 55		clock-indices = <IMX_LPCG_CLK_0>;
 56		clock-output-names = "mipi1_i2c0_lpcg_clk";
 57		power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
 58	};
 59
 60	mipi1_i2c0_lpcg_ipg_clk: clock-controller@57223014 {
 61		compatible = "fsl,imx8qxp-lpcg";
 62		reg = <0x57223014 0x4>;
 63		#clock-cells = <1>;
 64		clocks = <&mipi1_i2c0_lpcg_ipg_s_clk IMX_LPCG_CLK_0>;
 65		clock-indices = <IMX_LPCG_CLK_0>;
 66		clock-output-names = "mipi1_i2c0_lpcg_ipg_clk";
 67		power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
 68	};
 69
 70	mipi1_i2c0_lpcg_ipg_s_clk: clock-controller@57223018 {
 71		compatible = "fsl,imx8qxp-lpcg";
 72		reg = <0x57223018 0x4>;
 73		#clock-cells = <1>;
 74		clocks = <&dsi_ipg_clk>;
 75		clock-indices = <IMX_LPCG_CLK_0>;
 76		clock-output-names = "mipi1_i2c0_lpcg_ipg_s_clk";
 77		power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
 78	};
 79
 80	mipi1_i2c1_lpcg_ipg_clk: clock-controller@57223024 {
 81		compatible = "fsl,imx8qxp-lpcg";
 82		reg = <0x57223024 0x4>;
 83		#clock-cells = <1>;
 84		clocks = <&mipi1_i2c1_lpcg_ipg_s_clk IMX_LPCG_CLK_0>;
 85		clock-indices = <IMX_LPCG_CLK_0>;
 86		clock-output-names = "mipi1_i2c1_lpcg_ipg_clk";
 87		power-domains = <&pd IMX_SC_R_MIPI_1_I2C_1>;
 88	};
 89
 90	mipi1_i2c1_lpcg_ipg_s_clk: clock-controller@57223028 {
 91		compatible = "fsl,imx8qxp-lpcg";
 92		reg = <0x57223028 0x4>;
 93		#clock-cells = <1>;
 94		clocks = <&dsi_ipg_clk>;
 95		clock-indices = <IMX_LPCG_CLK_0>;
 96		clock-output-names = "mipi1_i2c1_lpcg_ipg_s_clk";
 97		power-domains = <&pd IMX_SC_R_MIPI_1_I2C_1>;
 98	};
 99
100	mipi1_i2c1_lpcg_clk: clock-controller@5722302c {
101		compatible = "fsl,imx8qxp-lpcg";
102		reg = <0x5722302c 0x4>;
103		#clock-cells = <1>;
104		clocks = <&clk IMX_SC_R_MIPI_1_I2C_1 IMX_SC_PM_CLK_MISC2>;
105		clock-indices = <IMX_LPCG_CLK_0>;
106		clock-output-names = "mipi1_i2c1_lpcg_clk";
107		power-domains = <&pd IMX_SC_R_MIPI_1_I2C_1>;
108	};
109
110	pwm_mipi1: pwm@57224000 {
111		compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
112		reg = <0x57224000 0x1000>;
113		clocks = <&mipi1_pwm_lpcg IMX_LPCG_CLK_4>,
114			 <&mipi1_pwm_lpcg IMX_LPCG_CLK_0>;
115		clock-names = "ipg", "per";
116		assigned-clocks = <&clk IMX_SC_R_MIPI_1_PWM_0 IMX_SC_PM_CLK_PER>;
117		assigned-clock-rates = <24000000>;
118		#pwm-cells = <3>;
119		power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>;
120		status = "disabled";
121	};
122
123	i2c0_mipi1: i2c@57226000 {
124		compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
125		reg = <0x57226000 0x1000>;
126		#address-cells = <1>;
127		#size-cells = <0>;
128		interrupts = <8>;
129		interrupt-parent = <&irqsteer_mipi1>;
130		clocks = <&mipi1_i2c0_lpcg_clk IMX_LPCG_CLK_0>,
131			 <&mipi1_i2c0_lpcg_ipg_clk IMX_LPCG_CLK_0>;
132		clock-names = "per", "ipg";
133		assigned-clocks = <&mipi1_i2c0_lpcg_clk IMX_LPCG_CLK_0>;
134		assigned-clock-rates = <24000000>;
135		power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
136		status = "disabled";
137	};
138};