imx8-ss-hsio.dtsi

  1// SPDX-License-Identifier: GPL-2.0+
  2/*
  3 * Copyright 2024 NXP
  4 *
  5 * Richard Zhu <hongxing.zhu@nxp.com>
  6 */
  7#include <dt-bindings/phy/phy.h>
  8
  9hsio_axi_clk: clock-hsio-axi {
 10	compatible = "fixed-clock";
 11	#clock-cells = <0>;
 12	clock-frequency = <400000000>;
 13	clock-output-names = "hsio_axi_clk";
 14};
 15
 16hsio_per_clk: clock-hsio-per {
 17	compatible = "fixed-clock";
 18	#clock-cells = <0>;
 19	clock-frequency = <133333333>;
 20	clock-output-names = "hsio_per_clk";
 21};
 22
 23hsio_refa_clk: clock-hsio-refa {
 24	compatible = "gpio-gate-clock";
 25	clocks = <&xtal100m>;
 26	#clock-cells = <0>;
 27	enable-gpios = <&lsio_gpio4 27 GPIO_ACTIVE_LOW>;
 28};
 29
 30hsio_refb_clk: clock-hsio-refb {
 31	compatible = "gpio-gate-clock";
 32	clocks = <&xtal100m>;
 33	#clock-cells = <0>;
 34	enable-gpios = <&lsio_gpio4 1 GPIO_ACTIVE_LOW>;
 35};
 36
 37xtal100m: clock-xtal100m {
 38	compatible = "fixed-clock";
 39	#clock-cells = <0>;
 40	clock-frequency = <100000000>;
 41	clock-output-names = "xtal_100MHz";
 42};
 43
 44hsio_subsys: bus@5f000000 {
 45	compatible = "simple-bus";
 46	ranges = <0x5f000000 0x0 0x5f000000 0x01000000>,
 47		 <0x80000000 0x0 0x70000000 0x10000000>;
 48	#address-cells = <1>;
 49	#size-cells = <1>;
 50	dma-ranges = <0x80000000 0 0x80000000 0x80000000>;
 51
 52	pcieb: pcie@5f010000 {
 53		compatible = "fsl,imx8q-pcie";
 54		reg = <0x5f010000 0x10000>,
 55		      <0x8ff00000 0x80000>;
 56		reg-names = "dbi", "config";
 57		ranges = <0x81000000 0 0x00000000 0x8ff80000 0 0x00010000>,
 58			 <0x82000000 0 0x80000000 0x80000000 0 0x0ff00000>;
 59		#interrupt-cells = <1>;
 60		interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 61			     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 62		interrupt-names = "msi", "dma";
 63		#address-cells = <3>;
 64		#size-cells = <2>;
 65		clocks = <&pcieb_lpcg IMX_LPCG_CLK_6>,
 66			 <&pcieb_lpcg IMX_LPCG_CLK_4>,
 67			 <&pcieb_lpcg IMX_LPCG_CLK_5>;
 68		clock-names = "dbi", "mstr", "slv";
 69		bus-range = <0x00 0xff>;
 70		device_type = "pci";
 71		interrupt-map = <0 0 0 1 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 72				<0 0 0 2 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 73				<0 0 0 3 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 74				<0 0 0 4 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 75		interrupt-map-mask = <0 0 0 0x7>;
 76		num-lanes = <1>;
 77		num-viewport = <4>;
 78		power-domains = <&pd IMX_SC_R_PCIE_B>;
 79		fsl,max-link-speed = <3>;
 80		status = "disabled";
 81	};
 82
 83	pcieb_ep: pcie-ep@5f010000 {
 84		compatible = "fsl,imx8q-pcie-ep";
 85		reg = <0x5f010000 0x00010000>,
 86		      <0x80000000 0x10000000>;
 87		reg-names = "dbi", "addr_space";
 88		num-lanes = <1>;
 89		interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 90		interrupt-names = "dma";
 91		clocks = <&pcieb_lpcg IMX_LPCG_CLK_6>,
 92			 <&pcieb_lpcg IMX_LPCG_CLK_4>,
 93			 <&pcieb_lpcg IMX_LPCG_CLK_5>;
 94		clock-names = "dbi", "mstr", "slv";
 95		power-domains = <&pd IMX_SC_R_PCIE_B>;
 96		fsl,max-link-speed = <3>;
 97		num-ib-windows = <6>;
 98		num-ob-windows = <6>;
 99		status = "disabled";
100	};
101
102	pcieb_lpcg: clock-controller@5f060000 {
103		compatible = "fsl,imx8qxp-lpcg";
104		reg = <0x5f060000 0x10000>;
105		clocks = <&hsio_axi_clk>, <&hsio_axi_clk>, <&hsio_axi_clk>;
106		#clock-cells = <1>;
107		clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>, <IMX_LPCG_CLK_6>;
108		clock-output-names = "hsio_pcieb_mstr_axi_clk",
109				     "hsio_pcieb_slv_axi_clk",
110				     "hsio_pcieb_dbi_axi_clk";
111		power-domains = <&pd IMX_SC_R_PCIE_B>;
112	};
113
114	phyx1_crr1_lpcg: clock-controller@5f0b0000 {
115		compatible = "fsl,imx8qxp-lpcg";
116		reg = <0x5f0b0000 0x10000>;
117		clocks = <&hsio_per_clk>;
118		#clock-cells = <1>;
119		clock-indices = <IMX_LPCG_CLK_4>;
120		clock-output-names = "hsio_phyx1_per_clk";
121		power-domains = <&pd IMX_SC_R_SERDES_1>;
122	};
123
124	pcieb_crr3_lpcg: clock-controller@5f0d0000 {
125		compatible = "fsl,imx8qxp-lpcg";
126		reg = <0x5f0d0000 0x10000>;
127		clocks = <&hsio_per_clk>;
128		#clock-cells = <1>;
129		clock-indices = <IMX_LPCG_CLK_4>;
130		clock-output-names = "hsio_pcieb_per_clk";
131		power-domains = <&pd IMX_SC_R_PCIE_B>;
132	};
133
134	misc_crr5_lpcg: clock-controller@5f0f0000 {
135		compatible = "fsl,imx8qxp-lpcg";
136		reg = <0x5f0f0000 0x10000>;
137		clocks = <&hsio_per_clk>;
138		#clock-cells = <1>;
139		clock-indices = <IMX_LPCG_CLK_4>;
140		clock-output-names = "hsio_misc_per_clk";
141		power-domains = <&pd IMX_SC_R_HSIO_GPIO>;
142	};
143};