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fsl-lx2160a.dtsi
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linux-6.19.14/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2// 3// Device Tree Include file for Layerscape-LX2160A family SoC. 4// 5// Copyright 2018-2020 NXP 6 7#include <dt-bindings/clock/fsl,qoriq-clockgen.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/thermal/thermal.h> 11 12/memreserve/ 0x80000000 0x00010000; 13 14/ { 15 compatible = "fsl,lx2160a"; 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 rtc1 = &ftm_alarm0; 22 }; 23 24 cpus { 25 #address-cells = <1>; 26 #size-cells = <0>; 27 28 // 8 clusters having 2 Cortex-A72 cores each 29 cpu0: cpu@0 { 30 device_type = "cpu"; 31 compatible = "arm,cortex-a72"; 32 enable-method = "psci"; 33 reg = <0x0>; 34 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 35 d-cache-size = <0x8000>; 36 d-cache-line-size = <64>; 37 d-cache-sets = <128>; 38 i-cache-size = <0xC000>; 39 i-cache-line-size = <64>; 40 i-cache-sets = <192>; 41 next-level-cache = <&cluster0_l2>; 42 cpu-idle-states = <&cpu_pw15>; 43 #cooling-cells = <2>; 44 }; 45 46 cpu1: cpu@1 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a72"; 49 enable-method = "psci"; 50 reg = <0x1>; 51 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 52 d-cache-size = <0x8000>; 53 d-cache-line-size = <64>; 54 d-cache-sets = <128>; 55 i-cache-size = <0xC000>; 56 i-cache-line-size = <64>; 57 i-cache-sets = <192>; 58 next-level-cache = <&cluster0_l2>; 59 cpu-idle-states = <&cpu_pw15>; 60 #cooling-cells = <2>; 61 }; 62 63 cpu100: cpu@100 { 64 device_type = "cpu"; 65 compatible = "arm,cortex-a72"; 66 enable-method = "psci"; 67 reg = <0x100>; 68 clocks = <&clockgen QORIQ_CLK_CMUX 1>; 69 d-cache-size = <0x8000>; 70 d-cache-line-size = <64>; 71 d-cache-sets = <128>; 72 i-cache-size = <0xC000>; 73 i-cache-line-size = <64>; 74 i-cache-sets = <192>; 75 next-level-cache = <&cluster1_l2>; 76 cpu-idle-states = <&cpu_pw15>; 77 #cooling-cells = <2>; 78 }; 79 80 cpu101: cpu@101 { 81 device_type = "cpu"; 82 compatible = "arm,cortex-a72"; 83 enable-method = "psci"; 84 reg = <0x101>; 85 clocks = <&clockgen QORIQ_CLK_CMUX 1>; 86 d-cache-size = <0x8000>; 87 d-cache-line-size = <64>; 88 d-cache-sets = <128>; 89 i-cache-size = <0xC000>; 90 i-cache-line-size = <64>; 91 i-cache-sets = <192>; 92 next-level-cache = <&cluster1_l2>; 93 cpu-idle-states = <&cpu_pw15>; 94 #cooling-cells = <2>; 95 }; 96 97 cpu200: cpu@200 { 98 device_type = "cpu"; 99 compatible = "arm,cortex-a72"; 100 enable-method = "psci"; 101 reg = <0x200>; 102 clocks = <&clockgen QORIQ_CLK_CMUX 2>; 103 d-cache-size = <0x8000>; 104 d-cache-line-size = <64>; 105 d-cache-sets = <128>; 106 i-cache-size = <0xC000>; 107 i-cache-line-size = <64>; 108 i-cache-sets = <192>; 109 next-level-cache = <&cluster2_l2>; 110 cpu-idle-states = <&cpu_pw15>; 111 #cooling-cells = <2>; 112 }; 113 114 cpu201: cpu@201 { 115 device_type = "cpu"; 116 compatible = "arm,cortex-a72"; 117 enable-method = "psci"; 118 reg = <0x201>; 119 clocks = <&clockgen QORIQ_CLK_CMUX 2>; 120 d-cache-size = <0x8000>; 121 d-cache-line-size = <64>; 122 d-cache-sets = <128>; 123 i-cache-size = <0xC000>; 124 i-cache-line-size = <64>; 125 i-cache-sets = <192>; 126 next-level-cache = <&cluster2_l2>; 127 cpu-idle-states = <&cpu_pw15>; 128 #cooling-cells = <2>; 129 }; 130 131 cpu300: cpu@300 { 132 device_type = "cpu"; 133 compatible = "arm,cortex-a72"; 134 enable-method = "psci"; 135 reg = <0x300>; 136 clocks = <&clockgen QORIQ_CLK_CMUX 3>; 137 d-cache-size = <0x8000>; 138 d-cache-line-size = <64>; 139 d-cache-sets = <128>; 140 i-cache-size = <0xC000>; 141 i-cache-line-size = <64>; 142 i-cache-sets = <192>; 143 next-level-cache = <&cluster3_l2>; 144 cpu-idle-states = <&cpu_pw15>; 145 #cooling-cells = <2>; 146 }; 147 148 cpu301: cpu@301 { 149 device_type = "cpu"; 150 compatible = "arm,cortex-a72"; 151 enable-method = "psci"; 152 reg = <0x301>; 153 clocks = <&clockgen QORIQ_CLK_CMUX 3>; 154 d-cache-size = <0x8000>; 155 d-cache-line-size = <64>; 156 d-cache-sets = <128>; 157 i-cache-size = <0xC000>; 158 i-cache-line-size = <64>; 159 i-cache-sets = <192>; 160 next-level-cache = <&cluster3_l2>; 161 cpu-idle-states = <&cpu_pw15>; 162 #cooling-cells = <2>; 163 }; 164 165 cpu400: cpu@400 { 166 device_type = "cpu"; 167 compatible = "arm,cortex-a72"; 168 enable-method = "psci"; 169 reg = <0x400>; 170 clocks = <&clockgen QORIQ_CLK_CMUX 4>; 171 d-cache-size = <0x8000>; 172 d-cache-line-size = <64>; 173 d-cache-sets = <128>; 174 i-cache-size = <0xC000>; 175 i-cache-line-size = <64>; 176 i-cache-sets = <192>; 177 next-level-cache = <&cluster4_l2>; 178 cpu-idle-states = <&cpu_pw15>; 179 #cooling-cells = <2>; 180 }; 181 182 cpu401: cpu@401 { 183 device_type = "cpu"; 184 compatible = "arm,cortex-a72"; 185 enable-method = "psci"; 186 reg = <0x401>; 187 clocks = <&clockgen QORIQ_CLK_CMUX 4>; 188 d-cache-size = <0x8000>; 189 d-cache-line-size = <64>; 190 d-cache-sets = <128>; 191 i-cache-size = <0xC000>; 192 i-cache-line-size = <64>; 193 i-cache-sets = <192>; 194 next-level-cache = <&cluster4_l2>; 195 cpu-idle-states = <&cpu_pw15>; 196 #cooling-cells = <2>; 197 }; 198 199 cpu500: cpu@500 { 200 device_type = "cpu"; 201 compatible = "arm,cortex-a72"; 202 enable-method = "psci"; 203 reg = <0x500>; 204 clocks = <&clockgen QORIQ_CLK_CMUX 5>; 205 d-cache-size = <0x8000>; 206 d-cache-line-size = <64>; 207 d-cache-sets = <128>; 208 i-cache-size = <0xC000>; 209 i-cache-line-size = <64>; 210 i-cache-sets = <192>; 211 next-level-cache = <&cluster5_l2>; 212 cpu-idle-states = <&cpu_pw15>; 213 #cooling-cells = <2>; 214 }; 215 216 cpu501: cpu@501 { 217 device_type = "cpu"; 218 compatible = "arm,cortex-a72"; 219 enable-method = "psci"; 220 reg = <0x501>; 221 clocks = <&clockgen QORIQ_CLK_CMUX 5>; 222 d-cache-size = <0x8000>; 223 d-cache-line-size = <64>; 224 d-cache-sets = <128>; 225 i-cache-size = <0xC000>; 226 i-cache-line-size = <64>; 227 i-cache-sets = <192>; 228 next-level-cache = <&cluster5_l2>; 229 cpu-idle-states = <&cpu_pw15>; 230 #cooling-cells = <2>; 231 }; 232 233 cpu600: cpu@600 { 234 device_type = "cpu"; 235 compatible = "arm,cortex-a72"; 236 enable-method = "psci"; 237 reg = <0x600>; 238 clocks = <&clockgen QORIQ_CLK_CMUX 6>; 239 d-cache-size = <0x8000>; 240 d-cache-line-size = <64>; 241 d-cache-sets = <128>; 242 i-cache-size = <0xC000>; 243 i-cache-line-size = <64>; 244 i-cache-sets = <192>; 245 next-level-cache = <&cluster6_l2>; 246 cpu-idle-states = <&cpu_pw15>; 247 #cooling-cells = <2>; 248 }; 249 250 cpu601: cpu@601 { 251 device_type = "cpu"; 252 compatible = "arm,cortex-a72"; 253 enable-method = "psci"; 254 reg = <0x601>; 255 clocks = <&clockgen QORIQ_CLK_CMUX 6>; 256 d-cache-size = <0x8000>; 257 d-cache-line-size = <64>; 258 d-cache-sets = <128>; 259 i-cache-size = <0xC000>; 260 i-cache-line-size = <64>; 261 i-cache-sets = <192>; 262 next-level-cache = <&cluster6_l2>; 263 cpu-idle-states = <&cpu_pw15>; 264 #cooling-cells = <2>; 265 }; 266 267 cpu700: cpu@700 { 268 device_type = "cpu"; 269 compatible = "arm,cortex-a72"; 270 enable-method = "psci"; 271 reg = <0x700>; 272 clocks = <&clockgen QORIQ_CLK_CMUX 7>; 273 d-cache-size = <0x8000>; 274 d-cache-line-size = <64>; 275 d-cache-sets = <128>; 276 i-cache-size = <0xC000>; 277 i-cache-line-size = <64>; 278 i-cache-sets = <192>; 279 next-level-cache = <&cluster7_l2>; 280 cpu-idle-states = <&cpu_pw15>; 281 #cooling-cells = <2>; 282 }; 283 284 cpu701: cpu@701 { 285 device_type = "cpu"; 286 compatible = "arm,cortex-a72"; 287 enable-method = "psci"; 288 reg = <0x701>; 289 clocks = <&clockgen QORIQ_CLK_CMUX 7>; 290 d-cache-size = <0x8000>; 291 d-cache-line-size = <64>; 292 d-cache-sets = <128>; 293 i-cache-size = <0xC000>; 294 i-cache-line-size = <64>; 295 i-cache-sets = <192>; 296 next-level-cache = <&cluster7_l2>; 297 cpu-idle-states = <&cpu_pw15>; 298 #cooling-cells = <2>; 299 }; 300 301 cluster0_l2: l2-cache0 { 302 compatible = "cache"; 303 cache-unified; 304 cache-size = <0x100000>; 305 cache-line-size = <64>; 306 cache-sets = <1024>; 307 cache-level = <2>; 308 }; 309 310 cluster1_l2: l2-cache1 { 311 compatible = "cache"; 312 cache-unified; 313 cache-size = <0x100000>; 314 cache-line-size = <64>; 315 cache-sets = <1024>; 316 cache-level = <2>; 317 }; 318 319 cluster2_l2: l2-cache2 { 320 compatible = "cache"; 321 cache-unified; 322 cache-size = <0x100000>; 323 cache-line-size = <64>; 324 cache-sets = <1024>; 325 cache-level = <2>; 326 }; 327 328 cluster3_l2: l2-cache3 { 329 compatible = "cache"; 330 cache-unified; 331 cache-size = <0x100000>; 332 cache-line-size = <64>; 333 cache-sets = <1024>; 334 cache-level = <2>; 335 }; 336 337 cluster4_l2: l2-cache4 { 338 compatible = "cache"; 339 cache-unified; 340 cache-size = <0x100000>; 341 cache-line-size = <64>; 342 cache-sets = <1024>; 343 cache-level = <2>; 344 }; 345 346 cluster5_l2: l2-cache5 { 347 compatible = "cache"; 348 cache-unified; 349 cache-size = <0x100000>; 350 cache-line-size = <64>; 351 cache-sets = <1024>; 352 cache-level = <2>; 353 }; 354 355 cluster6_l2: l2-cache6 { 356 compatible = "cache"; 357 cache-unified; 358 cache-size = <0x100000>; 359 cache-line-size = <64>; 360 cache-sets = <1024>; 361 cache-level = <2>; 362 }; 363 364 cluster7_l2: l2-cache7 { 365 compatible = "cache"; 366 cache-unified; 367 cache-size = <0x100000>; 368 cache-line-size = <64>; 369 cache-sets = <1024>; 370 cache-level = <2>; 371 }; 372 373 cpu_pw15: cpu-pw15 { 374 compatible = "arm,idle-state"; 375 idle-state-name = "PW15"; 376 arm,psci-suspend-param = <0x0>; 377 entry-latency-us = <2000>; 378 exit-latency-us = <2000>; 379 min-residency-us = <6000>; 380 }; 381 }; 382 383 gic: interrupt-controller@6000000 { 384 compatible = "arm,gic-v3"; 385 reg = <0x0 0x06000000 0 0x10000>, // GIC Dist 386 <0x0 0x06200000 0 0x200000>, // GICR (RD_base + 387 // SGI_base) 388 <0x0 0x0c0c0000 0 0x2000>, // GICC 389 <0x0 0x0c0d0000 0 0x1000>, // GICH 390 <0x0 0x0c0e0000 0 0x20000>; // GICV 391 #interrupt-cells = <3>; 392 #address-cells = <2>; 393 #size-cells = <2>; 394 ranges; 395 interrupt-controller; 396 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 397 398 its: msi-controller@6020000 { 399 compatible = "arm,gic-v3-its"; 400 msi-controller; 401 #msi-cells = <1>; 402 reg = <0x0 0x6020000 0 0x20000>; 403 }; 404 }; 405 406 timer { 407 compatible = "arm,armv8-timer"; 408 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, 409 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, 410 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, 411 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; 412 }; 413 414 pmu { 415 compatible = "arm,cortex-a72-pmu"; 416 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 417 }; 418 419 psci { 420 compatible = "arm,psci-0.2"; 421 method = "smc"; 422 }; 423 424 memory@80000000 { 425 // DRAM space - 1, size : 2 GB DRAM 426 device_type = "memory"; 427 reg = <0x00000000 0x80000000 0 0x80000000>; 428 }; 429 430 ddr1: memory-controller@1080000 { 431 compatible = "fsl,qoriq-memory-controller"; 432 reg = <0x0 0x1080000 0x0 0x1000>; 433 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 434 little-endian; 435 }; 436 437 ddr2: memory-controller@1090000 { 438 compatible = "fsl,qoriq-memory-controller"; 439 reg = <0x0 0x1090000 0x0 0x1000>; 440 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 441 little-endian; 442 }; 443 444 // One clock unit-sysclk node which bootloader require during DT fix-up 445 sysclk: sysclk { 446 compatible = "fixed-clock"; 447 #clock-cells = <0>; 448 clock-frequency = <100000000>; // fixed up by bootloader 449 clock-output-names = "sysclk"; 450 }; 451 452 thermal-zones { 453 cluster6-7-thermal { 454 polling-delay-passive = <1000>; 455 polling-delay = <5000>; 456 thermal-sensors = <&tmu 0>; 457 458 trips { 459 cluster6_7_alert: cluster6-7-alert { 460 temperature = <85000>; 461 hysteresis = <2000>; 462 type = "passive"; 463 }; 464 465 cluster6_7_crit: cluster6-7-crit { 466 temperature = <95000>; 467 hysteresis = <2000>; 468 type = "critical"; 469 }; 470 }; 471 472 cooling-maps { 473 map0 { 474 trip = <&cluster6_7_alert>; 475 cooling-device = 476 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 477 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 478 <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 479 <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 480 <&cpu200 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 481 <&cpu201 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 482 <&cpu300 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 483 <&cpu301 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 484 <&cpu400 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 485 <&cpu401 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 486 <&cpu500 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 487 <&cpu501 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 488 <&cpu600 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 489 <&cpu601 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 490 <&cpu700 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 491 <&cpu701 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 492 }; 493 }; 494 }; 495 496 ddr-ctrl5-thermal { 497 polling-delay-passive = <1000>; 498 polling-delay = <5000>; 499 thermal-sensors = <&tmu 1>; 500 501 trips { 502 ddr-cluster5-alert { 503 temperature = <85000>; 504 hysteresis = <2000>; 505 type = "passive"; 506 }; 507 508 ddr-cluster5-crit { 509 temperature = <95000>; 510 hysteresis = <2000>; 511 type = "critical"; 512 }; 513 }; 514 }; 515 516 wriop-thermal { 517 polling-delay-passive = <1000>; 518 polling-delay = <5000>; 519 thermal-sensors = <&tmu 2>; 520 521 trips { 522 wriop-alert { 523 temperature = <85000>; 524 hysteresis = <2000>; 525 type = "passive"; 526 }; 527 528 wriop-crit { 529 temperature = <95000>; 530 hysteresis = <2000>; 531 type = "critical"; 532 }; 533 }; 534 }; 535 536 dce-thermal { 537 polling-delay-passive = <1000>; 538 polling-delay = <5000>; 539 thermal-sensors = <&tmu 3>; 540 541 trips { 542 dce-qbman-alert { 543 temperature = <85000>; 544 hysteresis = <2000>; 545 type = "passive"; 546 }; 547 548 dce-qbman-crit { 549 temperature = <95000>; 550 hysteresis = <2000>; 551 type = "critical"; 552 }; 553 }; 554 }; 555 556 ccn-thermal { 557 polling-delay-passive = <1000>; 558 polling-delay = <5000>; 559 thermal-sensors = <&tmu 4>; 560 561 trips { 562 ccn-dpaa-alert { 563 temperature = <85000>; 564 hysteresis = <2000>; 565 type = "passive"; 566 }; 567 568 ccn-dpaa-crit { 569 temperature = <95000>; 570 hysteresis = <2000>; 571 type = "critical"; 572 }; 573 }; 574 }; 575 576 cluster4-thermal { 577 polling-delay-passive = <1000>; 578 polling-delay = <5000>; 579 thermal-sensors = <&tmu 5>; 580 581 trips { 582 clust4-hsio3-alert { 583 temperature = <85000>; 584 hysteresis = <2000>; 585 type = "passive"; 586 }; 587 588 clust4-hsio3-crit { 589 temperature = <95000>; 590 hysteresis = <2000>; 591 type = "critical"; 592 }; 593 }; 594 }; 595 596 cluster2-3-thermal { 597 polling-delay-passive = <1000>; 598 polling-delay = <5000>; 599 thermal-sensors = <&tmu 6>; 600 601 trips { 602 cluster2-3-alert { 603 temperature = <85000>; 604 hysteresis = <2000>; 605 type = "passive"; 606 }; 607 608 cluster2-3-crit { 609 temperature = <95000>; 610 hysteresis = <2000>; 611 type = "critical"; 612 }; 613 }; 614 }; 615 }; 616 617 soc: soc { 618 compatible = "simple-bus"; 619 #address-cells = <2>; 620 #size-cells = <2>; 621 ranges; 622 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; 623 624 serdes_1: phy@1ea0000 { 625 compatible = "fsl,lynx-28g"; 626 reg = <0x0 0x1ea0000 0x0 0x1e30>; 627 #phy-cells = <1>; 628 }; 629 630 serdes_2: phy@1eb0000 { 631 compatible = "fsl,lynx-28g"; 632 reg = <0x0 0x1eb0000 0x0 0x1e30>; 633 #phy-cells = <1>; 634 status = "disabled"; 635 }; 636 637 crypto: crypto@8000000 { 638 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 639 fsl,sec-era = <10>; 640 #address-cells = <1>; 641 #size-cells = <1>; 642 ranges = <0x0 0x00 0x8000000 0x100000>; 643 reg = <0x00 0x8000000 0x0 0x100000>; 644 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 645 dma-coherent; 646 status = "disabled"; 647 648 sec_jr0: jr@10000 { 649 compatible = "fsl,sec-v5.0-job-ring", 650 "fsl,sec-v4.0-job-ring"; 651 reg = <0x10000 0x10000>; 652 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 653 }; 654 655 sec_jr1: jr@20000 { 656 compatible = "fsl,sec-v5.0-job-ring", 657 "fsl,sec-v4.0-job-ring"; 658 reg = <0x20000 0x10000>; 659 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 660 }; 661 662 sec_jr2: jr@30000 { 663 compatible = "fsl,sec-v5.0-job-ring", 664 "fsl,sec-v4.0-job-ring"; 665 reg = <0x30000 0x10000>; 666 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 667 }; 668 669 sec_jr3: jr@40000 { 670 compatible = "fsl,sec-v5.0-job-ring", 671 "fsl,sec-v4.0-job-ring"; 672 reg = <0x40000 0x10000>; 673 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 674 }; 675 }; 676 677 clockgen: clock-controller@1300000 { 678 compatible = "fsl,lx2160a-clockgen"; 679 reg = <0 0x1300000 0 0xa0000>; 680 #clock-cells = <2>; 681 clocks = <&sysclk>; 682 }; 683 684 dcfg: syscon@1e00000 { 685 compatible = "fsl,lx2160a-dcfg", "syscon"; 686 reg = <0x0 0x1e00000 0x0 0x10000>; 687 little-endian; 688 }; 689 690 sfp: efuse@1e80000 { 691 compatible = "fsl,ls1028a-sfp"; 692 reg = <0x0 0x1e80000 0x0 0x10000>; 693 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 694 QORIQ_CLK_PLL_DIV(4)>; 695 clock-names = "sfp"; 696 }; 697 698 isc: syscon@1f70000 { 699 compatible = "fsl,lx2160a-isc", "syscon"; 700 reg = <0x0 0x1f70000 0x0 0x10000>; 701 little-endian; 702 #address-cells = <1>; 703 #size-cells = <1>; 704 ranges = <0x0 0x0 0x1f70000 0x10000>; 705 706 extirq: interrupt-controller@14 { 707 compatible = "fsl,lx2160a-extirq", "fsl,ls1088a-extirq"; 708 #interrupt-cells = <2>; 709 #address-cells = <0>; 710 interrupt-controller; 711 reg = <0x14 4>; 712 interrupt-map = 713 <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 714 <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 715 <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 716 <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 717 <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 718 <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 719 <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 720 <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 721 <8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 722 <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 723 <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 724 <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 725 interrupt-map-mask = <0xf 0x0>; 726 }; 727 }; 728 729 tmu: tmu@1f80000 { 730 compatible = "fsl,qoriq-tmu"; 731 reg = <0x0 0x1f80000 0x0 0x10000>; 732 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 733 fsl,tmu-range = <0x800000e6 0x8001017d>; 734 fsl,tmu-calibration = 735 /* Calibration data group 1 */ 736 <0x00000000 0x00000035>, 737 /* Calibration data group 2 */ 738 <0x00000001 0x00000154>; 739 little-endian; 740 #thermal-sensor-cells = <1>; 741 }; 742 743 i2c0: i2c@2000000 { 744 compatible = "fsl,vf610-i2c"; 745 #address-cells = <1>; 746 #size-cells = <0>; 747 reg = <0x0 0x2000000 0x0 0x10000>; 748 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 749 clock-names = "ipg"; 750 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 751 QORIQ_CLK_PLL_DIV(16)>; 752 pinctrl-names = "default", "gpio"; 753 pinctrl-0 = <&i2c0_scl>; 754 pinctrl-1 = <&i2c0_scl_gpio>; 755 scl-gpios = <&gpio0 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 756 status = "disabled"; 757 }; 758 759 i2c1: i2c@2010000 { 760 compatible = "fsl,vf610-i2c"; 761 #address-cells = <1>; 762 #size-cells = <0>; 763 reg = <0x0 0x2010000 0x0 0x10000>; 764 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 765 clock-names = "ipg"; 766 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 767 QORIQ_CLK_PLL_DIV(16)>; 768 pinctrl-names = "default", "gpio"; 769 pinctrl-0 = <&i2c1_scl>; 770 pinctrl-1 = <&i2c1_scl_gpio>; 771 scl-gpios = <&gpio0 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 772 status = "disabled"; 773 }; 774 775 i2c2: i2c@2020000 { 776 compatible = "fsl,vf610-i2c"; 777 #address-cells = <1>; 778 #size-cells = <0>; 779 reg = <0x0 0x2020000 0x0 0x10000>; 780 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 781 clock-names = "ipg"; 782 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 783 QORIQ_CLK_PLL_DIV(16)>; 784 pinctrl-names = "default", "gpio"; 785 pinctrl-0 = <&i2c2_scl>; 786 pinctrl-1 = <&i2c2_scl_gpio>; 787 scl-gpios = <&gpio0 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 788 status = "disabled"; 789 }; 790 791 i2c3: i2c@2030000 { 792 compatible = "fsl,vf610-i2c"; 793 #address-cells = <1>; 794 #size-cells = <0>; 795 reg = <0x0 0x2030000 0x0 0x10000>; 796 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 797 clock-names = "ipg"; 798 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 799 QORIQ_CLK_PLL_DIV(16)>; 800 pinctrl-names = "default", "gpio"; 801 pinctrl-0 = <&i2c3_scl>; 802 pinctrl-1 = <&i2c3_scl_gpio>; 803 scl-gpios = <&gpio0 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 804 status = "disabled"; 805 }; 806 807 i2c4: i2c@2040000 { 808 compatible = "fsl,vf610-i2c"; 809 #address-cells = <1>; 810 #size-cells = <0>; 811 reg = <0x0 0x2040000 0x0 0x10000>; 812 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 813 clock-names = "ipg"; 814 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 815 QORIQ_CLK_PLL_DIV(16)>; 816 pinctrl-names = "default", "gpio"; 817 pinctrl-0 = <&i2c4_scl>; 818 pinctrl-1 = <&i2c4_scl_gpio>; 819 scl-gpios = <&gpio0 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 820 status = "disabled"; 821 }; 822 823 i2c5: i2c@2050000 { 824 compatible = "fsl,vf610-i2c"; 825 #address-cells = <1>; 826 #size-cells = <0>; 827 reg = <0x0 0x2050000 0x0 0x10000>; 828 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 829 clock-names = "ipg"; 830 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 831 QORIQ_CLK_PLL_DIV(16)>; 832 pinctrl-names = "default", "gpio"; 833 pinctrl-0 = <&i2c5_scl>; 834 pinctrl-1 = <&i2c5_scl_gpio>; 835 scl-gpios = <&gpio0 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 836 status = "disabled"; 837 }; 838 839 i2c6: i2c@2060000 { 840 compatible = "fsl,vf610-i2c"; 841 #address-cells = <1>; 842 #size-cells = <0>; 843 reg = <0x0 0x2060000 0x0 0x10000>; 844 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 845 clock-names = "ipg"; 846 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 847 QORIQ_CLK_PLL_DIV(16)>; 848 pinctrl-names = "default", "gpio"; 849 pinctrl-0 = <&i2c6_scl>; 850 pinctrl-1 = <&i2c6_scl_gpio>; 851 scl-gpios = <&gpio1 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 852 status = "disabled"; 853 }; 854 855 i2c7: i2c@2070000 { 856 compatible = "fsl,vf610-i2c"; 857 #address-cells = <1>; 858 #size-cells = <0>; 859 reg = <0x0 0x2070000 0x0 0x10000>; 860 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 861 clock-names = "ipg"; 862 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 863 QORIQ_CLK_PLL_DIV(16)>; 864 pinctrl-names = "default", "gpio"; 865 pinctrl-0 = <&i2c7_scl>; 866 pinctrl-1 = <&i2c7_scl_gpio>; 867 scl-gpios = <&gpio1 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 868 status = "disabled"; 869 }; 870 871 fspi: spi@20c0000 { 872 compatible = "nxp,lx2160a-fspi"; 873 #address-cells = <1>; 874 #size-cells = <0>; 875 reg = <0x0 0x20c0000 0x0 0x10000>, 876 <0x0 0x20000000 0x0 0x10000000>; 877 reg-names = "fspi_base", "fspi_mmap"; 878 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 879 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 880 QORIQ_CLK_PLL_DIV(4)>, 881 <&clockgen QORIQ_CLK_PLATFORM_PLL 882 QORIQ_CLK_PLL_DIV(4)>; 883 clock-names = "fspi_en", "fspi"; 884 status = "disabled"; 885 }; 886 887 dspi0: spi@2100000 { 888 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi"; 889 #address-cells = <1>; 890 #size-cells = <0>; 891 reg = <0x0 0x2100000 0x0 0x10000>; 892 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 893 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 894 QORIQ_CLK_PLL_DIV(8)>; 895 clock-names = "dspi"; 896 spi-num-chipselects = <5>; 897 bus-num = <0>; 898 status = "disabled"; 899 }; 900 901 dspi1: spi@2110000 { 902 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi"; 903 #address-cells = <1>; 904 #size-cells = <0>; 905 reg = <0x0 0x2110000 0x0 0x10000>; 906 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 907 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 908 QORIQ_CLK_PLL_DIV(8)>; 909 clock-names = "dspi"; 910 spi-num-chipselects = <5>; 911 bus-num = <1>; 912 status = "disabled"; 913 }; 914 915 dspi2: spi@2120000 { 916 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi"; 917 #address-cells = <1>; 918 #size-cells = <0>; 919 reg = <0x0 0x2120000 0x0 0x10000>; 920 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 921 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 922 QORIQ_CLK_PLL_DIV(8)>; 923 clock-names = "dspi"; 924 spi-num-chipselects = <5>; 925 bus-num = <2>; 926 status = "disabled"; 927 }; 928 929 esdhc0: mmc@2140000 { 930 compatible = "fsl,ls2080a-esdhc", "fsl,esdhc"; 931 reg = <0x0 0x2140000 0x0 0x10000>; 932 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 933 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 934 QORIQ_CLK_PLL_DIV(2)>; 935 dma-coherent; 936 voltage-ranges = <1800 1800 3300 3300>; 937 sdhci,auto-cmd12; 938 little-endian; 939 bus-width = <4>; 940 status = "disabled"; 941 }; 942 943 esdhc1: mmc@2150000 { 944 compatible = "fsl,ls2080a-esdhc", "fsl,esdhc"; 945 reg = <0x0 0x2150000 0x0 0x10000>; 946 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 947 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 948 QORIQ_CLK_PLL_DIV(2)>; 949 dma-coherent; 950 voltage-ranges = <1800 1800 3300 3300>; 951 sdhci,auto-cmd12; 952 broken-cd; 953 little-endian; 954 bus-width = <4>; 955 status = "disabled"; 956 }; 957 958 can0: can@2180000 { 959 compatible = "fsl,lx2160ar1-flexcan"; 960 reg = <0x0 0x2180000 0x0 0x10000>; 961 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 962 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 963 QORIQ_CLK_PLL_DIV(8)>, 964 <&clockgen QORIQ_CLK_SYSCLK 0>; 965 clock-names = "ipg", "per"; 966 fsl,clk-source = /bits/ 8 <0>; 967 status = "disabled"; 968 }; 969 970 can1: can@2190000 { 971 compatible = "fsl,lx2160ar1-flexcan"; 972 reg = <0x0 0x2190000 0x0 0x10000>; 973 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 974 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 975 QORIQ_CLK_PLL_DIV(8)>, 976 <&clockgen QORIQ_CLK_SYSCLK 0>; 977 clock-names = "ipg", "per"; 978 fsl,clk-source = /bits/ 8 <0>; 979 status = "disabled"; 980 }; 981 982 uart0: serial@21c0000 { 983 compatible = "arm,pl011", "arm,primecell"; 984 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 985 QORIQ_CLK_PLL_DIV(8)>, 986 <&clockgen QORIQ_CLK_PLATFORM_PLL 987 QORIQ_CLK_PLL_DIV(8)>; 988 clock-names = "uartclk", "apb_pclk"; 989 reg = <0x0 0x21c0000 0x0 0x1000>; 990 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 991 status = "disabled"; 992 }; 993 994 uart1: serial@21d0000 { 995 compatible = "arm,pl011", "arm,primecell"; 996 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 997 QORIQ_CLK_PLL_DIV(8)>, 998 <&clockgen QORIQ_CLK_PLATFORM_PLL 999 QORIQ_CLK_PLL_DIV(8)>; 1000 clock-names = "uartclk", "apb_pclk"; 1001 reg = <0x0 0x21d0000 0x0 0x1000>; 1002 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1003 status = "disabled"; 1004 }; 1005 1006 uart2: serial@21e0000 { 1007 compatible = "arm,pl011", "arm,primecell"; 1008 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1009 QORIQ_CLK_PLL_DIV(8)>, 1010 <&clockgen QORIQ_CLK_PLATFORM_PLL 1011 QORIQ_CLK_PLL_DIV(8)>; 1012 clock-names = "uartclk", "apb_pclk"; 1013 reg = <0x0 0x21e0000 0x0 0x1000>; 1014 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1015 status = "disabled"; 1016 }; 1017 1018 uart3: serial@21f0000 { 1019 compatible = "arm,pl011", "arm,primecell"; 1020 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1021 QORIQ_CLK_PLL_DIV(8)>, 1022 <&clockgen QORIQ_CLK_PLATFORM_PLL 1023 QORIQ_CLK_PLL_DIV(8)>; 1024 clock-names = "uartclk", "apb_pclk"; 1025 reg = <0x0 0x21f0000 0x0 0x1000>; 1026 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 1027 status = "disabled"; 1028 }; 1029 1030 gpio0: gpio@2300000 { 1031 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; 1032 reg = <0x0 0x2300000 0x0 0x10000>; 1033 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1034 gpio-controller; 1035 little-endian; 1036 #gpio-cells = <2>; 1037 interrupt-controller; 1038 #interrupt-cells = <2>; 1039 }; 1040 1041 gpio1: gpio@2310000 { 1042 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; 1043 reg = <0x0 0x2310000 0x0 0x10000>; 1044 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1045 gpio-controller; 1046 little-endian; 1047 #gpio-cells = <2>; 1048 interrupt-controller; 1049 #interrupt-cells = <2>; 1050 }; 1051 1052 gpio2: gpio@2320000 { 1053 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; 1054 reg = <0x0 0x2320000 0x0 0x10000>; 1055 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1056 gpio-controller; 1057 little-endian; 1058 #gpio-cells = <2>; 1059 interrupt-controller; 1060 #interrupt-cells = <2>; 1061 }; 1062 1063 gpio3: gpio@2330000 { 1064 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; 1065 reg = <0x0 0x2330000 0x0 0x10000>; 1066 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1067 gpio-controller; 1068 little-endian; 1069 #gpio-cells = <2>; 1070 interrupt-controller; 1071 #interrupt-cells = <2>; 1072 }; 1073 1074 watchdog@23a0000 { 1075 compatible = "arm,sbsa-gwdt"; 1076 reg = <0x0 0x23a0000 0 0x1000>, 1077 <0x0 0x2390000 0 0x1000>; 1078 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1079 timeout-sec = <30>; 1080 }; 1081 1082 rcpm: wakeup-controller@1e34040 { 1083 compatible = "fsl,lx2160a-rcpm", "fsl,qoriq-rcpm-2.1+"; 1084 reg = <0x0 0x1e34040 0x0 0x1c>; 1085 #fsl,rcpm-wakeup-cells = <7>; 1086 little-endian; 1087 }; 1088 1089 ftm_alarm0: rtc@2800000 { 1090 compatible = "fsl,lx2160a-ftm-alarm"; 1091 reg = <0x0 0x2800000 0x0 0x10000>; 1092 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>; 1093 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1094 }; 1095 1096 usb0: usb@3100000 { 1097 compatible = "fsl,lx2160a-dwc3", "fsl,ls1028a-dwc3"; 1098 reg = <0x0 0x3100000 0x0 0x10000>; 1099 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1100 dr_mode = "host"; 1101 snps,quirk-frame-length-adjustment = <0x20>; 1102 usb3-lpm-capable; 1103 iommus = <&smmu 1>; 1104 dma-coherent; 1105 snps,dis_rxdet_inp3_quirk; 1106 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 1107 status = "disabled"; 1108 }; 1109 1110 usb1: usb@3110000 { 1111 compatible = "fsl,lx2160a-dwc3", "fsl,ls1028a-dwc3"; 1112 reg = <0x0 0x3110000 0x0 0x10000>; 1113 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1114 dr_mode = "host"; 1115 snps,quirk-frame-length-adjustment = <0x20>; 1116 usb3-lpm-capable; 1117 iommus = <&smmu 2>; 1118 dma-coherent; 1119 snps,dis_rxdet_inp3_quirk; 1120 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 1121 status = "disabled"; 1122 }; 1123 1124 sata0: sata@3200000 { 1125 compatible = "fsl,lx2160a-ahci"; 1126 reg = <0x0 0x3200000 0x0 0x10000>, 1127 <0x7 0x100520 0x0 0x4>; 1128 reg-names = "ahci", "sata-ecc"; 1129 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 1130 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1131 QORIQ_CLK_PLL_DIV(4)>; 1132 dma-coherent; 1133 status = "disabled"; 1134 }; 1135 1136 sata1: sata@3210000 { 1137 compatible = "fsl,lx2160a-ahci"; 1138 reg = <0x0 0x3210000 0x0 0x10000>, 1139 <0x7 0x100520 0x0 0x4>; 1140 reg-names = "ahci", "sata-ecc"; 1141 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1142 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1143 QORIQ_CLK_PLL_DIV(4)>; 1144 dma-coherent; 1145 status = "disabled"; 1146 }; 1147 1148 sata2: sata@3220000 { 1149 compatible = "fsl,lx2160a-ahci"; 1150 reg = <0x0 0x3220000 0x0 0x10000>, 1151 <0x7 0x100520 0x0 0x4>; 1152 reg-names = "ahci", "sata-ecc"; 1153 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1154 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1155 QORIQ_CLK_PLL_DIV(4)>; 1156 dma-coherent; 1157 status = "disabled"; 1158 }; 1159 1160 sata3: sata@3230000 { 1161 compatible = "fsl,lx2160a-ahci"; 1162 reg = <0x0 0x3230000 0x0 0x10000>, 1163 <0x7 0x100520 0x0 0x4>; 1164 reg-names = "ahci", "sata-ecc"; 1165 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 1166 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1167 QORIQ_CLK_PLL_DIV(4)>; 1168 dma-coherent; 1169 status = "disabled"; 1170 }; 1171 1172 pcie1: pcie@3400000 { 1173 compatible = "fsl,lx2160a-pcie"; 1174 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ 1175 <0x80 0x00000000 0x0 0x00002000>; /* configuration space */ 1176 reg-names = "csr_axi_slave", "config_axi_slave"; 1177 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1178 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1179 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1180 interrupt-names = "aer", "pme", "intr"; 1181 #address-cells = <3>; 1182 #size-cells = <2>; 1183 device_type = "pci"; 1184 dma-coherent; 1185 apio-wins = <8>; 1186 ppio-wins = <8>; 1187 bus-range = <0x0 0xff>; 1188 ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1189 msi-parent = <&its 0>; 1190 #interrupt-cells = <1>; 1191 interrupt-map-mask = <0 0 0 7>; 1192 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1193 <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1194 <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1195 <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1196 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 1197 status = "disabled"; 1198 }; 1199 1200 pcie2: pcie@3500000 { 1201 compatible = "fsl,lx2160a-pcie"; 1202 reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ 1203 <0x88 0x00000000 0x0 0x00002000>; /* configuration space */ 1204 reg-names = "csr_axi_slave", "config_axi_slave"; 1205 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1206 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1207 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1208 interrupt-names = "aer", "pme", "intr"; 1209 #address-cells = <3>; 1210 #size-cells = <2>; 1211 device_type = "pci"; 1212 dma-coherent; 1213 apio-wins = <8>; 1214 ppio-wins = <8>; 1215 bus-range = <0x0 0xff>; 1216 ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1217 msi-parent = <&its 0>; 1218 #interrupt-cells = <1>; 1219 interrupt-map-mask = <0 0 0 7>; 1220 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1221 <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1222 <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1223 <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 1224 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 1225 status = "disabled"; 1226 }; 1227 1228 pcie3: pcie@3600000 { 1229 compatible = "fsl,lx2160a-pcie"; 1230 reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */ 1231 <0x90 0x00000000 0x0 0x00002000>; /* configuration space */ 1232 reg-names = "csr_axi_slave", "config_axi_slave"; 1233 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1234 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1235 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1236 interrupt-names = "aer", "pme", "intr"; 1237 #address-cells = <3>; 1238 #size-cells = <2>; 1239 device_type = "pci"; 1240 dma-coherent; 1241 apio-wins = <256>; 1242 ppio-wins = <24>; 1243 bus-range = <0x0 0xff>; 1244 ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1245 msi-parent = <&its 0>; 1246 #interrupt-cells = <1>; 1247 interrupt-map-mask = <0 0 0 7>; 1248 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1249 <0000 0 0 2 &gic 0 0 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1250 <0000 0 0 3 &gic 0 0 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1251 <0000 0 0 4 &gic 0 0 GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1252 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 1253 status = "disabled"; 1254 }; 1255 1256 pcie4: pcie@3700000 { 1257 compatible = "fsl,lx2160a-pcie"; 1258 reg = <0x00 0x03700000 0x0 0x00100000>, /* controller registers */ 1259 <0x98 0x00000000 0x0 0x00002000>; /* configuration space */ 1260 reg-names = "csr_axi_slave", "config_axi_slave"; 1261 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1262 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1263 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1264 interrupt-names = "aer", "pme", "intr"; 1265 #address-cells = <3>; 1266 #size-cells = <2>; 1267 device_type = "pci"; 1268 dma-coherent; 1269 apio-wins = <8>; 1270 ppio-wins = <8>; 1271 bus-range = <0x0 0xff>; 1272 ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1273 msi-parent = <&its 0>; 1274 #interrupt-cells = <1>; 1275 interrupt-map-mask = <0 0 0 7>; 1276 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1277 <0000 0 0 2 &gic 0 0 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1278 <0000 0 0 3 &gic 0 0 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1279 <0000 0 0 4 &gic 0 0 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1280 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 1281 status = "disabled"; 1282 }; 1283 1284 pcie5: pcie@3800000 { 1285 compatible = "fsl,lx2160a-pcie"; 1286 reg = <0x00 0x03800000 0x0 0x00100000>, /* controller registers */ 1287 <0xa0 0x00000000 0x0 0x00002000>; /* configuration space */ 1288 reg-names = "csr_axi_slave", "config_axi_slave"; 1289 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1290 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1291 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1292 interrupt-names = "aer", "pme", "intr"; 1293 #address-cells = <3>; 1294 #size-cells = <2>; 1295 device_type = "pci"; 1296 dma-coherent; 1297 apio-wins = <256>; 1298 ppio-wins = <24>; 1299 bus-range = <0x0 0xff>; 1300 ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1301 msi-parent = <&its 0>; 1302 #interrupt-cells = <1>; 1303 interrupt-map-mask = <0 0 0 7>; 1304 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 1305 <0000 0 0 2 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1306 <0000 0 0 3 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1307 <0000 0 0 4 &gic 0 0 GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 1308 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 1309 status = "disabled"; 1310 }; 1311 1312 pcie6: pcie@3900000 { 1313 compatible = "fsl,lx2160a-pcie"; 1314 reg = <0x00 0x03900000 0x0 0x00100000>, /* controller registers */ 1315 <0xa8 0x00000000 0x0 0x00002000>; /* configuration space */ 1316 reg-names = "csr_axi_slave", "config_axi_slave"; 1317 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1318 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1319 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1320 interrupt-names = "aer", "pme", "intr"; 1321 #address-cells = <3>; 1322 #size-cells = <2>; 1323 device_type = "pci"; 1324 dma-coherent; 1325 apio-wins = <8>; 1326 ppio-wins = <8>; 1327 bus-range = <0x0 0xff>; 1328 ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1329 msi-parent = <&its 0>; 1330 #interrupt-cells = <1>; 1331 interrupt-map-mask = <0 0 0 7>; 1332 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1333 <0000 0 0 2 &gic 0 0 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1334 <0000 0 0 3 &gic 0 0 GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1335 <0000 0 0 4 &gic 0 0 GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1336 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 1337 status = "disabled"; 1338 }; 1339 1340 smmu: iommu@5000000 { 1341 compatible = "arm,mmu-500"; 1342 reg = <0 0x5000000 0 0x800000>; 1343 #iommu-cells = <1>; 1344 #global-interrupts = <14>; 1345 // global secure fault 1346 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 1347 // combined secure 1348 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1349 // global non-secure fault 1350 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 1351 // combined non-secure 1352 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1353 // performance counter interrupts 0-9 1354 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 1355 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 1356 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 1357 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 1358 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 1359 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 1360 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 1361 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 1362 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 1363 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 1364 // per context interrupt, 64 interrupts 1365 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1366 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1367 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1368 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1369 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 1370 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 1371 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 1372 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 1373 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 1374 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1375 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 1376 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 1377 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 1378 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 1379 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 1380 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 1381 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 1382 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1383 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 1384 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 1385 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 1386 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 1387 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 1388 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 1389 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1390 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 1391 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, 1392 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 1393 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 1394 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 1395 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1396 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 1397 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 1398 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 1399 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 1400 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1401 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 1402 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 1403 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 1404 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 1405 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1406 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1407 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1408 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1409 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 1410 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 1411 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 1412 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 1413 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, 1414 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 1415 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 1416 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 1417 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 1418 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 1419 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 1420 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 1421 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 1422 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 1423 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 1424 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 1425 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 1426 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 1427 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 1428 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 1429 dma-coherent; 1430 }; 1431 1432 console@8340020 { 1433 compatible = "fsl,dpaa2-console"; 1434 reg = <0x00000000 0x08340020 0 0x2>; 1435 }; 1436 1437 ptp-timer@8b95000 { 1438 compatible = "fsl,dpaa2-ptp"; 1439 reg = <0x0 0x8b95000 0x0 0x100>; 1440 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1441 QORIQ_CLK_PLL_DIV(2)>; 1442 little-endian; 1443 fsl,extts-fifo; 1444 }; 1445 1446 /* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */ 1447 emdio1: mdio@8b96000 { 1448 compatible = "fsl,fman-memac-mdio"; 1449 reg = <0x0 0x8b96000 0x0 0x1000>; 1450 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 1451 #address-cells = <1>; 1452 #size-cells = <0>; 1453 little-endian; 1454 clock-frequency = <2500000>; 1455 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1456 QORIQ_CLK_PLL_DIV(2)>; 1457 status = "disabled"; 1458 }; 1459 1460 emdio2: mdio@8b97000 { 1461 compatible = "fsl,fman-memac-mdio"; 1462 reg = <0x0 0x8b97000 0x0 0x1000>; 1463 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1464 little-endian; 1465 #address-cells = <1>; 1466 #size-cells = <0>; 1467 clock-frequency = <2500000>; 1468 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1469 QORIQ_CLK_PLL_DIV(2)>; 1470 status = "disabled"; 1471 }; 1472 1473 pcs_mdio1: mdio@8c07000 { 1474 compatible = "fsl,fman-memac-mdio"; 1475 reg = <0x0 0x8c07000 0x0 0x1000>; 1476 little-endian; 1477 #address-cells = <1>; 1478 #size-cells = <0>; 1479 status = "disabled"; 1480 1481 pcs1: ethernet-phy@0 { 1482 reg = <0>; 1483 }; 1484 }; 1485 1486 pcs_mdio2: mdio@8c0b000 { 1487 compatible = "fsl,fman-memac-mdio"; 1488 reg = <0x0 0x8c0b000 0x0 0x1000>; 1489 little-endian; 1490 #address-cells = <1>; 1491 #size-cells = <0>; 1492 status = "disabled"; 1493 1494 pcs2: ethernet-phy@0 { 1495 reg = <0>; 1496 }; 1497 }; 1498 1499 pcs_mdio3: mdio@8c0f000 { 1500 compatible = "fsl,fman-memac-mdio"; 1501 reg = <0x0 0x8c0f000 0x0 0x1000>; 1502 little-endian; 1503 #address-cells = <1>; 1504 #size-cells = <0>; 1505 status = "disabled"; 1506 1507 pcs3: ethernet-phy@0 { 1508 reg = <0>; 1509 }; 1510 }; 1511 1512 pcs_mdio4: mdio@8c13000 { 1513 compatible = "fsl,fman-memac-mdio"; 1514 reg = <0x0 0x8c13000 0x0 0x1000>; 1515 little-endian; 1516 #address-cells = <1>; 1517 #size-cells = <0>; 1518 status = "disabled"; 1519 1520 pcs4: ethernet-phy@0 { 1521 reg = <0>; 1522 }; 1523 }; 1524 1525 pcs_mdio5: mdio@8c17000 { 1526 compatible = "fsl,fman-memac-mdio"; 1527 reg = <0x0 0x8c17000 0x0 0x1000>; 1528 little-endian; 1529 #address-cells = <1>; 1530 #size-cells = <0>; 1531 status = "disabled"; 1532 1533 pcs5: ethernet-phy@0 { 1534 reg = <0>; 1535 }; 1536 }; 1537 1538 pcs_mdio6: mdio@8c1b000 { 1539 compatible = "fsl,fman-memac-mdio"; 1540 reg = <0x0 0x8c1b000 0x0 0x1000>; 1541 little-endian; 1542 #address-cells = <1>; 1543 #size-cells = <0>; 1544 status = "disabled"; 1545 1546 pcs6: ethernet-phy@0 { 1547 reg = <0>; 1548 }; 1549 }; 1550 1551 pcs_mdio7: mdio@8c1f000 { 1552 compatible = "fsl,fman-memac-mdio"; 1553 reg = <0x0 0x8c1f000 0x0 0x1000>; 1554 little-endian; 1555 #address-cells = <1>; 1556 #size-cells = <0>; 1557 status = "disabled"; 1558 1559 pcs7: ethernet-phy@0 { 1560 reg = <0>; 1561 }; 1562 }; 1563 1564 pcs_mdio8: mdio@8c23000 { 1565 compatible = "fsl,fman-memac-mdio"; 1566 reg = <0x0 0x8c23000 0x0 0x1000>; 1567 little-endian; 1568 #address-cells = <1>; 1569 #size-cells = <0>; 1570 status = "disabled"; 1571 1572 pcs8: ethernet-phy@0 { 1573 reg = <0>; 1574 }; 1575 }; 1576 1577 pcs_mdio9: mdio@8c27000 { 1578 compatible = "fsl,fman-memac-mdio"; 1579 reg = <0x0 0x8c27000 0x0 0x1000>; 1580 little-endian; 1581 #address-cells = <1>; 1582 #size-cells = <0>; 1583 status = "disabled"; 1584 1585 pcs9: ethernet-phy@0 { 1586 reg = <0>; 1587 }; 1588 }; 1589 1590 pcs_mdio10: mdio@8c2b000 { 1591 compatible = "fsl,fman-memac-mdio"; 1592 reg = <0x0 0x8c2b000 0x0 0x1000>; 1593 little-endian; 1594 #address-cells = <1>; 1595 #size-cells = <0>; 1596 status = "disabled"; 1597 1598 pcs10: ethernet-phy@0 { 1599 reg = <0>; 1600 }; 1601 }; 1602 1603 pcs_mdio11: mdio@8c2f000 { 1604 compatible = "fsl,fman-memac-mdio"; 1605 reg = <0x0 0x8c2f000 0x0 0x1000>; 1606 little-endian; 1607 #address-cells = <1>; 1608 #size-cells = <0>; 1609 status = "disabled"; 1610 1611 pcs11: ethernet-phy@0 { 1612 reg = <0>; 1613 }; 1614 }; 1615 1616 pcs_mdio12: mdio@8c33000 { 1617 compatible = "fsl,fman-memac-mdio"; 1618 reg = <0x0 0x8c33000 0x0 0x1000>; 1619 little-endian; 1620 #address-cells = <1>; 1621 #size-cells = <0>; 1622 status = "disabled"; 1623 1624 pcs12: ethernet-phy@0 { 1625 reg = <0>; 1626 }; 1627 }; 1628 1629 pcs_mdio13: mdio@8c37000 { 1630 compatible = "fsl,fman-memac-mdio"; 1631 reg = <0x0 0x8c37000 0x0 0x1000>; 1632 little-endian; 1633 #address-cells = <1>; 1634 #size-cells = <0>; 1635 status = "disabled"; 1636 1637 pcs13: ethernet-phy@0 { 1638 reg = <0>; 1639 }; 1640 }; 1641 1642 pcs_mdio14: mdio@8c3b000 { 1643 compatible = "fsl,fman-memac-mdio"; 1644 reg = <0x0 0x8c3b000 0x0 0x1000>; 1645 little-endian; 1646 #address-cells = <1>; 1647 #size-cells = <0>; 1648 status = "disabled"; 1649 1650 pcs14: ethernet-phy@0 { 1651 reg = <0>; 1652 }; 1653 }; 1654 1655 pcs_mdio15: mdio@8c3f000 { 1656 compatible = "fsl,fman-memac-mdio"; 1657 reg = <0x0 0x8c3f000 0x0 0x1000>; 1658 little-endian; 1659 #address-cells = <1>; 1660 #size-cells = <0>; 1661 status = "disabled"; 1662 1663 pcs15: ethernet-phy@0 { 1664 reg = <0>; 1665 }; 1666 }; 1667 1668 pcs_mdio16: mdio@8c43000 { 1669 compatible = "fsl,fman-memac-mdio"; 1670 reg = <0x0 0x8c43000 0x0 0x1000>; 1671 little-endian; 1672 #address-cells = <1>; 1673 #size-cells = <0>; 1674 status = "disabled"; 1675 1676 pcs16: ethernet-phy@0 { 1677 reg = <0>; 1678 }; 1679 }; 1680 1681 pcs_mdio17: mdio@8c47000 { 1682 compatible = "fsl,fman-memac-mdio"; 1683 reg = <0x0 0x8c47000 0x0 0x1000>; 1684 little-endian; 1685 #address-cells = <1>; 1686 #size-cells = <0>; 1687 status = "disabled"; 1688 1689 pcs17: ethernet-phy@0 { 1690 reg = <0>; 1691 }; 1692 }; 1693 1694 pcs_mdio18: mdio@8c4b000 { 1695 compatible = "fsl,fman-memac-mdio"; 1696 reg = <0x0 0x8c4b000 0x0 0x1000>; 1697 little-endian; 1698 #address-cells = <1>; 1699 #size-cells = <0>; 1700 status = "disabled"; 1701 1702 pcs18: ethernet-phy@0 { 1703 reg = <0>; 1704 }; 1705 }; 1706 1707 pinmux_i2crv: pinmux@70010012c { 1708 compatible = "pinctrl-single"; 1709 reg = <0x00000007 0x0010012c 0x0 0xc>; 1710 #address-cells = <1>; 1711 #size-cells = <0>; 1712 pinctrl-single,bit-per-mux; 1713 pinctrl-single,register-width = <32>; 1714 pinctrl-single,function-mask = <0x7>; 1715 1716 i2c1_scl: i2c1-scl-pins { 1717 pinctrl-single,bits = <0x0 0 0x7>; 1718 }; 1719 1720 i2c1_scl_gpio: i2c1-scl-gpio-pins { 1721 pinctrl-single,bits = <0x0 0x1 0x7>; 1722 }; 1723 1724 i2c2_scl: i2c2-scl-pins { 1725 pinctrl-single,bits = <0x0 0 (0x7 << 3)>; 1726 }; 1727 1728 i2c2_scl_gpio: i2c2-scl-gpio-pins { 1729 pinctrl-single,bits = <0x0 (0x1 << 3) (0x7 << 3)>; 1730 }; 1731 1732 i2c3_scl: i2c3-scl-pins { 1733 pinctrl-single,bits = <0x0 0 (0x7 << 6)>; 1734 }; 1735 1736 i2c3_scl_gpio: i2c3-scl-gpio-pins { 1737 pinctrl-single,bits = <0x0 (0x1 << 6) (0x7 << 6)>; 1738 }; 1739 1740 i2c4_scl: i2c4-scl-pins { 1741 pinctrl-single,bits = <0x0 0 (0x7 << 9)>; 1742 }; 1743 1744 i2c4_scl_gpio: i2c4-scl-gpio-pins { 1745 pinctrl-single,bits = <0x0 (0x1 << 9) (0x7 << 9)>; 1746 }; 1747 1748 i2c5_scl: i2c5-scl-pins { 1749 pinctrl-single,bits = <0x0 0 (0x7 << 12)>; 1750 }; 1751 1752 i2c5_scl_gpio: i2c5-scl-gpio-pins { 1753 pinctrl-single,bits = <0x0 (0x1 << 12) (0x7 << 12)>; 1754 }; 1755 1756 i2c6_scl: i2c6-scl-pins { 1757 pinctrl-single,bits = <0x4 0x2 0x7>; 1758 }; 1759 1760 i2c6_scl_gpio: i2c6-scl-gpio-pins { 1761 pinctrl-single,bits = <0x4 0x1 0x7>; 1762 }; 1763 1764 i2c7_scl: i2c7-scl-pins { 1765 pinctrl-single,bits = <0x4 0x2 0x7>; 1766 }; 1767 1768 i2c7_scl_gpio: i2c7-scl-gpio-pins { 1769 pinctrl-single,bits = <0x4 0x1 0x7>; 1770 }; 1771 1772 i2c0_scl: i2c0-scl-pins { 1773 pinctrl-single,bits = <0x8 0 (0x7 << 10)>; 1774 }; 1775 1776 i2c0_scl_gpio: i2c0-scl-gpio-pins { 1777 pinctrl-single,bits = <0x8 (0x1 << 10) (0x7 << 10)>; 1778 }; 1779 }; 1780 1781 fsl_mc: fsl-mc@80c000000 { 1782 compatible = "fsl,qoriq-mc"; 1783 reg = <0x00000008 0x0c000000 0 0x40>, 1784 <0x00000000 0x08340000 0 0x40000>; 1785 msi-parent = <&its 0>; 1786 /* iommu-map property is fixed up by u-boot */ 1787 iommu-map = <0 &smmu 0 0>; 1788 dma-coherent; 1789 #address-cells = <3>; 1790 #size-cells = <1>; 1791 1792 /* 1793 * Region type 0x0 - MC portals 1794 * Region type 0x1 - QBMAN portals 1795 */ 1796 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 1797 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; 1798 1799 /* 1800 * Define the maximum number of MACs present on the SoC. 1801 */ 1802 dpmacs { 1803 #address-cells = <1>; 1804 #size-cells = <0>; 1805 1806 dpmac1: ethernet@1 { 1807 compatible = "fsl,qoriq-mc-dpmac"; 1808 reg = <0x1>; 1809 pcs-handle = <&pcs1>; 1810 }; 1811 1812 dpmac2: ethernet@2 { 1813 compatible = "fsl,qoriq-mc-dpmac"; 1814 reg = <0x2>; 1815 pcs-handle = <&pcs2>; 1816 }; 1817 1818 dpmac3: ethernet@3 { 1819 compatible = "fsl,qoriq-mc-dpmac"; 1820 reg = <0x3>; 1821 pcs-handle = <&pcs3>; 1822 }; 1823 1824 dpmac4: ethernet@4 { 1825 compatible = "fsl,qoriq-mc-dpmac"; 1826 reg = <0x4>; 1827 pcs-handle = <&pcs4>; 1828 }; 1829 1830 dpmac5: ethernet@5 { 1831 compatible = "fsl,qoriq-mc-dpmac"; 1832 reg = <0x5>; 1833 pcs-handle = <&pcs5>; 1834 }; 1835 1836 dpmac6: ethernet@6 { 1837 compatible = "fsl,qoriq-mc-dpmac"; 1838 reg = <0x6>; 1839 pcs-handle = <&pcs6>; 1840 }; 1841 1842 dpmac7: ethernet@7 { 1843 compatible = "fsl,qoriq-mc-dpmac"; 1844 reg = <0x7>; 1845 pcs-handle = <&pcs7>; 1846 }; 1847 1848 dpmac8: ethernet@8 { 1849 compatible = "fsl,qoriq-mc-dpmac"; 1850 reg = <0x8>; 1851 pcs-handle = <&pcs8>; 1852 }; 1853 1854 dpmac9: ethernet@9 { 1855 compatible = "fsl,qoriq-mc-dpmac"; 1856 reg = <0x9>; 1857 pcs-handle = <&pcs9>; 1858 }; 1859 1860 dpmac10: ethernet@a { 1861 compatible = "fsl,qoriq-mc-dpmac"; 1862 reg = <0xa>; 1863 pcs-handle = <&pcs10>; 1864 }; 1865 1866 dpmac11: ethernet@b { 1867 compatible = "fsl,qoriq-mc-dpmac"; 1868 reg = <0xb>; 1869 pcs-handle = <&pcs11>; 1870 }; 1871 1872 dpmac12: ethernet@c { 1873 compatible = "fsl,qoriq-mc-dpmac"; 1874 reg = <0xc>; 1875 pcs-handle = <&pcs12>; 1876 }; 1877 1878 dpmac13: ethernet@d { 1879 compatible = "fsl,qoriq-mc-dpmac"; 1880 reg = <0xd>; 1881 pcs-handle = <&pcs13>; 1882 }; 1883 1884 dpmac14: ethernet@e { 1885 compatible = "fsl,qoriq-mc-dpmac"; 1886 reg = <0xe>; 1887 pcs-handle = <&pcs14>; 1888 }; 1889 1890 dpmac15: ethernet@f { 1891 compatible = "fsl,qoriq-mc-dpmac"; 1892 reg = <0xf>; 1893 pcs-handle = <&pcs15>; 1894 }; 1895 1896 dpmac16: ethernet@10 { 1897 compatible = "fsl,qoriq-mc-dpmac"; 1898 reg = <0x10>; 1899 pcs-handle = <&pcs16>; 1900 }; 1901 1902 dpmac17: ethernet@11 { 1903 compatible = "fsl,qoriq-mc-dpmac"; 1904 reg = <0x11>; 1905 pcs-handle = <&pcs17>; 1906 }; 1907 1908 dpmac18: ethernet@12 { 1909 compatible = "fsl,qoriq-mc-dpmac"; 1910 reg = <0x12>; 1911 pcs-handle = <&pcs18>; 1912 }; 1913 }; 1914 }; 1915 }; 1916 1917 firmware { 1918 optee: optee { 1919 compatible = "linaro,optee-tz"; 1920 method = "smc"; 1921 status = "disabled"; 1922 }; 1923 }; 1924};
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