fsl-ls1088a.dtsi

   1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2/*
   3 * Device Tree Include file for NXP Layerscape-1088A family SoC.
   4 *
   5 * Copyright 2017-2020 NXP
   6 *
   7 * Harninder Rai <harninder.rai@nxp.com>
   8 *
   9 */
  10#include <dt-bindings/clock/fsl,qoriq-clockgen.h>
  11#include <dt-bindings/interrupt-controller/arm-gic.h>
  12#include <dt-bindings/thermal/thermal.h>
  13
  14/ {
  15	compatible = "fsl,ls1088a";
  16	interrupt-parent = <&gic>;
  17	#address-cells = <2>;
  18	#size-cells = <2>;
  19
  20	aliases {
  21		crypto = &crypto;
  22		rtc1 = &ftm_alarm0;
  23	};
  24
  25	cpus {
  26		#address-cells = <1>;
  27		#size-cells = <0>;
  28
  29		/* We have 2 clusters having 4 Cortex-A53 cores each */
  30		cpu0: cpu@0 {
  31			device_type = "cpu";
  32			compatible = "arm,cortex-a53";
  33			reg = <0x0>;
  34			clocks = <&clockgen QORIQ_CLK_CMUX 0>;
  35			cpu-idle-states = <&CPU_PH20>;
  36			#cooling-cells = <2>;
  37		};
  38
  39		cpu1: cpu@1 {
  40			device_type = "cpu";
  41			compatible = "arm,cortex-a53";
  42			reg = <0x1>;
  43			clocks = <&clockgen QORIQ_CLK_CMUX 0>;
  44			cpu-idle-states = <&CPU_PH20>;
  45			#cooling-cells = <2>;
  46		};
  47
  48		cpu2: cpu@2 {
  49			device_type = "cpu";
  50			compatible = "arm,cortex-a53";
  51			reg = <0x2>;
  52			clocks = <&clockgen QORIQ_CLK_CMUX 0>;
  53			cpu-idle-states = <&CPU_PH20>;
  54			#cooling-cells = <2>;
  55		};
  56
  57		cpu3: cpu@3 {
  58			device_type = "cpu";
  59			compatible = "arm,cortex-a53";
  60			reg = <0x3>;
  61			clocks = <&clockgen QORIQ_CLK_CMUX 0>;
  62			cpu-idle-states = <&CPU_PH20>;
  63			#cooling-cells = <2>;
  64		};
  65
  66		cpu4: cpu@100 {
  67			device_type = "cpu";
  68			compatible = "arm,cortex-a53";
  69			reg = <0x100>;
  70			clocks = <&clockgen QORIQ_CLK_CMUX 1>;
  71			cpu-idle-states = <&CPU_PH20>;
  72			#cooling-cells = <2>;
  73		};
  74
  75		cpu5: cpu@101 {
  76			device_type = "cpu";
  77			compatible = "arm,cortex-a53";
  78			reg = <0x101>;
  79			clocks = <&clockgen QORIQ_CLK_CMUX 1>;
  80			cpu-idle-states = <&CPU_PH20>;
  81			#cooling-cells = <2>;
  82		};
  83
  84		cpu6: cpu@102 {
  85			device_type = "cpu";
  86			compatible = "arm,cortex-a53";
  87			reg = <0x102>;
  88			clocks = <&clockgen QORIQ_CLK_CMUX 1>;
  89			cpu-idle-states = <&CPU_PH20>;
  90			#cooling-cells = <2>;
  91		};
  92
  93		cpu7: cpu@103 {
  94			device_type = "cpu";
  95			compatible = "arm,cortex-a53";
  96			reg = <0x103>;
  97			clocks = <&clockgen QORIQ_CLK_CMUX 1>;
  98			cpu-idle-states = <&CPU_PH20>;
  99			#cooling-cells = <2>;
 100		};
 101
 102		CPU_PH20: cpu-ph20 {
 103			compatible = "arm,idle-state";
 104			idle-state-name = "PH20";
 105			arm,psci-suspend-param = <0x0>;
 106			entry-latency-us = <1000>;
 107			exit-latency-us = <1000>;
 108			min-residency-us = <3000>;
 109		};
 110	};
 111
 112	gic: interrupt-controller@6000000 {
 113		compatible = "arm,gic-v3";
 114		#interrupt-cells = <3>;
 115		interrupt-controller;
 116		reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
 117		      <0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/
 118		      <0x0 0x0c0c0000 0 0x2000>, /* GICC */
 119		      <0x0 0x0c0d0000 0 0x1000>, /* GICH */
 120		      <0x0 0x0c0e0000 0 0x20000>; /* GICV */
 121		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 122		#address-cells = <2>;
 123		#size-cells = <2>;
 124		ranges;
 125
 126		its: msi-controller@6020000 {
 127			compatible = "arm,gic-v3-its";
 128			msi-controller;
 129			#msi-cells = <1>;
 130			reg = <0x0 0x6020000 0 0x20000>;
 131		};
 132	};
 133
 134	thermal-zones {
 135		cluster-thermal {
 136			polling-delay-passive = <1000>;
 137			polling-delay = <5000>;
 138			thermal-sensors = <&tmu 0>;
 139
 140			trips {
 141				core_cluster_alert: core-cluster-alert {
 142					temperature = <85000>;
 143					hysteresis = <2000>;
 144					type = "passive";
 145				};
 146
 147				core-cluster-crit {
 148					temperature = <95000>;
 149					hysteresis = <2000>;
 150					type = "critical";
 151				};
 152			};
 153
 154			cooling-maps {
 155				map0 {
 156					trip = <&core_cluster_alert>;
 157					cooling-device =
 158						<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 159						<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 160						<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 161						<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 162						<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 163						<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 164						<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 165						<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 166				};
 167			};
 168		};
 169
 170		soc-thermal {
 171			polling-delay-passive = <1000>;
 172			polling-delay = <5000>;
 173			thermal-sensors = <&tmu 1>;
 174
 175			trips {
 176				soc-crit {
 177					temperature = <95000>;
 178					hysteresis = <2000>;
 179					type = "critical";
 180				};
 181			};
 182		};
 183	};
 184
 185	timer {
 186		compatible = "arm,armv8-timer";
 187		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
 188			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
 189			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
 190			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
 191	};
 192
 193	pmu {
 194		compatible = "arm,cortex-a53-pmu";
 195		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 196	};
 197
 198	psci {
 199		compatible = "arm,psci-0.2";
 200		method = "smc";
 201	};
 202
 203	sysclk: sysclk {
 204		compatible = "fixed-clock";
 205		#clock-cells = <0>;
 206		clock-frequency = <100000000>;
 207		clock-output-names = "sysclk";
 208	};
 209
 210	reboot {
 211		compatible = "syscon-reboot";
 212		regmap = <&reset>;
 213		offset = <0x0>;
 214		mask = <0x02>;
 215	};
 216
 217	soc {
 218		compatible = "simple-bus";
 219		#address-cells = <2>;
 220		#size-cells = <2>;
 221		ranges;
 222		dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
 223
 224		clockgen: clocking@1300000 {
 225			compatible = "fsl,ls1088a-clockgen";
 226			reg = <0 0x1300000 0 0xa0000>;
 227			#clock-cells = <2>;
 228			clocks = <&sysclk>;
 229		};
 230
 231		dcfg: dcfg@1e00000 {
 232			compatible = "fsl,ls1088a-dcfg", "syscon";
 233			reg = <0x0 0x1e00000 0x0 0x10000>;
 234			little-endian;
 235		};
 236
 237		reset: syscon@1e60000 {
 238			compatible = "fsl,ls1088a-reset", "syscon";
 239			reg = <0x0 0x1e60000 0x0 0x10000>;
 240		};
 241
 242		isc: syscon@1f70000 {
 243			compatible = "fsl,ls1088a-isc", "syscon";
 244			reg = <0x0 0x1f70000 0x0 0x10000>;
 245			little-endian;
 246			#address-cells = <1>;
 247			#size-cells = <1>;
 248			ranges = <0x0 0x0 0x1f70000 0x10000>;
 249
 250			extirq: interrupt-controller@14 {
 251				compatible = "fsl,ls1088a-extirq";
 252				#interrupt-cells = <2>;
 253				#address-cells = <0>;
 254				interrupt-controller;
 255				reg = <0x14 4>;
 256				interrupt-map =
 257					<0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 258					<1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 259					<2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 260					<3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 261					<4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 262					<5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 263					<6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
 264					<7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 265					<8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 266					<9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 267					<10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
 268					<11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 269				interrupt-map-mask = <0xf 0x0>;
 270			};
 271		};
 272
 273		sfp: efuse@1e80000 {
 274			compatible = "fsl,ls1028a-sfp";
 275			reg = <0x0 0x1e80000 0x0 0x10000>;
 276			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 277					    QORIQ_CLK_PLL_DIV(4)>;
 278			clock-names = "sfp";
 279		};
 280
 281		tmu: tmu@1f80000 {
 282			compatible = "fsl,qoriq-tmu";
 283			reg = <0x0 0x1f80000 0x0 0x10000>;
 284			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 285			fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>;
 286			fsl,tmu-calibration =
 287				/* Calibration data group 1 */
 288				<0x00000000 0x00000023>,
 289				<0x00000001 0x0000002a>,
 290				<0x00000002 0x00000030>,
 291				<0x00000003 0x00000037>,
 292				<0x00000004 0x0000003d>,
 293				<0x00000005 0x00000044>,
 294				<0x00000006 0x0000004a>,
 295				<0x00000007 0x00000051>,
 296				<0x00000008 0x00000057>,
 297				<0x00000009 0x0000005e>,
 298				<0x0000000a 0x00000064>,
 299				<0x0000000b 0x0000006b>,
 300				/* Calibration data group 2 */
 301				<0x00010000 0x00000022>,
 302				<0x00010001 0x0000002a>,
 303				<0x00010002 0x00000032>,
 304				<0x00010003 0x0000003a>,
 305				<0x00010004 0x00000042>,
 306				<0x00010005 0x0000004a>,
 307				<0x00010006 0x00000052>,
 308				<0x00010007 0x0000005a>,
 309				<0x00010008 0x00000062>,
 310				<0x00010009 0x0000006a>,
 311				/* Calibration data group 3 */
 312				<0x00020000 0x00000021>,
 313				<0x00020001 0x0000002b>,
 314				<0x00020002 0x00000035>,
 315				<0x00020003 0x00000040>,
 316				<0x00020004 0x0000004a>,
 317				<0x00020005 0x00000054>,
 318				<0x00020006 0x0000005e>,
 319				/* Calibration data group 4 */
 320				<0x00030000 0x00000010>,
 321				<0x00030001 0x0000001c>,
 322				<0x00030002 0x00000027>,
 323				<0x00030003 0x00000032>,
 324				<0x00030004 0x0000003e>,
 325				<0x00030005 0x00000049>,
 326				<0x00030006 0x00000054>,
 327				<0x00030007 0x00000060>;
 328			little-endian;
 329			#thermal-sensor-cells = <1>;
 330		};
 331
 332		dspi: spi@2100000 {
 333			compatible = "fsl,ls1088a-dspi",
 334				     "fsl,ls1021a-v1.0-dspi";
 335			#address-cells = <1>;
 336			#size-cells = <0>;
 337			reg = <0x0 0x2100000 0x0 0x10000>;
 338			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 339			clock-names = "dspi";
 340			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 341					    QORIQ_CLK_PLL_DIV(2)>;
 342			spi-num-chipselects = <6>;
 343			status = "disabled";
 344		};
 345
 346		duart0: serial@21c0500 {
 347			compatible = "fsl,ns16550", "ns16550a";
 348			reg = <0x0 0x21c0500 0x0 0x100>;
 349			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 350					    QORIQ_CLK_PLL_DIV(4)>;
 351			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 352			status = "disabled";
 353		};
 354
 355		duart1: serial@21c0600 {
 356			compatible = "fsl,ns16550", "ns16550a";
 357			reg = <0x0 0x21c0600 0x0 0x100>;
 358			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 359					    QORIQ_CLK_PLL_DIV(4)>;
 360			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 361			status = "disabled";
 362		};
 363
 364		gpio0: gpio@2300000 {
 365			compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
 366			reg = <0x0 0x2300000 0x0 0x10000>;
 367			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 368			little-endian;
 369			gpio-controller;
 370			#gpio-cells = <2>;
 371			interrupt-controller;
 372			#interrupt-cells = <2>;
 373		};
 374
 375		gpio1: gpio@2310000 {
 376			compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
 377			reg = <0x0 0x2310000 0x0 0x10000>;
 378			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 379			little-endian;
 380			gpio-controller;
 381			#gpio-cells = <2>;
 382			interrupt-controller;
 383			#interrupt-cells = <2>;
 384		};
 385
 386		gpio2: gpio@2320000 {
 387			compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
 388			reg = <0x0 0x2320000 0x0 0x10000>;
 389			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 390			little-endian;
 391			gpio-controller;
 392			#gpio-cells = <2>;
 393			interrupt-controller;
 394			#interrupt-cells = <2>;
 395		};
 396
 397		gpio3: gpio@2330000 {
 398			compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
 399			reg = <0x0 0x2330000 0x0 0x10000>;
 400			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 401			little-endian;
 402			gpio-controller;
 403			#gpio-cells = <2>;
 404			interrupt-controller;
 405			#interrupt-cells = <2>;
 406		};
 407
 408		ifc: memory-controller@2240000 {
 409			compatible = "fsl,ifc";
 410			reg = <0x0 0x2240000 0x0 0x20000>;
 411			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 412			little-endian;
 413			#address-cells = <2>;
 414			#size-cells = <1>;
 415			status = "disabled";
 416		};
 417
 418		i2c0: i2c@2000000 {
 419			compatible = "fsl,vf610-i2c";
 420			#address-cells = <1>;
 421			#size-cells = <0>;
 422			reg = <0x0 0x2000000 0x0 0x10000>;
 423			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 424			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 425					    QORIQ_CLK_PLL_DIV(8)>;
 426			status = "disabled";
 427		};
 428
 429		i2c1: i2c@2010000 {
 430			compatible = "fsl,vf610-i2c";
 431			#address-cells = <1>;
 432			#size-cells = <0>;
 433			reg = <0x0 0x2010000 0x0 0x10000>;
 434			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 435			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 436					    QORIQ_CLK_PLL_DIV(8)>;
 437			status = "disabled";
 438		};
 439
 440		i2c2: i2c@2020000 {
 441			compatible = "fsl,vf610-i2c";
 442			#address-cells = <1>;
 443			#size-cells = <0>;
 444			reg = <0x0 0x2020000 0x0 0x10000>;
 445			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 446			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 447					    QORIQ_CLK_PLL_DIV(8)>;
 448			status = "disabled";
 449		};
 450
 451		i2c3: i2c@2030000 {
 452			compatible = "fsl,vf610-i2c";
 453			#address-cells = <1>;
 454			#size-cells = <0>;
 455			reg = <0x0 0x2030000 0x0 0x10000>;
 456			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 457			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 458					    QORIQ_CLK_PLL_DIV(8)>;
 459			status = "disabled";
 460		};
 461
 462		qspi: spi@20c0000 {
 463			compatible = "fsl,ls2080a-qspi";
 464			#address-cells = <1>;
 465			#size-cells = <0>;
 466			reg = <0x0 0x20c0000 0x0 0x10000>,
 467			      <0x0 0x20000000 0x0 0x10000000>;
 468			reg-names = "QuadSPI", "QuadSPI-memory";
 469			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 470			clock-names = "qspi_en", "qspi";
 471			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 472					    QORIQ_CLK_PLL_DIV(4)>,
 473				 <&clockgen QORIQ_CLK_PLATFORM_PLL
 474					    QORIQ_CLK_PLL_DIV(4)>;
 475			status = "disabled";
 476		};
 477
 478		esdhc: mmc@2140000 {
 479			compatible = "fsl,ls1088a-esdhc", "fsl,esdhc";
 480			reg = <0x0 0x2140000 0x0 0x10000>;
 481			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 482			clock-frequency = <0>;
 483			clocks = <&clockgen QORIQ_CLK_HWACCEL 1>;
 484			voltage-ranges = <1800 1800 3300 3300>;
 485			sdhci,auto-cmd12;
 486			little-endian;
 487			bus-width = <4>;
 488			status = "disabled";
 489		};
 490
 491		usb0: usb@3100000 {
 492			compatible = "fsl,ls1088a-dwc3", "fsl,ls1028a-dwc3";
 493			reg = <0x0 0x3100000 0x0 0x10000>;
 494			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 495			dr_mode = "host";
 496			iommus = <&smmu 1>;
 497			dma-coherent;
 498			snps,quirk-frame-length-adjustment = <0x20>;
 499			snps,dis_rxdet_inp3_quirk;
 500			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
 501			status = "disabled";
 502		};
 503
 504		usb1: usb@3110000 {
 505			compatible = "fsl,ls1088a-dwc3", "fsl,ls1028a-dwc3";
 506			reg = <0x0 0x3110000 0x0 0x10000>;
 507			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 508			dr_mode = "host";
 509			iommus = <&smmu 2>;
 510			dma-coherent;
 511			snps,quirk-frame-length-adjustment = <0x20>;
 512			snps,dis_rxdet_inp3_quirk;
 513			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
 514			status = "disabled";
 515		};
 516
 517		sata: sata@3200000 {
 518			compatible = "fsl,ls1088a-ahci";
 519			reg = <0x0 0x3200000 0x0 0x10000>,
 520				<0x7 0x100520 0x0 0x4>;
 521			reg-names = "ahci", "sata-ecc";
 522			interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
 523			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 524					    QORIQ_CLK_PLL_DIV(4)>;
 525			dma-coherent;
 526			status = "disabled";
 527		};
 528
 529		crypto: crypto@8000000 {
 530			compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
 531			fsl,sec-era = <8>;
 532			#address-cells = <1>;
 533			#size-cells = <1>;
 534			ranges = <0x0 0x00 0x8000000 0x100000>;
 535			reg = <0x00 0x8000000 0x0 0x100000>;
 536			interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
 537			dma-coherent;
 538
 539			sec_jr0: jr@10000 {
 540				compatible = "fsl,sec-v5.0-job-ring",
 541					     "fsl,sec-v4.0-job-ring";
 542				reg = <0x10000 0x10000>;
 543				interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 544			};
 545
 546			sec_jr1: jr@20000 {
 547				compatible = "fsl,sec-v5.0-job-ring",
 548					     "fsl,sec-v4.0-job-ring";
 549				reg = <0x20000 0x10000>;
 550				interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
 551			};
 552
 553			sec_jr2: jr@30000 {
 554				compatible = "fsl,sec-v5.0-job-ring",
 555					     "fsl,sec-v4.0-job-ring";
 556				reg = <0x30000 0x10000>;
 557				interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
 558			};
 559
 560			sec_jr3: jr@40000 {
 561				compatible = "fsl,sec-v5.0-job-ring",
 562					     "fsl,sec-v4.0-job-ring";
 563				reg = <0x40000 0x10000>;
 564				interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 565			};
 566		};
 567
 568		pcie1: pcie@3400000 {
 569			compatible = "fsl,ls1088a-pcie";
 570			reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
 571			      <0x20 0x00000000 0x0 0x00002000>; /* configuration space */
 572			reg-names = "regs", "config";
 573			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
 574			interrupt-names = "aer";
 575			#address-cells = <3>;
 576			#size-cells = <2>;
 577			device_type = "pci";
 578			dma-coherent;
 579			num-viewport = <256>;
 580			bus-range = <0x0 0xff>;
 581			ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000   /* downstream I/O */
 582				  0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 583			msi-parent = <&its 0>;
 584			#interrupt-cells = <1>;
 585			interrupt-map-mask = <0 0 0 7>;
 586			interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,
 587					<0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>,
 588					<0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>,
 589					<0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>;
 590			iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
 591			status = "disabled";
 592		};
 593
 594		pcie_ep1: pcie-ep@3400000 {
 595			compatible = "fsl,ls1088a-pcie-ep";
 596			reg = <0x00 0x03400000 0x0 0x00100000>,
 597			      <0x20 0x00000000 0x8 0x00000000>;
 598			reg-names = "regs", "addr_space";
 599			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
 600			interrupt-names = "pme";
 601			num-ib-windows = <24>;
 602			num-ob-windows = <256>;
 603			max-functions = /bits/ 8 <2>;
 604			status = "disabled";
 605		};
 606
 607		pcie2: pcie@3500000 {
 608			compatible = "fsl,ls1088a-pcie";
 609			reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
 610			      <0x28 0x00000000 0x0 0x00002000>; /* configuration space */
 611			reg-names = "regs", "config";
 612			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
 613			interrupt-names = "aer";
 614			#address-cells = <3>;
 615			#size-cells = <2>;
 616			device_type = "pci";
 617			dma-coherent;
 618			num-viewport = <6>;
 619			bus-range = <0x0 0xff>;
 620			ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000   /* downstream I/O */
 621				  0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 622			msi-parent = <&its 0>;
 623			#interrupt-cells = <1>;
 624			interrupt-map-mask = <0 0 0 7>;
 625			interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>,
 626					<0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>,
 627					<0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>,
 628					<0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>;
 629			iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
 630			status = "disabled";
 631		};
 632
 633		pcie_ep2: pcie-ep@3500000 {
 634			compatible = "fsl,ls1088a-pcie-ep";
 635			reg = <0x00 0x03500000 0x0 0x00100000>,
 636			      <0x28 0x00000000 0x8 0x00000000>;
 637			reg-names = "regs", "addr_space";
 638			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
 639			interrupt-names = "pme";
 640			num-ib-windows = <6>;
 641			num-ob-windows = <6>;
 642			status = "disabled";
 643		};
 644
 645		pcie3: pcie@3600000 {
 646			compatible = "fsl,ls1088a-pcie";
 647			reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
 648			      <0x30 0x00000000 0x0 0x00002000>; /* configuration space */
 649			reg-names = "regs", "config";
 650			interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
 651			interrupt-names = "aer";
 652			#address-cells = <3>;
 653			#size-cells = <2>;
 654			device_type = "pci";
 655			dma-coherent;
 656			num-viewport = <6>;
 657			bus-range = <0x0 0xff>;
 658			ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000   /* downstream I/O */
 659				  0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 660			msi-parent = <&its 0>;
 661			#interrupt-cells = <1>;
 662			interrupt-map-mask = <0 0 0 7>;
 663			interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>,
 664					<0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>,
 665					<0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>,
 666					<0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>;
 667			iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
 668			status = "disabled";
 669		};
 670
 671		pcie_ep3: pcie-ep@3600000 {
 672			compatible = "fsl,ls1088a-pcie-ep";
 673			reg = <0x00 0x03600000 0x0 0x00100000>,
 674			      <0x30 0x00000000 0x8 0x00000000>;
 675			reg-names = "regs", "addr_space";
 676			interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
 677			interrupt-names = "pme";
 678			num-ib-windows = <6>;
 679			num-ob-windows = <6>;
 680			status = "disabled";
 681		};
 682
 683		smmu: iommu@5000000 {
 684			compatible = "arm,mmu-500";
 685			reg = <0 0x5000000 0 0x800000>;
 686			#iommu-cells = <1>;
 687			stream-match-mask = <0x7C00>;
 688			dma-coherent;
 689			#global-interrupts = <12>;
 690				     // global secure fault
 691			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 692				     // combined secure
 693				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 694				     // global non-secure fault
 695				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 696				     // combined non-secure
 697				     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 698				     // performance counter interrupts 0-7
 699				     <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
 700				     <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
 701				     <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
 702				     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
 703				     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
 704				     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
 705				     <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
 706				     <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
 707				     // per context interrupt, 64 interrupts
 708				     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 709				     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 710				     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 711				     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
 712				     <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
 713				     <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
 714				     <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
 715				     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
 716				     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
 717				     <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
 718				     <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
 719				     <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
 720				     <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
 721				     <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
 722				     <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
 723				     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
 724				     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
 725				     <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
 726				     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
 727				     <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
 728				     <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
 729				     <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
 730				     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
 731				     <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
 732				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 733				     <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
 734				     <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
 735				     <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
 736				     <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
 737				     <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
 738				     <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
 739				     <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
 740				     <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
 741				     <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
 742				     <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
 743				     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
 744				     <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
 745				     <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
 746				     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
 747				     <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
 748				     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
 749				     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
 750				     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
 751				     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
 752				     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
 753				     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
 754				     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
 755				     <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
 756				     <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
 757				     <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
 758				     <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
 759				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
 760				     <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
 761				     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
 762				     <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
 763				     <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
 764				     <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
 765				     <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
 766				     <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
 767				     <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
 768				     <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
 769				     <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
 770				     <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
 771				     <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
 772		};
 773
 774		console@8340020 {
 775			compatible = "fsl,dpaa2-console";
 776			reg = <0x00000000 0x08340020 0 0x2>;
 777		};
 778
 779		ptp-timer@8b95000 {
 780			compatible = "fsl,dpaa2-ptp";
 781			reg = <0x0 0x8b95000 0x0 0x100>;
 782			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 783					    QORIQ_CLK_PLL_DIV(1)>;
 784			little-endian;
 785			fsl,extts-fifo;
 786		};
 787
 788		emdio1: mdio@8b96000 {
 789			compatible = "fsl,fman-memac-mdio";
 790			reg = <0x0 0x8b96000 0x0 0x1000>;
 791			little-endian;
 792			#address-cells = <1>;
 793			#size-cells = <0>;
 794			clock-frequency = <2500000>;
 795			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 796					    QORIQ_CLK_PLL_DIV(1)>;
 797			status = "disabled";
 798		};
 799
 800		emdio2: mdio@8b97000 {
 801			compatible = "fsl,fman-memac-mdio";
 802			reg = <0x0 0x8b97000 0x0 0x1000>;
 803			little-endian;
 804			#address-cells = <1>;
 805			#size-cells = <0>;
 806			clock-frequency = <2500000>;
 807			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 808					    QORIQ_CLK_PLL_DIV(1)>;
 809			status = "disabled";
 810		};
 811
 812		pcs_mdio1: mdio@8c07000 {
 813			compatible = "fsl,fman-memac-mdio";
 814			reg = <0x0 0x8c07000 0x0 0x1000>;
 815			little-endian;
 816			#address-cells = <1>;
 817			#size-cells = <0>;
 818			status = "disabled";
 819
 820			pcs1: ethernet-phy@0 {
 821				reg = <0>;
 822			};
 823		};
 824
 825		pcs_mdio2: mdio@8c0b000 {
 826			compatible = "fsl,fman-memac-mdio";
 827			reg = <0x0 0x8c0b000 0x0 0x1000>;
 828			little-endian;
 829			#address-cells = <1>;
 830			#size-cells = <0>;
 831			status = "disabled";
 832
 833			pcs2: ethernet-phy@0 {
 834				reg = <0>;
 835			};
 836		};
 837
 838		pcs_mdio3: mdio@8c0f000 {
 839			compatible = "fsl,fman-memac-mdio";
 840			reg = <0x0 0x8c0f000 0x0 0x1000>;
 841			little-endian;
 842			#address-cells = <1>;
 843			#size-cells = <0>;
 844			status = "disabled";
 845
 846			pcs3_0: ethernet-phy@0 {
 847				reg = <0>;
 848			};
 849
 850			pcs3_1: ethernet-phy@1 {
 851				reg = <1>;
 852			};
 853
 854			pcs3_2: ethernet-phy@2 {
 855				reg = <2>;
 856			};
 857
 858			pcs3_3: ethernet-phy@3 {
 859				reg = <3>;
 860			};
 861		};
 862
 863		pcs_mdio7: mdio@8c1f000 {
 864			compatible = "fsl,fman-memac-mdio";
 865			reg = <0x0 0x8c1f000 0x0 0x1000>;
 866			little-endian;
 867			#address-cells = <1>;
 868			#size-cells = <0>;
 869			status = "disabled";
 870
 871			pcs7_0: ethernet-phy@0 {
 872				reg = <0>;
 873			};
 874
 875			pcs7_1: ethernet-phy@1 {
 876				reg = <1>;
 877			};
 878
 879			pcs7_2: ethernet-phy@2 {
 880				reg = <2>;
 881			};
 882
 883			pcs7_3: ethernet-phy@3 {
 884				reg = <3>;
 885			};
 886		};
 887
 888		cluster1_core0_watchdog: watchdog@c000000 {
 889			compatible = "arm,sp805", "arm,primecell";
 890			reg = <0x0 0xc000000 0x0 0x1000>;
 891			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 892					    QORIQ_CLK_PLL_DIV(16)>,
 893				 <&clockgen QORIQ_CLK_PLATFORM_PLL
 894					    QORIQ_CLK_PLL_DIV(16)>;
 895			clock-names = "wdog_clk", "apb_pclk";
 896		};
 897
 898		cluster1_core1_watchdog: watchdog@c010000 {
 899			compatible = "arm,sp805", "arm,primecell";
 900			reg = <0x0 0xc010000 0x0 0x1000>;
 901			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 902					    QORIQ_CLK_PLL_DIV(16)>,
 903				 <&clockgen QORIQ_CLK_PLATFORM_PLL
 904					    QORIQ_CLK_PLL_DIV(16)>;
 905			clock-names = "wdog_clk", "apb_pclk";
 906		};
 907
 908		cluster1_core2_watchdog: watchdog@c020000 {
 909			compatible = "arm,sp805", "arm,primecell";
 910			reg = <0x0 0xc020000 0x0 0x1000>;
 911			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 912					    QORIQ_CLK_PLL_DIV(16)>,
 913				 <&clockgen QORIQ_CLK_PLATFORM_PLL
 914					    QORIQ_CLK_PLL_DIV(16)>;
 915			clock-names = "wdog_clk", "apb_pclk";
 916		};
 917
 918		cluster1_core3_watchdog: watchdog@c030000 {
 919			compatible = "arm,sp805", "arm,primecell";
 920			reg = <0x0 0xc030000 0x0 0x1000>;
 921			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 922					    QORIQ_CLK_PLL_DIV(16)>,
 923				 <&clockgen QORIQ_CLK_PLATFORM_PLL
 924					    QORIQ_CLK_PLL_DIV(16)>;
 925			clock-names = "wdog_clk", "apb_pclk";
 926		};
 927
 928		cluster2_core0_watchdog: watchdog@c100000 {
 929			compatible = "arm,sp805", "arm,primecell";
 930			reg = <0x0 0xc100000 0x0 0x1000>;
 931			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 932					    QORIQ_CLK_PLL_DIV(16)>,
 933				 <&clockgen QORIQ_CLK_PLATFORM_PLL
 934					    QORIQ_CLK_PLL_DIV(16)>;
 935			clock-names = "wdog_clk", "apb_pclk";
 936		};
 937
 938		cluster2_core1_watchdog: watchdog@c110000 {
 939			compatible = "arm,sp805", "arm,primecell";
 940			reg = <0x0 0xc110000 0x0 0x1000>;
 941			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 942					    QORIQ_CLK_PLL_DIV(16)>,
 943				 <&clockgen QORIQ_CLK_PLATFORM_PLL
 944					    QORIQ_CLK_PLL_DIV(16)>;
 945			clock-names = "wdog_clk", "apb_pclk";
 946		};
 947
 948		cluster2_core2_watchdog: watchdog@c120000 {
 949			compatible = "arm,sp805", "arm,primecell";
 950			reg = <0x0 0xc120000 0x0 0x1000>;
 951			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 952					    QORIQ_CLK_PLL_DIV(16)>,
 953				 <&clockgen QORIQ_CLK_PLATFORM_PLL
 954					    QORIQ_CLK_PLL_DIV(16)>;
 955			clock-names = "wdog_clk", "apb_pclk";
 956		};
 957
 958		cluster2_core3_watchdog: watchdog@c130000 {
 959			compatible = "arm,sp805", "arm,primecell";
 960			reg = <0x0 0xc130000 0x0 0x1000>;
 961			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 962					    QORIQ_CLK_PLL_DIV(16)>,
 963				 <&clockgen QORIQ_CLK_PLATFORM_PLL
 964					    QORIQ_CLK_PLL_DIV(16)>;
 965			clock-names = "wdog_clk", "apb_pclk";
 966		};
 967
 968		fsl_mc: fsl-mc@80c000000 {
 969			compatible = "fsl,qoriq-mc";
 970			reg = <0x00000008 0x0c000000 0 0x40>,	 /* MC portal base */
 971			      <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
 972			msi-parent = <&its 0>;
 973			iommu-map = <0 &smmu 0 0>;	/* This is fixed-up by u-boot */
 974			dma-coherent;
 975			#address-cells = <3>;
 976			#size-cells = <1>;
 977
 978			/*
 979			 * Region type 0x0 - MC portals
 980			 * Region type 0x1 - QBMAN portals
 981			 */
 982			ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
 983				  0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
 984
 985			dpmacs {
 986				#address-cells = <1>;
 987				#size-cells = <0>;
 988
 989				dpmac1: ethernet@1 {
 990					compatible = "fsl,qoriq-mc-dpmac";
 991					reg = <1>;
 992				};
 993
 994				dpmac2: ethernet@2 {
 995					compatible = "fsl,qoriq-mc-dpmac";
 996					reg = <2>;
 997				};
 998
 999				dpmac3: ethernet@3 {
1000					compatible = "fsl,qoriq-mc-dpmac";
1001					reg = <3>;
1002				};
1003
1004				dpmac4: ethernet@4 {
1005					compatible = "fsl,qoriq-mc-dpmac";
1006					reg = <4>;
1007				};
1008
1009				dpmac5: ethernet@5 {
1010					compatible = "fsl,qoriq-mc-dpmac";
1011					reg = <5>;
1012				};
1013
1014				dpmac6: ethernet@6 {
1015					compatible = "fsl,qoriq-mc-dpmac";
1016					reg = <6>;
1017				};
1018
1019				dpmac7: ethernet@7 {
1020					compatible = "fsl,qoriq-mc-dpmac";
1021					reg = <7>;
1022				};
1023
1024				dpmac8: ethernet@8 {
1025					compatible = "fsl,qoriq-mc-dpmac";
1026					reg = <8>;
1027				};
1028
1029				dpmac9: ethernet@9 {
1030					compatible = "fsl,qoriq-mc-dpmac";
1031					reg = <9>;
1032				};
1033
1034				dpmac10: ethernet@a {
1035					compatible = "fsl,qoriq-mc-dpmac";
1036					reg = <0xa>;
1037				};
1038			};
1039		};
1040
1041		rcpm: wakeup-controller@1e34040 {
1042			compatible = "fsl,ls1088a-rcpm", "fsl,qoriq-rcpm-2.1+";
1043			reg = <0x0 0x1e34040 0x0 0x18>;
1044			#fsl,rcpm-wakeup-cells = <6>;
1045			little-endian;
1046		};
1047
1048		ftm_alarm0: rtc@2800000 {
1049			compatible = "fsl,ls1088a-ftm-alarm";
1050			reg = <0x0 0x2800000 0x0 0x10000>;
1051			fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>;
1052			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1053		};
1054	};
1055
1056	firmware {
1057		optee {
1058			compatible = "linaro,optee-tz";
1059			method = "smc";
1060		};
1061	};
1062};