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fsl-ls1046a.dtsi
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linux-6.19.14/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Include file for NXP Layerscape-1046A family SoC. 4 * 5 * Copyright 2016 Freescale Semiconductor, Inc. 6 * Copyright 2018, 2020 NXP 7 * 8 * Mingkai Hu <mingkai.hu@nxp.com> 9 */ 10 11#include <dt-bindings/clock/fsl,qoriq-clockgen.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/thermal/thermal.h> 14#include <dt-bindings/gpio/gpio.h> 15 16/ { 17 compatible = "fsl,ls1046a"; 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 crypto = &crypto; 24 fman0 = &fman0; 25 ethernet0 = &enet0; 26 ethernet1 = &enet1; 27 ethernet2 = &enet2; 28 ethernet3 = &enet3; 29 ethernet4 = &enet4; 30 ethernet5 = &enet5; 31 ethernet6 = &enet6; 32 ethernet7 = &enet7; 33 rtc1 = &ftm_alarm0; 34 }; 35 36 cpus { 37 #address-cells = <1>; 38 #size-cells = <0>; 39 40 cpu0: cpu@0 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a72"; 43 reg = <0x0>; 44 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 45 next-level-cache = <&l2>; 46 cpu-idle-states = <&CPU_PH20>; 47 #cooling-cells = <2>; 48 }; 49 50 cpu1: cpu@1 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a72"; 53 reg = <0x1>; 54 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 55 next-level-cache = <&l2>; 56 cpu-idle-states = <&CPU_PH20>; 57 #cooling-cells = <2>; 58 }; 59 60 cpu2: cpu@2 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a72"; 63 reg = <0x2>; 64 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 65 next-level-cache = <&l2>; 66 cpu-idle-states = <&CPU_PH20>; 67 #cooling-cells = <2>; 68 }; 69 70 cpu3: cpu@3 { 71 device_type = "cpu"; 72 compatible = "arm,cortex-a72"; 73 reg = <0x3>; 74 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 75 next-level-cache = <&l2>; 76 cpu-idle-states = <&CPU_PH20>; 77 #cooling-cells = <2>; 78 }; 79 80 l2: l2-cache { 81 compatible = "cache"; 82 cache-level = <2>; 83 cache-unified; 84 }; 85 }; 86 87 idle-states { 88 /* 89 * PSCI node is not added default, U-boot will add missing 90 * parts if it determines to use PSCI. 91 */ 92 entry-method = "psci"; 93 94 CPU_PH20: cpu-ph20 { 95 compatible = "arm,idle-state"; 96 idle-state-name = "PH20"; 97 arm,psci-suspend-param = <0x0>; 98 entry-latency-us = <1000>; 99 exit-latency-us = <1000>; 100 min-residency-us = <3000>; 101 }; 102 }; 103 104 memory@80000000 { 105 device_type = "memory"; 106 /* Real size will be filled by bootloader */ 107 reg = <0x0 0x80000000 0x0 0x0>; 108 }; 109 110 sysclk: sysclk { 111 compatible = "fixed-clock"; 112 #clock-cells = <0>; 113 clock-frequency = <100000000>; 114 clock-output-names = "sysclk"; 115 }; 116 117 reboot { 118 compatible = "syscon-reboot"; 119 regmap = <&dcfg>; 120 offset = <0xb0>; 121 mask = <0x02>; 122 }; 123 124 thermal-zones { 125 ddr-thermal { 126 polling-delay-passive = <1000>; 127 polling-delay = <5000>; 128 thermal-sensors = <&tmu 0>; 129 130 trips { 131 ddr-ctrler-alert { 132 temperature = <85000>; 133 hysteresis = <2000>; 134 type = "passive"; 135 }; 136 137 ddr-ctrler-crit { 138 temperature = <95000>; 139 hysteresis = <2000>; 140 type = "critical"; 141 }; 142 }; 143 }; 144 145 serdes-thermal { 146 polling-delay-passive = <1000>; 147 polling-delay = <5000>; 148 thermal-sensors = <&tmu 1>; 149 150 trips { 151 serdes-alert { 152 temperature = <85000>; 153 hysteresis = <2000>; 154 type = "passive"; 155 }; 156 157 serdes-crit { 158 temperature = <95000>; 159 hysteresis = <2000>; 160 type = "critical"; 161 }; 162 }; 163 }; 164 165 fman-thermal { 166 polling-delay-passive = <1000>; 167 polling-delay = <5000>; 168 thermal-sensors = <&tmu 2>; 169 170 trips { 171 fman-alert { 172 temperature = <85000>; 173 hysteresis = <2000>; 174 type = "passive"; 175 }; 176 177 fman-crit { 178 temperature = <95000>; 179 hysteresis = <2000>; 180 type = "critical"; 181 }; 182 }; 183 }; 184 185 cluster-thermal { 186 polling-delay-passive = <1000>; 187 polling-delay = <5000>; 188 thermal-sensors = <&tmu 3>; 189 190 trips { 191 core_cluster_alert: core-cluster-alert { 192 temperature = <85000>; 193 hysteresis = <2000>; 194 type = "passive"; 195 }; 196 197 core_cluster_crit: core-cluster-crit { 198 temperature = <95000>; 199 hysteresis = <2000>; 200 type = "critical"; 201 }; 202 }; 203 204 cooling-maps { 205 map0 { 206 trip = <&core_cluster_alert>; 207 cooling-device = 208 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 209 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 210 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 211 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 212 }; 213 }; 214 }; 215 216 sec-thermal { 217 polling-delay-passive = <1000>; 218 polling-delay = <5000>; 219 thermal-sensors = <&tmu 4>; 220 221 trips { 222 sec-alert { 223 temperature = <85000>; 224 hysteresis = <2000>; 225 type = "passive"; 226 }; 227 228 sec-crit { 229 temperature = <95000>; 230 hysteresis = <2000>; 231 type = "critical"; 232 }; 233 }; 234 }; 235 }; 236 237 timer { 238 compatible = "arm,armv8-timer"; 239 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xf) | 240 IRQ_TYPE_LEVEL_LOW)>, 241 <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xf) | 242 IRQ_TYPE_LEVEL_LOW)>, 243 <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xf) | 244 IRQ_TYPE_LEVEL_LOW)>, 245 <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xf) | 246 IRQ_TYPE_LEVEL_LOW)>; 247 }; 248 249 pmu { 250 compatible = "arm,cortex-a72-pmu"; 251 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 252 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 253 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 254 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 255 interrupt-affinity = <&cpu0>, 256 <&cpu1>, 257 <&cpu2>, 258 <&cpu3>; 259 }; 260 261 gic: interrupt-controller@1400000 { 262 compatible = "arm,gic-400"; 263 #address-cells = <0>; 264 #interrupt-cells = <3>; 265 interrupt-controller; 266 reg = <0x0 0x1410000 0 0x10000>, /* GICD */ 267 <0x0 0x1420000 0 0x20000>, /* GICC */ 268 <0x0 0x1440000 0 0x20000>, /* GICH */ 269 <0x0 0x1460000 0 0x20000>; /* GICV */ 270 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) | 271 IRQ_TYPE_LEVEL_LOW)>; 272 }; 273 274 soc: soc { 275 compatible = "simple-bus"; 276 #address-cells = <2>; 277 #size-cells = <2>; 278 ranges; 279 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; 280 dma-coherent; 281 282 ddr: memory-controller@1080000 { 283 compatible = "fsl,qoriq-memory-controller"; 284 reg = <0x0 0x1080000 0x0 0x1000>; 285 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 286 }; 287 288 ifc: memory-controller@1530000 { 289 compatible = "fsl,ifc"; 290 reg = <0x0 0x1530000 0x0 0x10000>; 291 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 292 status = "disabled"; 293 }; 294 295 qspi: spi@1550000 { 296 compatible = "fsl,ls1021a-qspi"; 297 #address-cells = <1>; 298 #size-cells = <0>; 299 reg = <0x0 0x1550000 0x0 0x10000>, 300 <0x0 0x40000000 0x0 0x10000000>; 301 reg-names = "QuadSPI", "QuadSPI-memory"; 302 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 303 clock-names = "qspi_en", "qspi"; 304 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 305 QORIQ_CLK_PLL_DIV(2)>, 306 <&clockgen QORIQ_CLK_PLATFORM_PLL 307 QORIQ_CLK_PLL_DIV(2)>; 308 status = "disabled"; 309 }; 310 311 esdhc: mmc@1560000 { 312 compatible = "fsl,ls1046a-esdhc", "fsl,esdhc"; 313 reg = <0x0 0x1560000 0x0 0x10000>; 314 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 315 clocks = <&clockgen QORIQ_CLK_HWACCEL 1>; 316 voltage-ranges = <1800 1800 3300 3300>; 317 sdhci,auto-cmd12; 318 bus-width = <4>; 319 }; 320 321 scfg: scfg@1570000 { 322 compatible = "fsl,ls1046a-scfg", "syscon"; 323 reg = <0x0 0x1570000 0x0 0x10000>; 324 big-endian; 325 #address-cells = <1>; 326 #size-cells = <1>; 327 ranges = <0x0 0x0 0x1570000 0x10000>; 328 329 extirq: interrupt-controller@1ac { 330 compatible = "fsl,ls1046a-extirq", "fsl,ls1043a-extirq"; 331 #interrupt-cells = <2>; 332 #address-cells = <0>; 333 interrupt-controller; 334 reg = <0x1ac 4>; 335 interrupt-map = 336 <0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 337 <1 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 338 <2 0 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 339 <3 0 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 340 <4 0 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 341 <5 0 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 342 <6 0 &gic GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 343 <7 0 &gic GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 344 <8 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 345 <9 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 346 <10 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 347 <11 0 &gic GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 348 interrupt-map-mask = <0xf 0x0>; 349 }; 350 }; 351 352 crypto: crypto@1700000 { 353 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0", 354 "fsl,sec-v4.0"; 355 fsl,sec-era = <8>; 356 #address-cells = <1>; 357 #size-cells = <1>; 358 ranges = <0x0 0x00 0x1700000 0x100000>; 359 reg = <0x00 0x1700000 0x0 0x100000>; 360 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 361 362 sec_jr0: jr@10000 { 363 compatible = "fsl,sec-v5.4-job-ring", 364 "fsl,sec-v5.0-job-ring", 365 "fsl,sec-v4.0-job-ring"; 366 reg = <0x10000 0x10000>; 367 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 368 }; 369 370 sec_jr1: jr@20000 { 371 compatible = "fsl,sec-v5.4-job-ring", 372 "fsl,sec-v5.0-job-ring", 373 "fsl,sec-v4.0-job-ring"; 374 reg = <0x20000 0x10000>; 375 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 376 }; 377 378 sec_jr2: jr@30000 { 379 compatible = "fsl,sec-v5.4-job-ring", 380 "fsl,sec-v5.0-job-ring", 381 "fsl,sec-v4.0-job-ring"; 382 reg = <0x30000 0x10000>; 383 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 384 }; 385 386 sec_jr3: jr@40000 { 387 compatible = "fsl,sec-v5.4-job-ring", 388 "fsl,sec-v5.0-job-ring", 389 "fsl,sec-v4.0-job-ring"; 390 reg = <0x40000 0x10000>; 391 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 392 }; 393 }; 394 395 qman: qman@1880000 { 396 compatible = "fsl,qman"; 397 reg = <0x0 0x1880000 0x0 0x10000>; 398 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 399 memory-region = <&qman_fqd &qman_pfdr>; 400 401 }; 402 403 bman: bman@1890000 { 404 compatible = "fsl,bman"; 405 reg = <0x0 0x1890000 0x0 0x10000>; 406 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 407 memory-region = <&bman_fbpr>; 408 409 }; 410 411 qportals: qman-portals-bus@500000000 { 412 ranges = <0x0 0x5 0x00000000 0x8000000>; 413 }; 414 415 bportals: bman-portals-bus@508000000 { 416 ranges = <0x0 0x5 0x08000000 0x8000000>; 417 }; 418 419 sfp: efuse@1e80000 { 420 compatible = "fsl,ls1021a-sfp"; 421 reg = <0x0 0x1e80000 0x0 0x10000>; 422 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 423 QORIQ_CLK_PLL_DIV(4)>; 424 clock-names = "sfp"; 425 }; 426 427 dcfg: dcfg@1ee0000 { 428 compatible = "fsl,ls1046a-dcfg", "syscon"; 429 reg = <0x0 0x1ee0000 0x0 0x1000>; 430 big-endian; 431 }; 432 433 clockgen: clocking@1ee1000 { 434 compatible = "fsl,ls1046a-clockgen"; 435 reg = <0x0 0x1ee1000 0x0 0x1000>; 436 #clock-cells = <2>; 437 clocks = <&sysclk>; 438 }; 439 440 tmu: tmu@1f00000 { 441 compatible = "fsl,qoriq-tmu"; 442 reg = <0x0 0x1f00000 0x0 0x10000>; 443 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 444 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>; 445 fsl,tmu-calibration = 446 /* Calibration data group 1 */ 447 <0x00000000 0x00000023>, 448 <0x00000001 0x00000029>, 449 <0x00000002 0x0000002f>, 450 <0x00000003 0x00000036>, 451 <0x00000004 0x0000003c>, 452 <0x00000005 0x00000042>, 453 <0x00000006 0x00000049>, 454 <0x00000007 0x0000004f>, 455 <0x00000008 0x00000055>, 456 <0x00000009 0x0000005c>, 457 <0x0000000a 0x00000062>, 458 <0x0000000b 0x00000068>, 459 /* Calibration data group 2 */ 460 <0x00010000 0x00000022>, 461 <0x00010001 0x0000002a>, 462 <0x00010002 0x00000032>, 463 <0x00010003 0x0000003a>, 464 <0x00010004 0x00000042>, 465 <0x00010005 0x0000004a>, 466 <0x00010006 0x00000052>, 467 <0x00010007 0x0000005a>, 468 <0x00010008 0x00000062>, 469 <0x00010009 0x0000006a>, 470 /* Calibration data group 3 */ 471 <0x00020000 0x00000021>, 472 <0x00020001 0x0000002b>, 473 <0x00020002 0x00000035>, 474 <0x00020003 0x0000003e>, 475 <0x00020004 0x00000048>, 476 <0x00020005 0x00000052>, 477 <0x00020006 0x0000005c>, 478 /* Calibration data group 4 */ 479 <0x00030000 0x00000011>, 480 <0x00030001 0x0000001a>, 481 <0x00030002 0x00000024>, 482 <0x00030003 0x0000002e>, 483 <0x00030004 0x00000038>, 484 <0x00030005 0x00000042>, 485 <0x00030006 0x0000004c>, 486 <0x00030007 0x00000056>; 487 #thermal-sensor-cells = <1>; 488 }; 489 490 dspi: spi@2100000 { 491 compatible = "fsl,ls1021a-v1.0-dspi"; 492 #address-cells = <1>; 493 #size-cells = <0>; 494 reg = <0x0 0x2100000 0x0 0x10000>; 495 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 496 clock-names = "dspi"; 497 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 498 QORIQ_CLK_PLL_DIV(2)>; 499 spi-num-chipselects = <5>; 500 big-endian; 501 status = "disabled"; 502 }; 503 504 i2c0: i2c@2180000 { 505 compatible = "fsl,ls1046a-i2c", "fsl,vf610-i2c"; 506 #address-cells = <1>; 507 #size-cells = <0>; 508 reg = <0x0 0x2180000 0x0 0x10000>; 509 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 510 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 511 QORIQ_CLK_PLL_DIV(2)>; 512 dmas = <&edma0 1 38>, 513 <&edma0 1 39>; 514 dma-names = "rx", "tx"; 515 status = "disabled"; 516 }; 517 518 i2c1: i2c@2190000 { 519 compatible = "fsl,ls1046a-i2c", "fsl,vf610-i2c"; 520 #address-cells = <1>; 521 #size-cells = <0>; 522 reg = <0x0 0x2190000 0x0 0x10000>; 523 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 524 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 525 QORIQ_CLK_PLL_DIV(2)>; 526 scl-gpios = <&gpio3 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 527 dmas = <&edma0 1 36>, 528 <&edma0 1 37>; 529 dma-names = "rx", "tx"; 530 status = "disabled"; 531 }; 532 533 i2c2: i2c@21a0000 { 534 compatible = "fsl,ls1046a-i2c", "fsl,vf610-i2c"; 535 #address-cells = <1>; 536 #size-cells = <0>; 537 reg = <0x0 0x21a0000 0x0 0x10000>; 538 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 539 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 540 QORIQ_CLK_PLL_DIV(2)>; 541 scl-gpios = <&gpio3 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 542 dmas = <&edma0 1 34>, 543 <&edma0 1 35>; 544 dma-names = "rx", "tx"; 545 status = "disabled"; 546 }; 547 548 i2c3: i2c@21b0000 { 549 compatible = "fsl,ls1046a-i2c", "fsl,vf610-i2c"; 550 #address-cells = <1>; 551 #size-cells = <0>; 552 reg = <0x0 0x21b0000 0x0 0x10000>; 553 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 554 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 555 QORIQ_CLK_PLL_DIV(2)>; 556 scl-gpios = <&gpio3 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 557 dmas = <&edma0 1 40>, 558 <&edma0 1 41>; 559 dma-names = "rx", "tx"; 560 status = "disabled"; 561 }; 562 563 duart0: serial@21c0500 { 564 compatible = "fsl,ns16550", "ns16550a"; 565 reg = <0x00 0x21c0500 0x0 0x100>; 566 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 567 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 568 QORIQ_CLK_PLL_DIV(2)>; 569 status = "disabled"; 570 }; 571 572 duart1: serial@21c0600 { 573 compatible = "fsl,ns16550", "ns16550a"; 574 reg = <0x00 0x21c0600 0x0 0x100>; 575 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 576 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 577 QORIQ_CLK_PLL_DIV(2)>; 578 status = "disabled"; 579 }; 580 581 duart2: serial@21d0500 { 582 compatible = "fsl,ns16550", "ns16550a"; 583 reg = <0x0 0x21d0500 0x0 0x100>; 584 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 585 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 586 QORIQ_CLK_PLL_DIV(2)>; 587 status = "disabled"; 588 }; 589 590 duart3: serial@21d0600 { 591 compatible = "fsl,ns16550", "ns16550a"; 592 reg = <0x0 0x21d0600 0x0 0x100>; 593 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 594 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 595 QORIQ_CLK_PLL_DIV(2)>; 596 status = "disabled"; 597 }; 598 599 gpio0: gpio@2300000 { 600 compatible = "fsl,ls1046a-gpio", "fsl,qoriq-gpio"; 601 reg = <0x0 0x2300000 0x0 0x10000>; 602 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 603 gpio-controller; 604 #gpio-cells = <2>; 605 interrupt-controller; 606 #interrupt-cells = <2>; 607 }; 608 609 gpio1: gpio@2310000 { 610 compatible = "fsl,ls1046a-gpio", "fsl,qoriq-gpio"; 611 reg = <0x0 0x2310000 0x0 0x10000>; 612 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 613 gpio-controller; 614 #gpio-cells = <2>; 615 interrupt-controller; 616 #interrupt-cells = <2>; 617 }; 618 619 gpio2: gpio@2320000 { 620 compatible = "fsl,ls1046a-gpio", "fsl,qoriq-gpio"; 621 reg = <0x0 0x2320000 0x0 0x10000>; 622 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 623 gpio-controller; 624 #gpio-cells = <2>; 625 interrupt-controller; 626 #interrupt-cells = <2>; 627 }; 628 629 gpio3: gpio@2330000 { 630 compatible = "fsl,ls1046a-gpio", "fsl,qoriq-gpio"; 631 reg = <0x0 0x2330000 0x0 0x10000>; 632 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 633 gpio-controller; 634 #gpio-cells = <2>; 635 interrupt-controller; 636 #interrupt-cells = <2>; 637 }; 638 639 lpuart0: serial@2950000 { 640 compatible = "fsl,ls1021a-lpuart"; 641 reg = <0x0 0x2950000 0x0 0x1000>; 642 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 643 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 644 QORIQ_CLK_PLL_DIV(1)>; 645 clock-names = "ipg"; 646 dmas = <&edma0 1 32>, 647 <&edma0 1 33>; 648 dma-names = "rx", "tx"; 649 status = "disabled"; 650 }; 651 652 lpuart1: serial@2960000 { 653 compatible = "fsl,ls1021a-lpuart"; 654 reg = <0x0 0x2960000 0x0 0x1000>; 655 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 656 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 657 QORIQ_CLK_PLL_DIV(2)>; 658 clock-names = "ipg"; 659 dmas = <&edma0 1 30>, 660 <&edma0 1 31>; 661 dma-names = "rx", "tx"; 662 status = "disabled"; 663 }; 664 665 lpuart2: serial@2970000 { 666 compatible = "fsl,ls1021a-lpuart"; 667 reg = <0x0 0x2970000 0x0 0x1000>; 668 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 669 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 670 QORIQ_CLK_PLL_DIV(2)>; 671 clock-names = "ipg"; 672 dmas = <&edma0 1 28>, 673 <&edma0 1 29>; 674 dma-names = "rx", "tx"; 675 status = "disabled"; 676 }; 677 678 lpuart3: serial@2980000 { 679 compatible = "fsl,ls1021a-lpuart"; 680 reg = <0x0 0x2980000 0x0 0x1000>; 681 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 682 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 683 QORIQ_CLK_PLL_DIV(2)>; 684 clock-names = "ipg"; 685 dmas = <&edma0 1 26>, 686 <&edma0 1 27>; 687 dma-names = "rx", "tx"; 688 status = "disabled"; 689 }; 690 691 lpuart4: serial@2990000 { 692 compatible = "fsl,ls1021a-lpuart"; 693 reg = <0x0 0x2990000 0x0 0x1000>; 694 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 695 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 696 QORIQ_CLK_PLL_DIV(2)>; 697 clock-names = "ipg"; 698 dmas = <&edma0 1 24>, 699 <&edma0 1 25>; 700 dma-names = "rx", "tx"; 701 status = "disabled"; 702 }; 703 704 lpuart5: serial@29a0000 { 705 compatible = "fsl,ls1021a-lpuart"; 706 reg = <0x0 0x29a0000 0x0 0x1000>; 707 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 708 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 709 QORIQ_CLK_PLL_DIV(2)>; 710 clock-names = "ipg"; 711 dmas = <&edma0 1 22>, 712 <&edma0 1 23>; 713 dma-names = "rx", "tx"; 714 status = "disabled"; 715 }; 716 717 wdog0: watchdog@2ad0000 { 718 compatible = "fsl,ls1046a-wdt", "fsl,imx21-wdt"; 719 reg = <0x0 0x2ad0000 0x0 0x10000>; 720 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 721 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 722 QORIQ_CLK_PLL_DIV(2)>; 723 big-endian; 724 }; 725 726 edma0: dma-controller@2c00000 { 727 #dma-cells = <2>; 728 compatible = "fsl,vf610-edma"; 729 reg = <0x0 0x2c00000 0x0 0x10000>, 730 <0x0 0x2c10000 0x0 0x10000>, 731 <0x0 0x2c20000 0x0 0x10000>; 732 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 733 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 734 interrupt-names = "edma-tx", "edma-err"; 735 dma-channels = <32>; 736 big-endian; 737 clock-names = "dmamux0", "dmamux1"; 738 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 739 QORIQ_CLK_PLL_DIV(2)>, 740 <&clockgen QORIQ_CLK_PLATFORM_PLL 741 QORIQ_CLK_PLL_DIV(2)>; 742 }; 743 744 aux_bus: bus { 745 #address-cells = <2>; 746 #size-cells = <2>; 747 compatible = "simple-bus"; 748 ranges; 749 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x00000000>; 750 751 usb0: usb@2f00000 { 752 compatible = "fsl,ls1046a-dwc3", "fsl,ls1028a-dwc3"; 753 reg = <0x0 0x2f00000 0x0 0x10000>; 754 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 755 dr_mode = "host"; 756 dma-coherent; 757 snps,quirk-frame-length-adjustment = <0x20>; 758 snps,dis_rxdet_inp3_quirk; 759 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 760 usb3-lpm-capable; 761 }; 762 763 usb1: usb@3000000 { 764 compatible = "fsl,ls1046a-dwc3", "fsl,ls1028a-dwc3"; 765 reg = <0x0 0x3000000 0x0 0x10000>; 766 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 767 dr_mode = "host"; 768 dma-coherent; 769 snps,quirk-frame-length-adjustment = <0x20>; 770 snps,dis_rxdet_inp3_quirk; 771 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 772 usb3-lpm-capable; 773 }; 774 775 usb2: usb@3100000 { 776 compatible = "fsl,ls1046a-dwc3", "fsl,ls1028a-dwc3"; 777 reg = <0x0 0x3100000 0x0 0x10000>; 778 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 779 dr_mode = "host"; 780 dma-coherent; 781 snps,quirk-frame-length-adjustment = <0x20>; 782 snps,dis_rxdet_inp3_quirk; 783 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 784 usb3-lpm-capable; 785 }; 786 787 sata: sata@3200000 { 788 compatible = "fsl,ls1046a-ahci"; 789 reg = <0x0 0x3200000 0x0 0x10000>, 790 <0x0 0x20140520 0x0 0x4>; 791 reg-names = "ahci", "sata-ecc"; 792 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 793 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 794 QORIQ_CLK_PLL_DIV(2)>; 795 }; 796 }; 797 798 msi1: msi-controller@1580000 { 799 compatible = "fsl,ls1046a-msi"; 800 msi-controller; 801 reg = <0x0 0x1580000 0x0 0x10000>; 802 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 803 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 804 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 805 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 806 }; 807 808 msi2: msi-controller@1590000 { 809 compatible = "fsl,ls1046a-msi"; 810 msi-controller; 811 reg = <0x0 0x1590000 0x0 0x10000>; 812 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 813 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 814 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 815 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 816 }; 817 818 msi3: msi-controller@15a0000 { 819 compatible = "fsl,ls1046a-msi"; 820 msi-controller; 821 reg = <0x0 0x15a0000 0x0 0x10000>; 822 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 823 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 824 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 825 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 826 }; 827 828 pcie1: pcie@3400000 { 829 compatible = "fsl,ls1046a-pcie"; 830 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ 831 <0x40 0x00000000 0x0 0x00002000>; /* configuration space */ 832 reg-names = "regs", "config"; 833 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 834 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 835 interrupt-names = "pme", "aer"; 836 #address-cells = <3>; 837 #size-cells = <2>; 838 device_type = "pci"; 839 num-viewport = <8>; 840 bus-range = <0x0 0xff>; 841 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ 842 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 843 msi-parent = <&msi1>, <&msi2>, <&msi3>; 844 #interrupt-cells = <1>; 845 interrupt-map-mask = <0 0 0 7>; 846 interrupt-map = <0000 0 0 1 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 847 <0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 848 <0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 849 <0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 850 big-endian; 851 status = "disabled"; 852 }; 853 854 pcie_ep1: pcie_ep@3400000 { 855 compatible = "fsl,ls1046a-pcie-ep"; 856 reg = <0x00 0x03400000 0x0 0x00100000>, 857 <0x40 0x00000000 0x8 0x00000000>; 858 reg-names = "regs", "addr_space"; 859 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 860 interrupt-names = "pme"; 861 num-ib-windows = <6>; 862 num-ob-windows = <8>; 863 big-endian; 864 status = "disabled"; 865 }; 866 867 pcie2: pcie@3500000 { 868 compatible = "fsl,ls1046a-pcie"; 869 reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ 870 <0x48 0x00000000 0x0 0x00002000>; /* configuration space */ 871 reg-names = "regs", "config"; 872 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 873 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 874 interrupt-names = "pme", "aer"; 875 #address-cells = <3>; 876 #size-cells = <2>; 877 device_type = "pci"; 878 num-viewport = <8>; 879 bus-range = <0x0 0xff>; 880 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ 881 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 882 msi-parent = <&msi2>, <&msi3>, <&msi1>; 883 #interrupt-cells = <1>; 884 interrupt-map-mask = <0 0 0 7>; 885 interrupt-map = <0000 0 0 1 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 886 <0000 0 0 2 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 887 <0000 0 0 3 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 888 <0000 0 0 4 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 889 big-endian; 890 status = "disabled"; 891 }; 892 893 pcie_ep2: pcie_ep@3500000 { 894 compatible = "fsl,ls1046a-pcie-ep"; 895 reg = <0x00 0x03500000 0x0 0x00100000>, 896 <0x48 0x00000000 0x8 0x00000000>; 897 reg-names = "regs", "addr_space"; 898 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 899 interrupt-names = "pme"; 900 num-ib-windows = <6>; 901 num-ob-windows = <8>; 902 big-endian; 903 status = "disabled"; 904 }; 905 906 pcie3: pcie@3600000 { 907 compatible = "fsl,ls1046a-pcie"; 908 reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */ 909 <0x50 0x00000000 0x0 0x00002000>; /* configuration space */ 910 reg-names = "regs", "config"; 911 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 912 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 913 interrupt-names = "pme", "aer"; 914 #address-cells = <3>; 915 #size-cells = <2>; 916 device_type = "pci"; 917 num-viewport = <8>; 918 bus-range = <0x0 0xff>; 919 ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */ 920 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 921 msi-parent = <&msi3>, <&msi1>, <&msi2>; 922 #interrupt-cells = <1>; 923 interrupt-map-mask = <0 0 0 7>; 924 interrupt-map = <0000 0 0 1 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 925 <0000 0 0 2 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 926 <0000 0 0 3 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 927 <0000 0 0 4 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 928 big-endian; 929 status = "disabled"; 930 }; 931 932 pcie_ep3: pcie_ep@3600000 { 933 compatible = "fsl,ls1046a-pcie-ep"; 934 reg = <0x00 0x03600000 0x0 0x00100000>, 935 <0x50 0x00000000 0x8 0x00000000>; 936 reg-names = "regs", "addr_space"; 937 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 938 interrupt-names = "pme"; 939 num-ib-windows = <6>; 940 num-ob-windows = <8>; 941 big-endian; 942 status = "disabled"; 943 }; 944 945 qdma: dma-controller@8380000 { 946 compatible = "fsl,ls1046a-qdma", "fsl,ls1021a-qdma"; 947 reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */ 948 <0x0 0x8390000 0x0 0x10000>, /* Status regs */ 949 <0x0 0x83a0000 0x0 0x40000>; /* Block regs */ 950 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 951 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 952 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 953 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 954 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 955 interrupt-names = "qdma-error", "qdma-queue0", 956 "qdma-queue1", "qdma-queue2", "qdma-queue3"; 957 #dma-cells = <1>; 958 dma-channels = <8>; 959 block-number = <1>; 960 block-offset = <0x10000>; 961 fsl,dma-queues = <2>; 962 status-sizes = <64>; 963 queue-sizes = <64 64>; 964 big-endian; 965 }; 966 967 rcpm: wakeup-controller@1ee2140 { 968 compatible = "fsl,ls1046a-rcpm", "fsl,qoriq-rcpm-2.1+"; 969 reg = <0x0 0x1ee2140 0x0 0x4>; 970 #fsl,rcpm-wakeup-cells = <1>; 971 }; 972 973 ftm_alarm0: rtc@29d0000 { 974 compatible = "fsl,ls1046a-ftm-alarm"; 975 reg = <0x0 0x29d0000 0x0 0x10000>; 976 fsl,rcpm-wakeup = <&rcpm 0x20000>; 977 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 978 big-endian; 979 }; 980 }; 981 982 reserved-memory { 983 #address-cells = <2>; 984 #size-cells = <2>; 985 ranges; 986 987 bman_fbpr: bman-fbpr { 988 compatible = "shared-dma-pool"; 989 size = <0 0x1000000>; 990 alignment = <0 0x1000000>; 991 no-map; 992 }; 993 994 qman_fqd: qman-fqd { 995 compatible = "shared-dma-pool"; 996 size = <0 0x800000>; 997 alignment = <0 0x800000>; 998 no-map; 999 }; 1000 1001 qman_pfdr: qman-pfdr { 1002 compatible = "shared-dma-pool"; 1003 size = <0 0x2000000>; 1004 alignment = <0 0x2000000>; 1005 no-map; 1006 }; 1007 }; 1008 1009 firmware { 1010 optee { 1011 compatible = "linaro,optee-tz"; 1012 method = "smc"; 1013 }; 1014 }; 1015}; 1016 1017#include "qoriq-qman-portals.dtsi" 1018#include "qoriq-bman-portals.dtsi"
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