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fsl-ls1043a.dtsi
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linux-6.19.14/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Include file for NXP Layerscape-1043A family SoC. 4 * 5 * Copyright 2014-2015 Freescale Semiconductor, Inc. 6 * Copyright 2018, 2020 NXP 7 * 8 * Mingkai Hu <Mingkai.hu@freescale.com> 9 */ 10 11#include <dt-bindings/clock/fsl,qoriq-clockgen.h> 12#include <dt-bindings/thermal/thermal.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/gpio/gpio.h> 15 16/ { 17 compatible = "fsl,ls1043a"; 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 crypto = &crypto; 24 fman0 = &fman0; 25 ethernet0 = &enet0; 26 ethernet1 = &enet1; 27 ethernet2 = &enet2; 28 ethernet3 = &enet3; 29 ethernet4 = &enet4; 30 ethernet5 = &enet5; 31 ethernet6 = &enet6; 32 rtc1 = &ftm_alarm0; 33 }; 34 35 cpus { 36 #address-cells = <1>; 37 #size-cells = <0>; 38 39 /* 40 * We expect the enable-method for cpu's to be "psci", but this 41 * is dependent on the SoC FW, which will fill this in. 42 * 43 * Currently supported enable-method is psci v0.2 44 */ 45 cpu0: cpu@0 { 46 device_type = "cpu"; 47 compatible = "arm,cortex-a53"; 48 reg = <0x0>; 49 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 50 next-level-cache = <&l2>; 51 cpu-idle-states = <&CPU_PH20>; 52 #cooling-cells = <2>; 53 }; 54 55 cpu1: cpu@1 { 56 device_type = "cpu"; 57 compatible = "arm,cortex-a53"; 58 reg = <0x1>; 59 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 60 next-level-cache = <&l2>; 61 cpu-idle-states = <&CPU_PH20>; 62 #cooling-cells = <2>; 63 }; 64 65 cpu2: cpu@2 { 66 device_type = "cpu"; 67 compatible = "arm,cortex-a53"; 68 reg = <0x2>; 69 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 70 next-level-cache = <&l2>; 71 cpu-idle-states = <&CPU_PH20>; 72 #cooling-cells = <2>; 73 }; 74 75 cpu3: cpu@3 { 76 device_type = "cpu"; 77 compatible = "arm,cortex-a53"; 78 reg = <0x3>; 79 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 80 next-level-cache = <&l2>; 81 cpu-idle-states = <&CPU_PH20>; 82 #cooling-cells = <2>; 83 }; 84 85 l2: l2-cache { 86 compatible = "cache"; 87 cache-level = <2>; 88 cache-unified; 89 }; 90 }; 91 92 idle-states { 93 /* 94 * PSCI node is not added default, U-boot will add missing 95 * parts if it determines to use PSCI. 96 */ 97 entry-method = "psci"; 98 99 CPU_PH20: cpu-ph20 { 100 compatible = "arm,idle-state"; 101 idle-state-name = "PH20"; 102 arm,psci-suspend-param = <0x0>; 103 entry-latency-us = <1000>; 104 exit-latency-us = <1000>; 105 min-residency-us = <3000>; 106 }; 107 }; 108 109 memory@80000000 { 110 device_type = "memory"; 111 reg = <0x0 0x80000000 0 0x80000000>; 112 /* DRAM space 1, size: 2GiB DRAM */ 113 }; 114 115 reserved-memory { 116 #address-cells = <2>; 117 #size-cells = <2>; 118 ranges; 119 120 bman_fbpr: bman-fbpr { 121 compatible = "shared-dma-pool"; 122 size = <0 0x1000000>; 123 alignment = <0 0x1000000>; 124 no-map; 125 }; 126 127 qman_fqd: qman-fqd { 128 compatible = "shared-dma-pool"; 129 size = <0 0x400000>; 130 alignment = <0 0x400000>; 131 no-map; 132 }; 133 134 qman_pfdr: qman-pfdr { 135 compatible = "shared-dma-pool"; 136 size = <0 0x2000000>; 137 alignment = <0 0x2000000>; 138 no-map; 139 }; 140 }; 141 142 sysclk: sysclk { 143 compatible = "fixed-clock"; 144 #clock-cells = <0>; 145 clock-frequency = <100000000>; 146 clock-output-names = "sysclk"; 147 }; 148 149 reboot { 150 compatible = "syscon-reboot"; 151 regmap = <&dcfg>; 152 offset = <0xb0>; 153 mask = <0x02>; 154 }; 155 156 thermal-zones { 157 ddr-thermal { 158 polling-delay-passive = <1000>; 159 polling-delay = <5000>; 160 thermal-sensors = <&tmu 0>; 161 162 trips { 163 ddr-ctrler-alert { 164 temperature = <85000>; 165 hysteresis = <2000>; 166 type = "passive"; 167 }; 168 169 ddr-ctrler-crit { 170 temperature = <95000>; 171 hysteresis = <2000>; 172 type = "critical"; 173 }; 174 }; 175 }; 176 177 serdes-thermal { 178 polling-delay-passive = <1000>; 179 polling-delay = <5000>; 180 thermal-sensors = <&tmu 1>; 181 182 trips { 183 serdes-alert { 184 temperature = <85000>; 185 hysteresis = <2000>; 186 type = "passive"; 187 }; 188 189 serdes-crit { 190 temperature = <95000>; 191 hysteresis = <2000>; 192 type = "critical"; 193 }; 194 }; 195 }; 196 197 fman-thermal { 198 polling-delay-passive = <1000>; 199 polling-delay = <5000>; 200 thermal-sensors = <&tmu 2>; 201 202 trips { 203 fman-alert { 204 temperature = <85000>; 205 hysteresis = <2000>; 206 type = "passive"; 207 }; 208 209 fman-crit { 210 temperature = <95000>; 211 hysteresis = <2000>; 212 type = "critical"; 213 }; 214 }; 215 }; 216 217 cluster-thermal { 218 polling-delay-passive = <1000>; 219 polling-delay = <5000>; 220 thermal-sensors = <&tmu 3>; 221 222 trips { 223 core_cluster_alert: core-cluster-alert { 224 temperature = <85000>; 225 hysteresis = <2000>; 226 type = "passive"; 227 }; 228 229 core_cluster_crit: core-cluster-crit { 230 temperature = <95000>; 231 hysteresis = <2000>; 232 type = "critical"; 233 }; 234 }; 235 236 cooling-maps { 237 map0 { 238 trip = <&core_cluster_alert>; 239 cooling-device = 240 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 241 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 242 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 243 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 244 }; 245 }; 246 }; 247 248 sec-thermal { 249 polling-delay-passive = <1000>; 250 polling-delay = <5000>; 251 thermal-sensors = <&tmu 4>; 252 253 trips { 254 sec-alert { 255 temperature = <85000>; 256 hysteresis = <2000>; 257 type = "passive"; 258 }; 259 260 sec-crit { 261 temperature = <95000>; 262 hysteresis = <2000>; 263 type = "critical"; 264 }; 265 }; 266 }; 267 }; 268 269 timer { 270 compatible = "arm,armv8-timer"; 271 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 272 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 273 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 274 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 275 fsl,erratum-a008585; 276 }; 277 278 pmu { 279 compatible = "arm,cortex-a53-pmu"; 280 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 281 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 282 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 283 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 284 interrupt-affinity = <&cpu0>, 285 <&cpu1>, 286 <&cpu2>, 287 <&cpu3>; 288 }; 289 290 gic: interrupt-controller@1400000 { 291 compatible = "arm,gic-400"; 292 #address-cells = <0>; 293 #interrupt-cells = <3>; 294 interrupt-controller; 295 reg = <0x0 0x1401000 0 0x1000>, /* GICD */ 296 <0x0 0x1402000 0 0x2000>, /* GICC */ 297 <0x0 0x1404000 0 0x2000>, /* GICH */ 298 <0x0 0x1406000 0 0x2000>; /* GICV */ 299 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 300 }; 301 302 soc: soc { 303 compatible = "simple-bus"; 304 #address-cells = <2>; 305 #size-cells = <2>; 306 ranges; 307 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; 308 dma-coherent; 309 310 clockgen: clocking@1ee1000 { 311 compatible = "fsl,ls1043a-clockgen"; 312 reg = <0x0 0x1ee1000 0x0 0x1000>; 313 #clock-cells = <2>; 314 clocks = <&sysclk>; 315 }; 316 317 scfg: scfg@1570000 { 318 compatible = "fsl,ls1043a-scfg", "syscon"; 319 reg = <0x0 0x1570000 0x0 0x10000>; 320 big-endian; 321 #address-cells = <1>; 322 #size-cells = <1>; 323 ranges = <0x0 0x0 0x1570000 0x10000>; 324 325 extirq: interrupt-controller@1ac { 326 compatible = "fsl,ls1043a-extirq"; 327 #interrupt-cells = <2>; 328 #address-cells = <0>; 329 interrupt-controller; 330 reg = <0x1ac 4>; 331 interrupt-map = 332 <0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 333 <1 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 334 <2 0 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 335 <3 0 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 336 <4 0 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 337 <5 0 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 338 <6 0 &gic GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 339 <7 0 &gic GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 340 <8 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 341 <9 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 342 <10 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 343 <11 0 &gic GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 344 interrupt-map-mask = <0xf 0x0>; 345 }; 346 }; 347 348 crypto: crypto@1700000 { 349 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0", 350 "fsl,sec-v4.0"; 351 fsl,sec-era = <3>; 352 #address-cells = <1>; 353 #size-cells = <1>; 354 ranges = <0x0 0x00 0x1700000 0x100000>; 355 reg = <0x00 0x1700000 0x0 0x100000>; 356 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 357 dma-coherent; 358 359 sec_jr0: jr@10000 { 360 compatible = "fsl,sec-v5.4-job-ring", 361 "fsl,sec-v5.0-job-ring", 362 "fsl,sec-v4.0-job-ring"; 363 reg = <0x10000 0x10000>; 364 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 365 }; 366 367 sec_jr1: jr@20000 { 368 compatible = "fsl,sec-v5.4-job-ring", 369 "fsl,sec-v5.0-job-ring", 370 "fsl,sec-v4.0-job-ring"; 371 reg = <0x20000 0x10000>; 372 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 373 }; 374 375 sec_jr2: jr@30000 { 376 compatible = "fsl,sec-v5.4-job-ring", 377 "fsl,sec-v5.0-job-ring", 378 "fsl,sec-v4.0-job-ring"; 379 reg = <0x30000 0x10000>; 380 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 381 }; 382 383 sec_jr3: jr@40000 { 384 compatible = "fsl,sec-v5.4-job-ring", 385 "fsl,sec-v5.0-job-ring", 386 "fsl,sec-v4.0-job-ring"; 387 reg = <0x40000 0x10000>; 388 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 389 }; 390 }; 391 392 sfp: efuse@1e80000 { 393 compatible = "fsl,ls1021a-sfp"; 394 reg = <0x0 0x1e80000 0x0 0x10000>; 395 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 396 QORIQ_CLK_PLL_DIV(4)>; 397 clock-names = "sfp"; 398 }; 399 400 dcfg: dcfg@1ee0000 { 401 compatible = "fsl,ls1043a-dcfg", "syscon"; 402 reg = <0x0 0x1ee0000 0x0 0x1000>; 403 big-endian; 404 }; 405 406 ifc: memory-controller@1530000 { 407 compatible = "fsl,ifc"; 408 reg = <0x0 0x1530000 0x0 0x10000>; 409 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 410 }; 411 412 qspi: spi@1550000 { 413 compatible = "fsl,ls1043a-qspi", "fsl,ls1021a-qspi"; 414 #address-cells = <1>; 415 #size-cells = <0>; 416 reg = <0x0 0x1550000 0x0 0x10000>, 417 <0x0 0x40000000 0x0 0x4000000>; 418 reg-names = "QuadSPI", "QuadSPI-memory"; 419 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 420 clock-names = "qspi_en", "qspi"; 421 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 422 QORIQ_CLK_PLL_DIV(1)>, 423 <&clockgen QORIQ_CLK_PLATFORM_PLL 424 QORIQ_CLK_PLL_DIV(1)>; 425 status = "disabled"; 426 }; 427 428 esdhc: mmc@1560000 { 429 compatible = "fsl,ls1043a-esdhc", "fsl,esdhc"; 430 reg = <0x0 0x1560000 0x0 0x10000>; 431 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 432 clock-frequency = <0>; 433 voltage-ranges = <1800 1800 3300 3300>; 434 sdhci,auto-cmd12; 435 bus-width = <4>; 436 }; 437 438 ddr: memory-controller@1080000 { 439 compatible = "fsl,qoriq-memory-controller"; 440 reg = <0x0 0x1080000 0x0 0x1000>; 441 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 442 }; 443 444 tmu: tmu@1f00000 { 445 compatible = "fsl,qoriq-tmu"; 446 reg = <0x0 0x1f00000 0x0 0x10000>; 447 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 448 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>; 449 fsl,tmu-calibration = 450 <0x00000000 0x00000023>, 451 <0x00000001 0x0000002a>, 452 <0x00000002 0x00000031>, 453 <0x00000003 0x00000037>, 454 <0x00000004 0x0000003e>, 455 <0x00000005 0x00000044>, 456 <0x00000006 0x0000004b>, 457 <0x00000007 0x00000051>, 458 <0x00000008 0x00000058>, 459 <0x00000009 0x0000005e>, 460 <0x0000000a 0x00000065>, 461 <0x0000000b 0x0000006b>, 462 463 <0x00010000 0x00000023>, 464 <0x00010001 0x0000002b>, 465 <0x00010002 0x00000033>, 466 <0x00010003 0x0000003b>, 467 <0x00010004 0x00000043>, 468 <0x00010005 0x0000004b>, 469 <0x00010006 0x00000054>, 470 <0x00010007 0x0000005c>, 471 <0x00010008 0x00000064>, 472 <0x00010009 0x0000006c>, 473 474 <0x00020000 0x00000021>, 475 <0x00020001 0x0000002c>, 476 <0x00020002 0x00000036>, 477 <0x00020003 0x00000040>, 478 <0x00020004 0x0000004b>, 479 <0x00020005 0x00000055>, 480 <0x00020006 0x0000005f>, 481 482 <0x00030000 0x00000013>, 483 <0x00030001 0x0000001d>, 484 <0x00030002 0x00000028>, 485 <0x00030003 0x00000032>, 486 <0x00030004 0x0000003d>, 487 <0x00030005 0x00000047>, 488 <0x00030006 0x00000052>, 489 <0x00030007 0x0000005c>; 490 #thermal-sensor-cells = <1>; 491 }; 492 493 qman: qman@1880000 { 494 compatible = "fsl,qman"; 495 reg = <0x0 0x1880000 0x0 0x10000>; 496 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 497 memory-region = <&qman_fqd &qman_pfdr>; 498 }; 499 500 bman: bman@1890000 { 501 compatible = "fsl,bman"; 502 reg = <0x0 0x1890000 0x0 0x10000>; 503 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 504 memory-region = <&bman_fbpr>; 505 }; 506 507 bportals: bman-portals-bus@508000000 { 508 ranges = <0x0 0x5 0x08000000 0x8000000>; 509 }; 510 511 qportals: qman-portals-bus@500000000 { 512 ranges = <0x0 0x5 0x00000000 0x8000000>; 513 }; 514 515 dspi0: spi@2100000 { 516 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi"; 517 #address-cells = <1>; 518 #size-cells = <0>; 519 reg = <0x0 0x2100000 0x0 0x10000>; 520 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 521 clock-names = "dspi"; 522 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 523 QORIQ_CLK_PLL_DIV(1)>; 524 spi-num-chipselects = <5>; 525 big-endian; 526 status = "disabled"; 527 }; 528 529 i2c0: i2c@2180000 { 530 compatible = "fsl,ls1043a-i2c", "fsl,vf610-i2c"; 531 #address-cells = <1>; 532 #size-cells = <0>; 533 reg = <0x0 0x2180000 0x0 0x10000>; 534 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 535 clock-names = "ipg"; 536 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 537 QORIQ_CLK_PLL_DIV(1)>; 538 dmas = <&edma0 1 38>, 539 <&edma0 1 39>; 540 dma-names = "rx", "tx"; 541 status = "disabled"; 542 }; 543 544 i2c1: i2c@2190000 { 545 compatible = "fsl,ls1043a-i2c", "fsl,vf610-i2c"; 546 #address-cells = <1>; 547 #size-cells = <0>; 548 reg = <0x0 0x2190000 0x0 0x10000>; 549 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 550 clock-names = "ipg"; 551 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 552 QORIQ_CLK_PLL_DIV(1)>; 553 scl-gpios = <&gpio4 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 554 dmas = <&edma0 1 36>, 555 <&edma0 1 37>; 556 dma-names = "rx", "tx"; 557 status = "disabled"; 558 }; 559 560 i2c2: i2c@21a0000 { 561 compatible = "fsl,ls1043a-i2c", "fsl,vf610-i2c"; 562 #address-cells = <1>; 563 #size-cells = <0>; 564 reg = <0x0 0x21a0000 0x0 0x10000>; 565 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 566 clock-names = "ipg"; 567 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 568 QORIQ_CLK_PLL_DIV(1)>; 569 scl-gpios = <&gpio4 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 570 dmas = <&edma0 1 34>, 571 <&edma0 1 35>; 572 dma-names = "rx", "tx"; 573 status = "disabled"; 574 }; 575 576 i2c3: i2c@21b0000 { 577 compatible = "fsl,ls1043a-i2c", "fsl,vf610-i2c"; 578 #address-cells = <1>; 579 #size-cells = <0>; 580 reg = <0x0 0x21b0000 0x0 0x10000>; 581 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 582 clock-names = "ipg"; 583 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 584 QORIQ_CLK_PLL_DIV(1)>; 585 scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 586 dmas = <&edma0 1 40>, 587 <&edma0 1 41>; 588 dma-names = "rx", "tx"; 589 status = "disabled"; 590 }; 591 592 duart0: serial@21c0500 { 593 compatible = "fsl,ns16550", "ns16550a"; 594 reg = <0x00 0x21c0500 0x0 0x100>; 595 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 596 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 597 QORIQ_CLK_PLL_DIV(1)>; 598 }; 599 600 duart1: serial@21c0600 { 601 compatible = "fsl,ns16550", "ns16550a"; 602 reg = <0x00 0x21c0600 0x0 0x100>; 603 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 604 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 605 QORIQ_CLK_PLL_DIV(1)>; 606 }; 607 608 duart2: serial@21d0500 { 609 compatible = "fsl,ns16550", "ns16550a"; 610 reg = <0x0 0x21d0500 0x0 0x100>; 611 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 612 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 613 QORIQ_CLK_PLL_DIV(1)>; 614 }; 615 616 duart3: serial@21d0600 { 617 compatible = "fsl,ns16550", "ns16550a"; 618 reg = <0x0 0x21d0600 0x0 0x100>; 619 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 620 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 621 QORIQ_CLK_PLL_DIV(1)>; 622 }; 623 624 gpio1: gpio@2300000 { 625 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; 626 reg = <0x0 0x2300000 0x0 0x10000>; 627 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 628 gpio-controller; 629 #gpio-cells = <2>; 630 interrupt-controller; 631 #interrupt-cells = <2>; 632 }; 633 634 gpio2: gpio@2310000 { 635 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; 636 reg = <0x0 0x2310000 0x0 0x10000>; 637 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 638 gpio-controller; 639 #gpio-cells = <2>; 640 interrupt-controller; 641 #interrupt-cells = <2>; 642 }; 643 644 gpio3: gpio@2320000 { 645 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; 646 reg = <0x0 0x2320000 0x0 0x10000>; 647 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 648 gpio-controller; 649 #gpio-cells = <2>; 650 interrupt-controller; 651 #interrupt-cells = <2>; 652 }; 653 654 gpio4: gpio@2330000 { 655 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; 656 reg = <0x0 0x2330000 0x0 0x10000>; 657 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 658 gpio-controller; 659 #gpio-cells = <2>; 660 interrupt-controller; 661 #interrupt-cells = <2>; 662 }; 663 664 uqe: uqe-bus@2400000 { 665 #address-cells = <1>; 666 #size-cells = <1>; 667 compatible = "fsl,qe", "simple-bus"; 668 ranges = <0x0 0x0 0x2400000 0x40000>; 669 reg = <0x0 0x2400000 0x0 0x480>; 670 brg-frequency = <100000000>; 671 bus-frequency = <200000000>; 672 fsl,qe-num-riscs = <1>; 673 fsl,qe-num-snums = <28>; 674 675 qeic: qeic@80 { 676 compatible = "fsl,qe-ic"; 677 reg = <0x80 0x80>; 678 interrupt-controller; 679 #interrupt-cells = <1>; 680 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 681 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 682 }; 683 684 si1: si@700 { 685 compatible = "fsl,ls1043-qe-si", 686 "fsl,t1040-qe-si"; 687 reg = <0x700 0x80>; 688 }; 689 690 siram1: siram@1000 { 691 compatible = "fsl,ls1043-qe-siram", 692 "fsl,t1040-qe-siram"; 693 reg = <0x1000 0x800>; 694 }; 695 696 ucc@2000 { 697 cell-index = <1>; 698 reg = <0x2000 0x200>; 699 interrupts = <32>; 700 interrupt-parent = <&qeic>; 701 }; 702 703 ucc@2200 { 704 cell-index = <3>; 705 reg = <0x2200 0x200>; 706 interrupts = <34>; 707 interrupt-parent = <&qeic>; 708 }; 709 710 muram@10000 { 711 #address-cells = <1>; 712 #size-cells = <1>; 713 compatible = "fsl,qe-muram", "fsl,cpm-muram"; 714 ranges = <0x0 0x10000 0x6000>; 715 716 data-only@0 { 717 compatible = "fsl,qe-muram-data", 718 "fsl,cpm-muram-data"; 719 reg = <0x0 0x6000>; 720 }; 721 }; 722 }; 723 724 lpuart0: serial@2950000 { 725 compatible = "fsl,ls1021a-lpuart"; 726 reg = <0x0 0x2950000 0x0 0x1000>; 727 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 728 clocks = <&clockgen QORIQ_CLK_SYSCLK 0>; 729 clock-names = "ipg"; 730 dmas = <&edma0 1 32>, 731 <&edma0 1 33>; 732 dma-names = "rx", "tx"; 733 status = "disabled"; 734 }; 735 736 lpuart1: serial@2960000 { 737 compatible = "fsl,ls1021a-lpuart"; 738 reg = <0x0 0x2960000 0x0 0x1000>; 739 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 740 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 741 QORIQ_CLK_PLL_DIV(1)>; 742 clock-names = "ipg"; 743 dmas = <&edma0 1 30>, 744 <&edma0 1 31>; 745 dma-names = "rx", "tx"; 746 status = "disabled"; 747 }; 748 749 lpuart2: serial@2970000 { 750 compatible = "fsl,ls1021a-lpuart"; 751 reg = <0x0 0x2970000 0x0 0x1000>; 752 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 753 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 754 QORIQ_CLK_PLL_DIV(1)>; 755 clock-names = "ipg"; 756 dmas = <&edma0 1 28>, 757 <&edma0 1 29>; 758 dma-names = "rx", "tx"; 759 status = "disabled"; 760 }; 761 762 lpuart3: serial@2980000 { 763 compatible = "fsl,ls1021a-lpuart"; 764 reg = <0x0 0x2980000 0x0 0x1000>; 765 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 766 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 767 QORIQ_CLK_PLL_DIV(1)>; 768 clock-names = "ipg"; 769 dmas = <&edma0 1 26>, 770 <&edma0 1 27>; 771 dma-names = "rx", "tx"; 772 status = "disabled"; 773 }; 774 775 lpuart4: serial@2990000 { 776 compatible = "fsl,ls1021a-lpuart"; 777 reg = <0x0 0x2990000 0x0 0x1000>; 778 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 779 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 780 QORIQ_CLK_PLL_DIV(1)>; 781 clock-names = "ipg"; 782 dmas = <&edma0 1 24>, 783 <&edma0 1 25>; 784 dma-names = "rx", "tx"; 785 status = "disabled"; 786 }; 787 788 lpuart5: serial@29a0000 { 789 compatible = "fsl,ls1021a-lpuart"; 790 reg = <0x0 0x29a0000 0x0 0x1000>; 791 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 792 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 793 QORIQ_CLK_PLL_DIV(1)>; 794 clock-names = "ipg"; 795 dmas = <&edma0 1 22>, 796 <&edma0 1 23>; 797 dma-names = "rx", "tx"; 798 status = "disabled"; 799 }; 800 801 wdog0: watchdog@2ad0000 { 802 compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt"; 803 reg = <0x0 0x2ad0000 0x0 0x10000>; 804 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 805 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 806 QORIQ_CLK_PLL_DIV(1)>; 807 big-endian; 808 }; 809 810 edma0: dma-controller@2c00000 { 811 #dma-cells = <2>; 812 compatible = "fsl,vf610-edma"; 813 reg = <0x0 0x2c00000 0x0 0x10000>, 814 <0x0 0x2c10000 0x0 0x10000>, 815 <0x0 0x2c20000 0x0 0x10000>; 816 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 817 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 818 interrupt-names = "edma-tx", "edma-err"; 819 dma-channels = <32>; 820 big-endian; 821 clock-names = "dmamux0", "dmamux1"; 822 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 823 QORIQ_CLK_PLL_DIV(1)>, 824 <&clockgen QORIQ_CLK_PLATFORM_PLL 825 QORIQ_CLK_PLL_DIV(1)>; 826 }; 827 828 aux_bus: bus { 829 #address-cells = <2>; 830 #size-cells = <2>; 831 compatible = "simple-bus"; 832 ranges; 833 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x00000000>; 834 835 usb0: usb@2f00000 { 836 compatible = "fsl,ls1043a-dwc3", "fsl,ls1028a-dwc3"; 837 reg = <0x0 0x2f00000 0x0 0x10000>; 838 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 839 dr_mode = "host"; 840 dma-coherent; 841 snps,quirk-frame-length-adjustment = <0x20>; 842 snps,dis_rxdet_inp3_quirk; 843 usb3-lpm-capable; 844 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 845 status = "disabled"; 846 }; 847 848 usb1: usb@3000000 { 849 compatible = "fsl,ls1043a-dwc3", "fsl,ls1028a-dwc3"; 850 reg = <0x0 0x3000000 0x0 0x10000>; 851 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 852 dr_mode = "host"; 853 dma-coherent; 854 snps,quirk-frame-length-adjustment = <0x20>; 855 snps,dis_rxdet_inp3_quirk; 856 usb3-lpm-capable; 857 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 858 status = "disabled"; 859 }; 860 861 usb2: usb@3100000 { 862 compatible = "fsl,ls1043a-dwc3", "fsl,ls1028a-dwc3"; 863 reg = <0x0 0x3100000 0x0 0x10000>; 864 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 865 dr_mode = "host"; 866 dma-coherent; 867 snps,quirk-frame-length-adjustment = <0x20>; 868 snps,dis_rxdet_inp3_quirk; 869 usb3-lpm-capable; 870 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 871 status = "disabled"; 872 }; 873 874 sata: sata@3200000 { 875 compatible = "fsl,ls1043a-ahci"; 876 reg = <0x0 0x3200000 0x0 0x10000>, 877 <0x0 0x20140520 0x0 0x4>; 878 reg-names = "ahci", "sata-ecc"; 879 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 880 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 881 QORIQ_CLK_PLL_DIV(1)>; 882 dma-coherent; 883 }; 884 }; 885 886 msi1: msi-controller1@1571000 { 887 compatible = "fsl,ls1043a-msi"; 888 reg = <0x0 0x1571000 0x0 0x8>; 889 msi-controller; 890 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 891 }; 892 893 msi2: msi-controller2@1572000 { 894 compatible = "fsl,ls1043a-msi"; 895 reg = <0x0 0x1572000 0x0 0x8>; 896 msi-controller; 897 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 898 }; 899 900 msi3: msi-controller3@1573000 { 901 compatible = "fsl,ls1043a-msi"; 902 reg = <0x0 0x1573000 0x0 0x8>; 903 msi-controller; 904 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 905 }; 906 907 pcie1: pcie@3400000 { 908 compatible = "fsl,ls1043a-pcie"; 909 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ 910 <0x40 0x00000000 0x0 0x00002000>; /* configuration space */ 911 reg-names = "regs", "config"; 912 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 913 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 914 interrupt-names = "pme", "aer"; 915 #address-cells = <3>; 916 #size-cells = <2>; 917 device_type = "pci"; 918 num-viewport = <6>; 919 bus-range = <0x0 0xff>; 920 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ 921 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 922 msi-parent = <&msi1>, <&msi2>, <&msi3>; 923 #interrupt-cells = <1>; 924 interrupt-map-mask = <0 0 0 7>; 925 interrupt-map = <0000 0 0 1 &gic 0 110 0x4>, 926 <0000 0 0 2 &gic 0 111 0x4>, 927 <0000 0 0 3 &gic 0 112 0x4>, 928 <0000 0 0 4 &gic 0 113 0x4>; 929 fsl,pcie-scfg = <&scfg 0>; 930 big-endian; 931 status = "disabled"; 932 }; 933 934 pcie2: pcie@3500000 { 935 compatible = "fsl,ls1043a-pcie"; 936 reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ 937 <0x48 0x00000000 0x0 0x00002000>; /* configuration space */ 938 reg-names = "regs", "config"; 939 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 940 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 941 interrupt-names = "pme", "aer"; 942 #address-cells = <3>; 943 #size-cells = <2>; 944 device_type = "pci"; 945 num-viewport = <6>; 946 bus-range = <0x0 0xff>; 947 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ 948 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 949 msi-parent = <&msi1>, <&msi2>, <&msi3>; 950 #interrupt-cells = <1>; 951 interrupt-map-mask = <0 0 0 7>; 952 interrupt-map = <0000 0 0 1 &gic 0 120 0x4>, 953 <0000 0 0 2 &gic 0 121 0x4>, 954 <0000 0 0 3 &gic 0 122 0x4>, 955 <0000 0 0 4 &gic 0 123 0x4>; 956 fsl,pcie-scfg = <&scfg 1>; 957 big-endian; 958 status = "disabled"; 959 }; 960 961 pcie3: pcie@3600000 { 962 compatible = "fsl,ls1043a-pcie"; 963 reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */ 964 <0x50 0x00000000 0x0 0x00002000>; /* configuration space */ 965 reg-names = "regs", "config"; 966 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 967 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 968 interrupt-names = "pme", "aer"; 969 #address-cells = <3>; 970 #size-cells = <2>; 971 device_type = "pci"; 972 num-viewport = <6>; 973 bus-range = <0x0 0xff>; 974 ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */ 975 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 976 msi-parent = <&msi1>, <&msi2>, <&msi3>; 977 #interrupt-cells = <1>; 978 interrupt-map-mask = <0 0 0 7>; 979 interrupt-map = <0000 0 0 1 &gic 0 154 0x4>, 980 <0000 0 0 2 &gic 0 155 0x4>, 981 <0000 0 0 3 &gic 0 156 0x4>, 982 <0000 0 0 4 &gic 0 157 0x4>; 983 fsl,pcie-scfg = <&scfg 2>; 984 big-endian; 985 status = "disabled"; 986 }; 987 988 qdma: dma-controller@8380000 { 989 compatible = "fsl,ls1043a-qdma", "fsl,ls1021a-qdma"; 990 reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */ 991 <0x0 0x8390000 0x0 0x10000>, /* Status regs */ 992 <0x0 0x83a0000 0x0 0x40000>; /* Block regs */ 993 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 994 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 995 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 996 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 997 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 998 interrupt-names = "qdma-error", "qdma-queue0", 999 "qdma-queue1", "qdma-queue2", "qdma-queue3"; 1000 #dma-cells = <1>; 1001 dma-channels = <8>; 1002 block-number = <1>; 1003 block-offset = <0x10000>; 1004 fsl,dma-queues = <2>; 1005 status-sizes = <64>; 1006 queue-sizes = <64 64>; 1007 big-endian; 1008 }; 1009 1010 rcpm: wakeup-controller@1ee2140 { 1011 compatible = "fsl,ls1043a-rcpm", "fsl,qoriq-rcpm-2.1+"; 1012 reg = <0x0 0x1ee2140 0x0 0x4>; 1013 #fsl,rcpm-wakeup-cells = <1>; 1014 }; 1015 1016 ftm_alarm0: rtc@29d0000 { 1017 compatible = "fsl,ls1043a-ftm-alarm"; 1018 reg = <0x0 0x29d0000 0x0 0x10000>; 1019 fsl,rcpm-wakeup = <&rcpm 0x20000>; 1020 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1021 big-endian; 1022 }; 1023 }; 1024 1025 firmware { 1026 optee { 1027 compatible = "linaro,optee-tz"; 1028 method = "smc"; 1029 }; 1030 }; 1031 1032}; 1033 1034#include "qoriq-qman-portals.dtsi" 1035#include "qoriq-bman-portals.dtsi"
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