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fsl-ls1028a.dtsi
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linux-6.19.14/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Include file for NXP Layerscape-1028A family SoC. 4 * 5 * Copyright 2018-2020 NXP 6 * 7 * Harninder Rai <harninder.rai@nxp.com> 8 * 9 */ 10 11#include <dt-bindings/clock/fsl,qoriq-clockgen.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 compatible = "fsl,ls1028a"; 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 cpus { 22 #address-cells = <1>; 23 #size-cells = <0>; 24 25 cpu0: cpu@0 { 26 device_type = "cpu"; 27 compatible = "arm,cortex-a72"; 28 reg = <0x0>; 29 enable-method = "psci"; 30 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 31 i-cache-size = <0xc000>; 32 i-cache-line-size = <64>; 33 i-cache-sets = <256>; 34 d-cache-size = <0x8000>; 35 d-cache-line-size = <64>; 36 d-cache-sets = <256>; 37 next-level-cache = <&l2>; 38 cpu-idle-states = <&CPU_PW20>; 39 #cooling-cells = <2>; 40 }; 41 42 cpu1: cpu@1 { 43 device_type = "cpu"; 44 compatible = "arm,cortex-a72"; 45 reg = <0x1>; 46 enable-method = "psci"; 47 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 48 i-cache-size = <0xc000>; 49 i-cache-line-size = <64>; 50 i-cache-sets = <256>; 51 d-cache-size = <0x8000>; 52 d-cache-line-size = <64>; 53 d-cache-sets = <256>; 54 next-level-cache = <&l2>; 55 cpu-idle-states = <&CPU_PW20>; 56 #cooling-cells = <2>; 57 }; 58 59 l2: l2-cache { 60 compatible = "cache"; 61 cache-level = <2>; 62 cache-unified; 63 cache-size = <0x100000>; 64 cache-line-size = <64>; 65 cache-sets = <1024>; 66 }; 67 }; 68 69 idle-states { 70 /* 71 * PSCI node is not added default, U-boot will add missing 72 * parts if it determines to use PSCI. 73 */ 74 entry-method = "psci"; 75 76 CPU_PW20: cpu-pw20 { 77 compatible = "arm,idle-state"; 78 idle-state-name = "PW20"; 79 arm,psci-suspend-param = <0x0>; 80 entry-latency-us = <2000>; 81 exit-latency-us = <2000>; 82 min-residency-us = <6000>; 83 }; 84 }; 85 86 rtc_clk: rtc-clk { 87 compatible = "fixed-clock"; 88 #clock-cells = <0>; 89 clock-frequency = <32768>; 90 clock-output-names = "rtc_clk"; 91 }; 92 93 sysclk: sysclk { 94 compatible = "fixed-clock"; 95 #clock-cells = <0>; 96 clock-frequency = <100000000>; 97 clock-output-names = "sysclk"; 98 }; 99 100 osc_27m: clock-osc-27m { 101 compatible = "fixed-clock"; 102 #clock-cells = <0>; 103 clock-frequency = <27000000>; 104 clock-output-names = "phy_27m"; 105 }; 106 107 firmware { 108 optee: optee { 109 compatible = "linaro,optee-tz"; 110 method = "smc"; 111 status = "disabled"; 112 }; 113 }; 114 115 timer { 116 compatible = "arm,armv8-timer"; 117 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | 118 IRQ_TYPE_LEVEL_LOW)>, 119 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | 120 IRQ_TYPE_LEVEL_LOW)>, 121 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | 122 IRQ_TYPE_LEVEL_LOW)>, 123 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | 124 IRQ_TYPE_LEVEL_LOW)>; 125 }; 126 127 pmu { 128 compatible = "arm,cortex-a72-pmu"; 129 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 130 }; 131 132 gic: interrupt-controller@6000000 { 133 compatible = "arm,gic-v3"; 134 #address-cells = <2>; 135 #size-cells = <2>; 136 ranges; 137 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 138 <0x0 0x06040000 0 0x40000>; /* GIC Redistributor */ 139 #interrupt-cells = <3>; 140 interrupt-controller; 141 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) | 142 IRQ_TYPE_LEVEL_LOW)>; 143 its: msi-controller@6020000 { 144 compatible = "arm,gic-v3-its"; 145 msi-controller; 146 #msi-cells = <1>; 147 reg = <0x0 0x06020000 0 0x20000>;/* GIC Translater */ 148 }; 149 }; 150 151 thermal-zones { 152 ddr-thermal { 153 polling-delay-passive = <1000>; 154 polling-delay = <5000>; 155 thermal-sensors = <&tmu 0>; 156 157 trips { 158 ddr-ctrler-alert { 159 temperature = <85000>; 160 hysteresis = <2000>; 161 type = "passive"; 162 }; 163 164 ddr-ctrler-crit { 165 temperature = <95000>; 166 hysteresis = <2000>; 167 type = "critical"; 168 }; 169 }; 170 }; 171 172 cluster-thermal { 173 polling-delay-passive = <1000>; 174 polling-delay = <5000>; 175 thermal-sensors = <&tmu 1>; 176 177 trips { 178 core_cluster_alert: core-cluster-alert { 179 temperature = <85000>; 180 hysteresis = <2000>; 181 type = "passive"; 182 }; 183 184 core_cluster_crit: core-cluster-crit { 185 temperature = <95000>; 186 hysteresis = <2000>; 187 type = "critical"; 188 }; 189 }; 190 191 cooling-maps { 192 map0 { 193 trip = <&core_cluster_alert>; 194 cooling-device = 195 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 196 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 197 }; 198 }; 199 }; 200 }; 201 202 soc: soc { 203 compatible = "simple-bus"; 204 #address-cells = <2>; 205 #size-cells = <2>; 206 ranges; 207 208 ddr: memory-controller@1080000 { 209 compatible = "fsl,qoriq-memory-controller"; 210 reg = <0x0 0x1080000 0x0 0x1000>; 211 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 212 little-endian; 213 }; 214 215 dcfg: syscon@1e00000 { 216 #address-cells = <1>; 217 #size-cells = <1>; 218 compatible = "fsl,ls1028a-dcfg", "syscon", "simple-mfd"; 219 reg = <0x0 0x1e00000 0x0 0x10000>; 220 ranges = <0x0 0x0 0x1e00000 0x10000>; 221 little-endian; 222 223 fspi_clk: clock-controller@900 { 224 compatible = "fsl,ls1028a-flexspi-clk"; 225 reg = <0x900 0x4>; 226 #clock-cells = <0>; 227 clocks = <&clockgen QORIQ_CLK_HWACCEL 0>; 228 clock-output-names = "fspi_clk"; 229 }; 230 }; 231 232 syscon@1e60000 { 233 compatible = "fsl,ls1028a-reset", "syscon", "simple-mfd"; 234 reg = <0x0 0x1e60000 0x0 0x10000>; 235 little-endian; 236 237 reboot { 238 compatible = "syscon-reboot"; 239 offset = <0>; 240 mask = <0x02>; 241 }; 242 }; 243 244 sfp: efuse@1e80000 { 245 compatible = "fsl,ls1028a-sfp"; 246 reg = <0x0 0x1e80000 0x0 0x10000>; 247 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 248 QORIQ_CLK_PLL_DIV(4)>; 249 clock-names = "sfp"; 250 #address-cells = <1>; 251 #size-cells = <1>; 252 253 ls1028a_uid: unique-id@1c { 254 reg = <0x1c 0x8>; 255 }; 256 }; 257 258 scfg: syscon@1fc0000 { 259 compatible = "fsl,ls1028a-scfg", "syscon"; 260 reg = <0x0 0x1fc0000 0x0 0x10000>; 261 big-endian; 262 }; 263 264 clockgen: clock-controller@1300000 { 265 compatible = "fsl,ls1028a-clockgen"; 266 reg = <0x0 0x1300000 0x0 0xa0000>; 267 #clock-cells = <2>; 268 clocks = <&sysclk>; 269 }; 270 271 i2c0: i2c@2000000 { 272 compatible = "fsl,vf610-i2c"; 273 #address-cells = <1>; 274 #size-cells = <0>; 275 reg = <0x0 0x2000000 0x0 0x10000>; 276 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 277 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 278 QORIQ_CLK_PLL_DIV(4)>; 279 status = "disabled"; 280 }; 281 282 i2c1: i2c@2010000 { 283 compatible = "fsl,vf610-i2c"; 284 #address-cells = <1>; 285 #size-cells = <0>; 286 reg = <0x0 0x2010000 0x0 0x10000>; 287 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 288 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 289 QORIQ_CLK_PLL_DIV(4)>; 290 status = "disabled"; 291 }; 292 293 i2c2: i2c@2020000 { 294 compatible = "fsl,vf610-i2c"; 295 #address-cells = <1>; 296 #size-cells = <0>; 297 reg = <0x0 0x2020000 0x0 0x10000>; 298 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 299 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 300 QORIQ_CLK_PLL_DIV(4)>; 301 status = "disabled"; 302 }; 303 304 i2c3: i2c@2030000 { 305 compatible = "fsl,vf610-i2c"; 306 #address-cells = <1>; 307 #size-cells = <0>; 308 reg = <0x0 0x2030000 0x0 0x10000>; 309 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 310 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 311 QORIQ_CLK_PLL_DIV(4)>; 312 status = "disabled"; 313 }; 314 315 i2c4: i2c@2040000 { 316 compatible = "fsl,vf610-i2c"; 317 #address-cells = <1>; 318 #size-cells = <0>; 319 reg = <0x0 0x2040000 0x0 0x10000>; 320 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 321 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 322 QORIQ_CLK_PLL_DIV(4)>; 323 status = "disabled"; 324 }; 325 326 i2c5: i2c@2050000 { 327 compatible = "fsl,vf610-i2c"; 328 #address-cells = <1>; 329 #size-cells = <0>; 330 reg = <0x0 0x2050000 0x0 0x10000>; 331 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 332 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 333 QORIQ_CLK_PLL_DIV(4)>; 334 status = "disabled"; 335 }; 336 337 i2c6: i2c@2060000 { 338 compatible = "fsl,vf610-i2c"; 339 #address-cells = <1>; 340 #size-cells = <0>; 341 reg = <0x0 0x2060000 0x0 0x10000>; 342 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 343 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 344 QORIQ_CLK_PLL_DIV(4)>; 345 status = "disabled"; 346 }; 347 348 i2c7: i2c@2070000 { 349 compatible = "fsl,vf610-i2c"; 350 #address-cells = <1>; 351 #size-cells = <0>; 352 reg = <0x0 0x2070000 0x0 0x10000>; 353 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 354 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 355 QORIQ_CLK_PLL_DIV(4)>; 356 status = "disabled"; 357 }; 358 359 fspi: spi@20c0000 { 360 compatible = "nxp,lx2160a-fspi"; 361 #address-cells = <1>; 362 #size-cells = <0>; 363 reg = <0x0 0x20c0000 0x0 0x10000>, 364 <0x0 0x20000000 0x0 0x10000000>; 365 reg-names = "fspi_base", "fspi_mmap"; 366 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 367 clocks = <&fspi_clk>, <&fspi_clk>; 368 clock-names = "fspi_en", "fspi"; 369 status = "disabled"; 370 }; 371 372 dspi0: spi@2100000 { 373 compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; 374 #address-cells = <1>; 375 #size-cells = <0>; 376 reg = <0x0 0x2100000 0x0 0x10000>; 377 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 378 clock-names = "dspi"; 379 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 380 QORIQ_CLK_PLL_DIV(2)>; 381 dmas = <&edma0 0 62>, <&edma0 0 60>; 382 dma-names = "tx", "rx"; 383 spi-num-chipselects = <4>; 384 status = "disabled"; 385 }; 386 387 dspi1: spi@2110000 { 388 compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; 389 #address-cells = <1>; 390 #size-cells = <0>; 391 reg = <0x0 0x2110000 0x0 0x10000>; 392 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 393 clock-names = "dspi"; 394 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 395 QORIQ_CLK_PLL_DIV(2)>; 396 dmas = <&edma0 0 58>, <&edma0 0 56>; 397 dma-names = "tx", "rx"; 398 spi-num-chipselects = <4>; 399 status = "disabled"; 400 }; 401 402 dspi2: spi@2120000 { 403 compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; 404 #address-cells = <1>; 405 #size-cells = <0>; 406 reg = <0x0 0x2120000 0x0 0x10000>; 407 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 408 clock-names = "dspi"; 409 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 410 QORIQ_CLK_PLL_DIV(2)>; 411 dmas = <&edma0 0 54>, <&edma0 0 2>; 412 dma-names = "tx", "rx"; 413 spi-num-chipselects = <3>; 414 status = "disabled"; 415 }; 416 417 esdhc: mmc@2140000 { 418 compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; 419 reg = <0x0 0x2140000 0x0 0x10000>; 420 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 421 clock-frequency = <0>; /* fixed up by bootloader */ 422 clocks = <&clockgen QORIQ_CLK_HWACCEL 1>; 423 voltage-ranges = <1800 1800 3300 3300>; 424 sdhci,auto-cmd12; 425 little-endian; 426 bus-width = <4>; 427 status = "disabled"; 428 }; 429 430 esdhc1: mmc@2150000 { 431 compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; 432 reg = <0x0 0x2150000 0x0 0x10000>; 433 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 434 clock-frequency = <0>; /* fixed up by bootloader */ 435 clocks = <&clockgen QORIQ_CLK_HWACCEL 1>; 436 voltage-ranges = <1800 1800>; 437 sdhci,auto-cmd12; 438 non-removable; 439 little-endian; 440 bus-width = <4>; 441 status = "disabled"; 442 }; 443 444 can0: can@2180000 { 445 compatible = "fsl,lx2160ar1-flexcan"; 446 reg = <0x0 0x2180000 0x0 0x10000>; 447 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 448 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 449 QORIQ_CLK_PLL_DIV(2)>, 450 <&clockgen QORIQ_CLK_PLATFORM_PLL 451 QORIQ_CLK_PLL_DIV(2)>; 452 clock-names = "ipg", "per"; 453 status = "disabled"; 454 }; 455 456 can1: can@2190000 { 457 compatible = "fsl,lx2160ar1-flexcan"; 458 reg = <0x0 0x2190000 0x0 0x10000>; 459 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 460 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 461 QORIQ_CLK_PLL_DIV(2)>, 462 <&clockgen QORIQ_CLK_PLATFORM_PLL 463 QORIQ_CLK_PLL_DIV(2)>; 464 clock-names = "ipg", "per"; 465 status = "disabled"; 466 }; 467 468 duart0: serial@21c0500 { 469 compatible = "fsl,ns16550", "ns16550a"; 470 reg = <0x00 0x21c0500 0x0 0x100>; 471 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 472 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 473 QORIQ_CLK_PLL_DIV(2)>; 474 status = "disabled"; 475 }; 476 477 duart1: serial@21c0600 { 478 compatible = "fsl,ns16550", "ns16550a"; 479 reg = <0x00 0x21c0600 0x0 0x100>; 480 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 481 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 482 QORIQ_CLK_PLL_DIV(2)>; 483 status = "disabled"; 484 }; 485 486 487 lpuart0: serial@2260000 { 488 compatible = "fsl,ls1028a-lpuart"; 489 reg = <0x0 0x2260000 0x0 0x1000>; 490 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 491 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 492 QORIQ_CLK_PLL_DIV(2)>; 493 clock-names = "ipg"; 494 dma-names = "rx","tx"; 495 dmas = <&edma0 1 32>, 496 <&edma0 1 33>; 497 status = "disabled"; 498 }; 499 500 lpuart1: serial@2270000 { 501 compatible = "fsl,ls1028a-lpuart"; 502 reg = <0x0 0x2270000 0x0 0x1000>; 503 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 504 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 505 QORIQ_CLK_PLL_DIV(2)>; 506 clock-names = "ipg"; 507 dma-names = "rx","tx"; 508 dmas = <&edma0 1 30>, 509 <&edma0 1 31>; 510 status = "disabled"; 511 }; 512 513 lpuart2: serial@2280000 { 514 compatible = "fsl,ls1028a-lpuart"; 515 reg = <0x0 0x2280000 0x0 0x1000>; 516 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 517 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 518 QORIQ_CLK_PLL_DIV(2)>; 519 clock-names = "ipg"; 520 dma-names = "rx","tx"; 521 dmas = <&edma0 1 28>, 522 <&edma0 1 29>; 523 status = "disabled"; 524 }; 525 526 lpuart3: serial@2290000 { 527 compatible = "fsl,ls1028a-lpuart"; 528 reg = <0x0 0x2290000 0x0 0x1000>; 529 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 530 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 531 QORIQ_CLK_PLL_DIV(2)>; 532 clock-names = "ipg"; 533 dma-names = "rx","tx"; 534 dmas = <&edma0 1 26>, 535 <&edma0 1 27>; 536 status = "disabled"; 537 }; 538 539 lpuart4: serial@22a0000 { 540 compatible = "fsl,ls1028a-lpuart"; 541 reg = <0x0 0x22a0000 0x0 0x1000>; 542 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; 543 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 544 QORIQ_CLK_PLL_DIV(2)>; 545 clock-names = "ipg"; 546 dma-names = "rx","tx"; 547 dmas = <&edma0 1 24>, 548 <&edma0 1 25>; 549 status = "disabled"; 550 }; 551 552 lpuart5: serial@22b0000 { 553 compatible = "fsl,ls1028a-lpuart"; 554 reg = <0x0 0x22b0000 0x0 0x1000>; 555 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 556 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 557 QORIQ_CLK_PLL_DIV(2)>; 558 clock-names = "ipg"; 559 dma-names = "rx","tx"; 560 dmas = <&edma0 1 22>, 561 <&edma0 1 23>; 562 status = "disabled"; 563 }; 564 565 edma0: dma-controller@22c0000 { 566 #dma-cells = <2>; 567 compatible = "fsl,ls1028a-edma", "fsl,vf610-edma"; 568 reg = <0x0 0x22c0000 0x0 0x10000>, 569 <0x0 0x22d0000 0x0 0x10000>, 570 <0x0 0x22e0000 0x0 0x10000>; 571 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 573 interrupt-names = "edma-tx", "edma-err"; 574 dma-channels = <32>; 575 clock-names = "dmamux0", "dmamux1"; 576 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 577 QORIQ_CLK_PLL_DIV(2)>, 578 <&clockgen QORIQ_CLK_PLATFORM_PLL 579 QORIQ_CLK_PLL_DIV(2)>; 580 }; 581 582 gpio1: gpio@2300000 { 583 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 584 reg = <0x0 0x2300000 0x0 0x10000>; 585 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 586 gpio-controller; 587 #gpio-cells = <2>; 588 interrupt-controller; 589 #interrupt-cells = <2>; 590 little-endian; 591 }; 592 593 gpio2: gpio@2310000 { 594 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 595 reg = <0x0 0x2310000 0x0 0x10000>; 596 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 597 gpio-controller; 598 #gpio-cells = <2>; 599 interrupt-controller; 600 #interrupt-cells = <2>; 601 little-endian; 602 }; 603 604 gpio3: gpio@2320000 { 605 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 606 reg = <0x0 0x2320000 0x0 0x10000>; 607 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 608 gpio-controller; 609 #gpio-cells = <2>; 610 interrupt-controller; 611 #interrupt-cells = <2>; 612 little-endian; 613 }; 614 615 usb0: usb@3100000 { 616 compatible = "fsl,ls1028a-dwc3"; 617 reg = <0x0 0x3100000 0x0 0x10000>; 618 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 619 iommus = <&smmu 1>; 620 dma-coherent; 621 snps,dis_rxdet_inp3_quirk; 622 snps,quirk-frame-length-adjustment = <0x20>; 623 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 624 status = "disabled"; 625 }; 626 627 usb1: usb@3110000 { 628 compatible = "fsl,ls1028a-dwc3"; 629 reg = <0x0 0x3110000 0x0 0x10000>; 630 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 631 iommus = <&smmu 2>; 632 dma-coherent; 633 snps,dis_rxdet_inp3_quirk; 634 snps,quirk-frame-length-adjustment = <0x20>; 635 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 636 status = "disabled"; 637 }; 638 639 sata: sata@3200000 { 640 compatible = "fsl,ls1028a-ahci"; 641 reg = <0x0 0x3200000 0x0 0x10000>, 642 <0x7 0x100520 0x0 0x4>; 643 reg-names = "ahci", "sata-ecc"; 644 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 645 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 646 QORIQ_CLK_PLL_DIV(2)>; 647 status = "disabled"; 648 }; 649 650 pcie1: pcie@3400000 { 651 compatible = "fsl,ls1028a-pcie"; 652 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ 653 <0x80 0x00000000 0x0 0x00002000>; /* configuration space */ 654 reg-names = "regs", "config"; 655 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 656 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ 657 interrupt-names = "pme", "aer"; 658 #address-cells = <3>; 659 #size-cells = <2>; 660 device_type = "pci"; 661 dma-coherent; 662 num-viewport = <8>; 663 bus-range = <0x0 0xff>; 664 ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000 /* downstream I/O */ 665 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 666 msi-parent = <&its 0>; 667 #interrupt-cells = <1>; 668 interrupt-map-mask = <0 0 0 7>; 669 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 670 <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 671 <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 672 <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 673 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 674 status = "disabled"; 675 }; 676 677 pcie_ep1: pcie-ep@3400000 { 678 compatible = "fsl,ls1028a-pcie-ep"; 679 reg = <0x00 0x03400000 0x0 0x00100000 680 0x80 0x00000000 0x8 0x00000000>; 681 reg-names = "regs", "addr_space"; 682 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */ 683 interrupt-names = "pme"; 684 num-ib-windows = <6>; 685 num-ob-windows = <8>; 686 status = "disabled"; 687 }; 688 689 pcie2: pcie@3500000 { 690 compatible = "fsl,ls1028a-pcie"; 691 reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ 692 <0x88 0x00000000 0x0 0x00002000>; /* configuration space */ 693 reg-names = "regs", "config"; 694 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 695 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 696 interrupt-names = "pme", "aer"; 697 #address-cells = <3>; 698 #size-cells = <2>; 699 device_type = "pci"; 700 dma-coherent; 701 num-viewport = <8>; 702 bus-range = <0x0 0xff>; 703 ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000 /* downstream I/O */ 704 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 705 msi-parent = <&its 0>; 706 #interrupt-cells = <1>; 707 interrupt-map-mask = <0 0 0 7>; 708 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 709 <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 710 <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 711 <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 712 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 713 status = "disabled"; 714 }; 715 716 pcie_ep2: pcie-ep@3500000 { 717 compatible = "fsl,ls1028a-pcie-ep"; 718 reg = <0x00 0x03500000 0x0 0x00100000 719 0x88 0x00000000 0x8 0x00000000>; 720 reg-names = "regs", "addr_space"; 721 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */ 722 interrupt-names = "pme"; 723 num-ib-windows = <6>; 724 num-ob-windows = <8>; 725 status = "disabled"; 726 }; 727 728 smmu: iommu@5000000 { 729 compatible = "arm,mmu-500"; 730 reg = <0 0x5000000 0 0x800000>; 731 #global-interrupts = <8>; 732 #iommu-cells = <1>; 733 dma-coherent; 734 stream-match-mask = <0x7c00>; 735 /* global secure fault */ 736 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 737 /* combined secure interrupt */ 738 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 739 /* global non-secure fault */ 740 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 741 /* combined non-secure interrupt */ 742 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 743 /* performance counter interrupts 0-7 */ 744 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 745 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 746 /* per context interrupt, 64 interrupts */ 747 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 748 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 749 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 750 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 751 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 752 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 753 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 754 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 755 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 756 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 757 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 758 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 759 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 760 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 761 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 762 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 763 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 764 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 765 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 766 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 767 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 768 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 769 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 770 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 771 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 772 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 773 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 774 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 775 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 776 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 777 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 778 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 779 }; 780 781 crypto: crypto@8000000 { 782 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 783 fsl,sec-era = <10>; 784 #address-cells = <1>; 785 #size-cells = <1>; 786 ranges = <0x0 0x00 0x8000000 0x100000>; 787 reg = <0x00 0x8000000 0x0 0x100000>; 788 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 789 dma-coherent; 790 791 sec_jr0: jr@10000 { 792 compatible = "fsl,sec-v5.0-job-ring", 793 "fsl,sec-v4.0-job-ring"; 794 reg = <0x10000 0x10000>; 795 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 796 }; 797 798 sec_jr1: jr@20000 { 799 compatible = "fsl,sec-v5.0-job-ring", 800 "fsl,sec-v4.0-job-ring"; 801 reg = <0x20000 0x10000>; 802 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 803 }; 804 805 sec_jr2: jr@30000 { 806 compatible = "fsl,sec-v5.0-job-ring", 807 "fsl,sec-v4.0-job-ring"; 808 reg = <0x30000 0x10000>; 809 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 810 }; 811 812 sec_jr3: jr@40000 { 813 compatible = "fsl,sec-v5.0-job-ring", 814 "fsl,sec-v4.0-job-ring"; 815 reg = <0x40000 0x10000>; 816 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 817 }; 818 }; 819 820 qdma: dma-controller@8380000 { 821 compatible = "fsl,ls1028a-qdma", "fsl,ls1021a-qdma"; 822 reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */ 823 <0x0 0x8390000 0x0 0x10000>, /* Status regs */ 824 <0x0 0x83a0000 0x0 0x40000>; /* Block regs */ 825 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 826 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 827 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 828 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 829 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; 830 interrupt-names = "qdma-error", "qdma-queue0", 831 "qdma-queue1", "qdma-queue2", "qdma-queue3"; 832 #dma-cells = <1>; 833 dma-channels = <8>; 834 block-number = <1>; 835 block-offset = <0x10000>; 836 fsl,dma-queues = <2>; 837 status-sizes = <64>; 838 queue-sizes = <64 64>; 839 }; 840 841 cluster1_core0_watchdog: watchdog@c000000 { 842 compatible = "arm,sp805", "arm,primecell"; 843 reg = <0x0 0xc000000 0x0 0x1000>; 844 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 845 QORIQ_CLK_PLL_DIV(16)>, 846 <&clockgen QORIQ_CLK_PLATFORM_PLL 847 QORIQ_CLK_PLL_DIV(16)>; 848 clock-names = "wdog_clk", "apb_pclk"; 849 }; 850 851 cluster1_core1_watchdog: watchdog@c010000 { 852 compatible = "arm,sp805", "arm,primecell"; 853 reg = <0x0 0xc010000 0x0 0x1000>; 854 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 855 QORIQ_CLK_PLL_DIV(16)>, 856 <&clockgen QORIQ_CLK_PLATFORM_PLL 857 QORIQ_CLK_PLL_DIV(16)>; 858 clock-names = "wdog_clk", "apb_pclk"; 859 }; 860 861 malidp0: display@f080000 { 862 compatible = "arm,mali-dp500"; 863 reg = <0x0 0xf080000 0x0 0x10000>; 864 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, 865 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 866 interrupt-names = "DE", "SE"; 867 clocks = <&dpclk>, 868 <&clockgen QORIQ_CLK_HWACCEL 2>, 869 <&clockgen QORIQ_CLK_HWACCEL 2>, 870 <&clockgen QORIQ_CLK_HWACCEL 2>; 871 clock-names = "pxlclk", "mclk", "aclk", "pclk"; 872 arm,malidp-output-port-lines = /bits/ 8 <8 8 8>; 873 arm,malidp-arqos-value = <0xd000d000>; 874 875 port { 876 dpi0_out: endpoint { 877 878 }; 879 }; 880 }; 881 882 gpu: gpu@f0c0000 { 883 compatible = "vivante,gc"; 884 reg = <0x0 0xf0c0000 0x0 0x10000>; 885 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 886 clocks = <&clockgen QORIQ_CLK_HWACCEL 2>, 887 <&clockgen QORIQ_CLK_HWACCEL 2>, 888 <&clockgen QORIQ_CLK_HWACCEL 2>; 889 clock-names = "core", "shader", "bus"; 890 #cooling-cells = <2>; 891 }; 892 893 sai1: audio-controller@f100000 { 894 #sound-dai-cells = <0>; 895 compatible = "fsl,vf610-sai"; 896 reg = <0x0 0xf100000 0x0 0x10000>; 897 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 898 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 899 QORIQ_CLK_PLL_DIV(2)>, 900 <&clockgen QORIQ_CLK_PLATFORM_PLL 901 QORIQ_CLK_PLL_DIV(2)>, 902 <&clockgen QORIQ_CLK_PLATFORM_PLL 903 QORIQ_CLK_PLL_DIV(2)>, 904 <&clockgen QORIQ_CLK_PLATFORM_PLL 905 QORIQ_CLK_PLL_DIV(2)>; 906 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 907 dma-names = "rx", "tx"; 908 dmas = <&edma0 1 3>, 909 <&edma0 1 4>; 910 fsl,sai-asynchronous; 911 status = "disabled"; 912 }; 913 914 sai2: audio-controller@f110000 { 915 #sound-dai-cells = <0>; 916 compatible = "fsl,vf610-sai"; 917 reg = <0x0 0xf110000 0x0 0x10000>; 918 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 919 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 920 QORIQ_CLK_PLL_DIV(2)>, 921 <&clockgen QORIQ_CLK_PLATFORM_PLL 922 QORIQ_CLK_PLL_DIV(2)>, 923 <&clockgen QORIQ_CLK_PLATFORM_PLL 924 QORIQ_CLK_PLL_DIV(2)>, 925 <&clockgen QORIQ_CLK_PLATFORM_PLL 926 QORIQ_CLK_PLL_DIV(2)>; 927 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 928 dma-names = "rx", "tx"; 929 dmas = <&edma0 1 5>, 930 <&edma0 1 6>; 931 fsl,sai-asynchronous; 932 status = "disabled"; 933 }; 934 935 sai3: audio-controller@f120000 { 936 #sound-dai-cells = <0>; 937 compatible = "fsl,vf610-sai"; 938 reg = <0x0 0xf120000 0x0 0x10000>; 939 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 940 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 941 QORIQ_CLK_PLL_DIV(2)>, 942 <&clockgen QORIQ_CLK_PLATFORM_PLL 943 QORIQ_CLK_PLL_DIV(2)>, 944 <&clockgen QORIQ_CLK_PLATFORM_PLL 945 QORIQ_CLK_PLL_DIV(2)>, 946 <&clockgen QORIQ_CLK_PLATFORM_PLL 947 QORIQ_CLK_PLL_DIV(2)>; 948 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 949 dma-names = "rx", "tx"; 950 dmas = <&edma0 1 7>, 951 <&edma0 1 8>; 952 fsl,sai-asynchronous; 953 status = "disabled"; 954 }; 955 956 sai4: audio-controller@f130000 { 957 #sound-dai-cells = <0>; 958 compatible = "fsl,vf610-sai"; 959 reg = <0x0 0xf130000 0x0 0x10000>; 960 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 961 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 962 QORIQ_CLK_PLL_DIV(2)>, 963 <&clockgen QORIQ_CLK_PLATFORM_PLL 964 QORIQ_CLK_PLL_DIV(2)>, 965 <&clockgen QORIQ_CLK_PLATFORM_PLL 966 QORIQ_CLK_PLL_DIV(2)>, 967 <&clockgen QORIQ_CLK_PLATFORM_PLL 968 QORIQ_CLK_PLL_DIV(2)>; 969 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 970 dma-names = "rx", "tx"; 971 dmas = <&edma0 1 9>, 972 <&edma0 1 10>; 973 fsl,sai-asynchronous; 974 status = "disabled"; 975 }; 976 977 sai5: audio-controller@f140000 { 978 #sound-dai-cells = <0>; 979 compatible = "fsl,vf610-sai"; 980 reg = <0x0 0xf140000 0x0 0x10000>; 981 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 982 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 983 QORIQ_CLK_PLL_DIV(2)>, 984 <&clockgen QORIQ_CLK_PLATFORM_PLL 985 QORIQ_CLK_PLL_DIV(2)>, 986 <&clockgen QORIQ_CLK_PLATFORM_PLL 987 QORIQ_CLK_PLL_DIV(2)>, 988 <&clockgen QORIQ_CLK_PLATFORM_PLL 989 QORIQ_CLK_PLL_DIV(2)>; 990 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 991 dma-names = "rx", "tx"; 992 dmas = <&edma0 1 11>, 993 <&edma0 1 12>; 994 fsl,sai-asynchronous; 995 status = "disabled"; 996 }; 997 998 sai6: audio-controller@f150000 { 999 #sound-dai-cells = <0>; 1000 compatible = "fsl,vf610-sai"; 1001 reg = <0x0 0xf150000 0x0 0x10000>; 1002 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1003 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1004 QORIQ_CLK_PLL_DIV(2)>, 1005 <&clockgen QORIQ_CLK_PLATFORM_PLL 1006 QORIQ_CLK_PLL_DIV(2)>, 1007 <&clockgen QORIQ_CLK_PLATFORM_PLL 1008 QORIQ_CLK_PLL_DIV(2)>, 1009 <&clockgen QORIQ_CLK_PLATFORM_PLL 1010 QORIQ_CLK_PLL_DIV(2)>; 1011 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 1012 dma-names = "rx", "tx"; 1013 dmas = <&edma0 1 13>, 1014 <&edma0 1 14>; 1015 fsl,sai-asynchronous; 1016 status = "disabled"; 1017 }; 1018 1019 dpclk: clock-controller@f1f0000 { 1020 compatible = "fsl,ls1028a-plldig"; 1021 reg = <0x0 0xf1f0000 0x0 0x10000>; 1022 #clock-cells = <0>; 1023 clocks = <&osc_27m>; 1024 }; 1025 1026 tmu: tmu@1f80000 { 1027 compatible = "fsl,qoriq-tmu"; 1028 reg = <0x0 0x1f80000 0x0 0x10000>; 1029 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1030 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; 1031 fsl,tmu-calibration = 1032 <0x00000000 0x00000024>, 1033 <0x00000001 0x0000002b>, 1034 <0x00000002 0x00000031>, 1035 <0x00000003 0x00000038>, 1036 <0x00000004 0x0000003f>, 1037 <0x00000005 0x00000045>, 1038 <0x00000006 0x0000004c>, 1039 <0x00000007 0x00000053>, 1040 <0x00000008 0x00000059>, 1041 <0x00000009 0x00000060>, 1042 <0x0000000a 0x00000066>, 1043 <0x0000000b 0x0000006d>, 1044 1045 <0x00010000 0x0000001c>, 1046 <0x00010001 0x00000024>, 1047 <0x00010002 0x0000002c>, 1048 <0x00010003 0x00000035>, 1049 <0x00010004 0x0000003d>, 1050 <0x00010005 0x00000045>, 1051 <0x00010006 0x0000004d>, 1052 <0x00010007 0x00000055>, 1053 <0x00010008 0x0000005e>, 1054 <0x00010009 0x00000066>, 1055 <0x0001000a 0x0000006e>, 1056 1057 <0x00020000 0x00000018>, 1058 <0x00020001 0x00000022>, 1059 <0x00020002 0x0000002d>, 1060 <0x00020003 0x00000038>, 1061 <0x00020004 0x00000043>, 1062 <0x00020005 0x0000004d>, 1063 <0x00020006 0x00000058>, 1064 <0x00020007 0x00000063>, 1065 <0x00020008 0x0000006e>, 1066 1067 <0x00030000 0x00000010>, 1068 <0x00030001 0x0000001c>, 1069 <0x00030002 0x00000029>, 1070 <0x00030003 0x00000036>, 1071 <0x00030004 0x00000042>, 1072 <0x00030005 0x0000004f>, 1073 <0x00030006 0x0000005b>, 1074 <0x00030007 0x00000068>; 1075 little-endian; 1076 #thermal-sensor-cells = <1>; 1077 }; 1078 1079 pcie@1f0000000 { /* Integrated Endpoint Root Complex */ 1080 compatible = "pci-host-ecam-generic"; 1081 reg = <0x01 0xf0000000 0x0 0x100000>; 1082 #address-cells = <3>; 1083 #size-cells = <2>; 1084 msi-parent = <&its 0>; 1085 device_type = "pci"; 1086 bus-range = <0x0 0x0>; 1087 dma-coherent; 1088 msi-map = <0 &its 0x17 0xe>; 1089 iommu-map = <0 &smmu 0x17 0xe>; 1090 /* PF0-6 BAR0 - non-prefetchable memory */ 1091 ranges = <0x82000000 0x1 0xf8000000 0x1 0xf8000000 0x0 0x160000 1092 /* PF0-6 BAR2 - prefetchable memory */ 1093 0xc2000000 0x1 0xf8160000 0x1 0xf8160000 0x0 0x070000 1094 /* PF0: VF0-1 BAR0 - non-prefetchable memory */ 1095 0x82000000 0x1 0xf81d0000 0x1 0xf81d0000 0x0 0x020000 1096 /* PF0: VF0-1 BAR2 - prefetchable memory */ 1097 0xc2000000 0x1 0xf81f0000 0x1 0xf81f0000 0x0 0x020000 1098 /* PF1: VF0-1 BAR0 - non-prefetchable memory */ 1099 0x82000000 0x1 0xf8210000 0x1 0xf8210000 0x0 0x020000 1100 /* PF1: VF0-1 BAR2 - prefetchable memory */ 1101 0xc2000000 0x1 0xf8230000 0x1 0xf8230000 0x0 0x020000 1102 /* BAR4 (PF5) - non-prefetchable memory */ 1103 0x82000000 0x1 0xfc000000 0x1 0xfc000000 0x0 0x400000>; 1104 #interrupt-cells = <1>; 1105 interrupt-map-mask = <0 0 0 7>; 1106 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 1107 <0000 0 0 2 &gic 0 0 GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1108 1109 enetc_port0: ethernet@0,0 { 1110 compatible = "pci1957,e100", "fsl,enetc"; 1111 reg = <0x000000 0 0 0 0>; 1112 status = "disabled"; 1113 }; 1114 1115 enetc_port1: ethernet@0,1 { 1116 compatible = "pci1957,e100", "fsl,enetc"; 1117 reg = <0x000100 0 0 0 0>; 1118 status = "disabled"; 1119 }; 1120 1121 enetc_port2: ethernet@0,2 { 1122 compatible = "pci1957,e100", "fsl,enetc"; 1123 reg = <0x000200 0 0 0 0>; 1124 phy-mode = "internal"; 1125 status = "disabled"; 1126 1127 fixed-link { 1128 speed = <2500>; 1129 full-duplex; 1130 pause; 1131 }; 1132 }; 1133 1134 enetc_mdio_pf3: mdio@0,3 { 1135 compatible = "pci1957,ee01", "fsl,enetc-mdio"; 1136 reg = <0x000300 0 0 0 0>; 1137 #address-cells = <1>; 1138 #size-cells = <0>; 1139 }; 1140 1141 ethernet@0,4 { 1142 compatible = "pci1957,ee02", "fsl,enetc-ptp"; 1143 reg = <0x000400 0 0 0 0>; 1144 clocks = <&clockgen QORIQ_CLK_HWACCEL 3>; 1145 little-endian; 1146 fsl,extts-fifo; 1147 }; 1148 1149 mscc_felix: ethernet-switch@0,5 { 1150 reg = <0x000500 0 0 0 0>; 1151 /* IEP INT_B */ 1152 interrupts = <2>; 1153 status = "disabled"; 1154 1155 mscc_felix_ports: ports { 1156 #address-cells = <1>; 1157 #size-cells = <0>; 1158 1159 /* External ports */ 1160 mscc_felix_port0: port@0 { 1161 reg = <0>; 1162 status = "disabled"; 1163 }; 1164 1165 mscc_felix_port1: port@1 { 1166 reg = <1>; 1167 status = "disabled"; 1168 }; 1169 1170 mscc_felix_port2: port@2 { 1171 reg = <2>; 1172 status = "disabled"; 1173 }; 1174 1175 mscc_felix_port3: port@3 { 1176 reg = <3>; 1177 status = "disabled"; 1178 }; 1179 1180 /* Internal ports */ 1181 mscc_felix_port4: port@4 { 1182 reg = <4>; 1183 phy-mode = "internal"; 1184 ethernet = <&enetc_port2>; 1185 status = "disabled"; 1186 1187 fixed-link { 1188 speed = <2500>; 1189 full-duplex; 1190 pause; 1191 }; 1192 }; 1193 1194 mscc_felix_port5: port@5 { 1195 reg = <5>; 1196 phy-mode = "internal"; 1197 ethernet = <&enetc_port3>; 1198 status = "disabled"; 1199 1200 fixed-link { 1201 speed = <1000>; 1202 full-duplex; 1203 pause; 1204 }; 1205 }; 1206 }; 1207 }; 1208 1209 enetc_port3: ethernet@0,6 { 1210 compatible = "pci1957,e100", "fsl,enetc"; 1211 reg = <0x000600 0 0 0 0>; 1212 phy-mode = "internal"; 1213 status = "disabled"; 1214 1215 fixed-link { 1216 speed = <1000>; 1217 full-duplex; 1218 pause; 1219 }; 1220 }; 1221 1222 rcec@1f,0 { 1223 reg = <0x00f800 0 0 0 0>; 1224 /* IEP INT_A */ 1225 interrupts = <1>; 1226 }; 1227 }; 1228 1229 /* Integrated Endpoint Register Block */ 1230 ierb@1f0800000 { 1231 compatible = "fsl,ls1028a-enetc-ierb"; 1232 reg = <0x01 0xf0800000 0x0 0x10000>; 1233 }; 1234 1235 pwm0: pwm@2800000 { 1236 compatible = "fsl,vf610-ftm-pwm"; 1237 #pwm-cells = <3>; 1238 reg = <0x0 0x2800000 0x0 0x10000>; 1239 clock-names = "ftm_sys", "ftm_ext", 1240 "ftm_fix", "ftm_cnt_clk_en"; 1241 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 1242 <&rtc_clk>, <&clockgen 4 1>; 1243 status = "disabled"; 1244 }; 1245 1246 pwm1: pwm@2810000 { 1247 compatible = "fsl,vf610-ftm-pwm"; 1248 #pwm-cells = <3>; 1249 reg = <0x0 0x2810000 0x0 0x10000>; 1250 clock-names = "ftm_sys", "ftm_ext", 1251 "ftm_fix", "ftm_cnt_clk_en"; 1252 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 1253 <&rtc_clk>, <&clockgen 4 1>; 1254 status = "disabled"; 1255 }; 1256 1257 pwm2: pwm@2820000 { 1258 compatible = "fsl,vf610-ftm-pwm"; 1259 #pwm-cells = <3>; 1260 reg = <0x0 0x2820000 0x0 0x10000>; 1261 clock-names = "ftm_sys", "ftm_ext", 1262 "ftm_fix", "ftm_cnt_clk_en"; 1263 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 1264 <&rtc_clk>, <&clockgen 4 1>; 1265 status = "disabled"; 1266 }; 1267 1268 pwm3: pwm@2830000 { 1269 compatible = "fsl,vf610-ftm-pwm"; 1270 #pwm-cells = <3>; 1271 reg = <0x0 0x2830000 0x0 0x10000>; 1272 clock-names = "ftm_sys", "ftm_ext", 1273 "ftm_fix", "ftm_cnt_clk_en"; 1274 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 1275 <&rtc_clk>, <&clockgen 4 1>; 1276 status = "disabled"; 1277 }; 1278 1279 pwm4: pwm@2840000 { 1280 compatible = "fsl,vf610-ftm-pwm"; 1281 #pwm-cells = <3>; 1282 reg = <0x0 0x2840000 0x0 0x10000>; 1283 clock-names = "ftm_sys", "ftm_ext", 1284 "ftm_fix", "ftm_cnt_clk_en"; 1285 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 1286 <&rtc_clk>, <&clockgen 4 1>; 1287 status = "disabled"; 1288 }; 1289 1290 pwm5: pwm@2850000 { 1291 compatible = "fsl,vf610-ftm-pwm"; 1292 #pwm-cells = <3>; 1293 reg = <0x0 0x2850000 0x0 0x10000>; 1294 clock-names = "ftm_sys", "ftm_ext", 1295 "ftm_fix", "ftm_cnt_clk_en"; 1296 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 1297 <&rtc_clk>, <&clockgen 4 1>; 1298 status = "disabled"; 1299 }; 1300 1301 pwm6: pwm@2860000 { 1302 compatible = "fsl,vf610-ftm-pwm"; 1303 #pwm-cells = <3>; 1304 reg = <0x0 0x2860000 0x0 0x10000>; 1305 clock-names = "ftm_sys", "ftm_ext", 1306 "ftm_fix", "ftm_cnt_clk_en"; 1307 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 1308 <&rtc_clk>, <&clockgen 4 1>; 1309 status = "disabled"; 1310 }; 1311 1312 pwm7: pwm@2870000 { 1313 compatible = "fsl,vf610-ftm-pwm"; 1314 #pwm-cells = <3>; 1315 reg = <0x0 0x2870000 0x0 0x10000>; 1316 clock-names = "ftm_sys", "ftm_ext", 1317 "ftm_fix", "ftm_cnt_clk_en"; 1318 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 1319 <&rtc_clk>, <&clockgen 4 1>; 1320 status = "disabled"; 1321 }; 1322 1323 rcpm: wakeup-controller@1e34040 { 1324 compatible = "fsl,ls1028a-rcpm", "fsl,qoriq-rcpm-2.1+"; 1325 reg = <0x0 0x1e34040 0x0 0x1c>; 1326 #fsl,rcpm-wakeup-cells = <7>; 1327 little-endian; 1328 }; 1329 1330 ftm_alarm0: rtc@2800000 { 1331 compatible = "fsl,ls1028a-ftm-alarm"; 1332 reg = <0x0 0x2800000 0x0 0x10000>; 1333 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>; 1334 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1335 status = "disabled"; 1336 }; 1337 1338 ftm_alarm1: rtc@2810000 { 1339 compatible = "fsl,ls1028a-ftm-alarm"; 1340 reg = <0x0 0x2810000 0x0 0x10000>; 1341 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>; 1342 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1343 status = "disabled"; 1344 }; 1345 }; 1346 1347};
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