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fsl-ls1012a.dtsi
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linux-6.19.14/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Include file for NXP Layerscape-1012A family SoC. 4 * 5 * Copyright 2016 Freescale Semiconductor, Inc. 6 * Copyright 2019-2020 NXP 7 * 8 */ 9 10#include <dt-bindings/clock/fsl,qoriq-clockgen.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 compatible = "fsl,ls1012a"; 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 crypto = &crypto; 22 rtc1 = &ftm_alarm0; 23 rtic-a = &rtic_a; 24 rtic-b = &rtic_b; 25 rtic-c = &rtic_c; 26 rtic-d = &rtic_d; 27 sec-mon = &sec_mon; 28 }; 29 30 cpus { 31 #address-cells = <1>; 32 #size-cells = <0>; 33 34 cpu0: cpu@0 { 35 device_type = "cpu"; 36 compatible = "arm,cortex-a53"; 37 reg = <0x0>; 38 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 39 #cooling-cells = <2>; 40 cpu-idle-states = <&CPU_PH20>; 41 }; 42 }; 43 44 idle-states { 45 /* 46 * PSCI node is not added default, U-boot will add missing 47 * parts if it determines to use PSCI. 48 */ 49 entry-method = "psci"; 50 51 CPU_PH20: cpu-ph20 { 52 compatible = "arm,idle-state"; 53 idle-state-name = "PH20"; 54 arm,psci-suspend-param = <0x0>; 55 entry-latency-us = <1000>; 56 exit-latency-us = <1000>; 57 min-residency-us = <3000>; 58 }; 59 }; 60 61 sysclk: sysclk { 62 compatible = "fixed-clock"; 63 #clock-cells = <0>; 64 clock-frequency = <125000000>; 65 clock-output-names = "sysclk"; 66 }; 67 68 coreclk: coreclk { 69 compatible = "fixed-clock"; 70 #clock-cells = <0>; 71 clock-frequency = <100000000>; 72 clock-output-names = "coreclk"; 73 }; 74 75 timer { 76 compatible = "arm,armv8-timer"; 77 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */ 78 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */ 79 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */ 80 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */ 81 }; 82 83 pmu { 84 compatible = "arm,cortex-a53-pmu"; 85 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 86 }; 87 88 gic: interrupt-controller@1400000 { 89 compatible = "arm,gic-400"; 90 #address-cells = <0>; 91 #interrupt-cells = <3>; 92 interrupt-controller; 93 reg = <0x0 0x1401000 0 0x1000>, /* GICD */ 94 <0x0 0x1402000 0 0x2000>, /* GICC */ 95 <0x0 0x1404000 0 0x2000>, /* GICH */ 96 <0x0 0x1406000 0 0x2000>; /* GICV */ 97 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 98 }; 99 100 reboot { 101 compatible = "syscon-reboot"; 102 regmap = <&dcfg>; 103 offset = <0xb0>; 104 mask = <0x02>; 105 }; 106 107 thermal-zones { 108 cpu_thermal: cpu-thermal { 109 polling-delay-passive = <1000>; 110 polling-delay = <5000>; 111 thermal-sensors = <&tmu 0>; 112 113 trips { 114 cpu_alert: cpu-alert { 115 temperature = <85000>; 116 hysteresis = <2000>; 117 type = "passive"; 118 }; 119 120 cpu_crit: cpu-crit { 121 temperature = <95000>; 122 hysteresis = <2000>; 123 type = "critical"; 124 }; 125 }; 126 127 cooling-maps { 128 map0 { 129 trip = <&cpu_alert>; 130 cooling-device = 131 <&cpu0 THERMAL_NO_LIMIT 132 THERMAL_NO_LIMIT>; 133 }; 134 }; 135 }; 136 }; 137 138 soc { 139 compatible = "simple-bus"; 140 #address-cells = <2>; 141 #size-cells = <2>; 142 ranges; 143 144 qspi: spi@1550000 { 145 compatible = "fsl,ls1021a-qspi"; 146 #address-cells = <1>; 147 #size-cells = <0>; 148 reg = <0x0 0x1550000 0x0 0x10000>, 149 <0x0 0x40000000 0x0 0x10000000>; 150 reg-names = "QuadSPI", "QuadSPI-memory"; 151 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 152 clock-names = "qspi_en", "qspi"; 153 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 154 QORIQ_CLK_PLL_DIV(1)>, 155 <&clockgen QORIQ_CLK_PLATFORM_PLL 156 QORIQ_CLK_PLL_DIV(1)>; 157 status = "disabled"; 158 }; 159 160 esdhc0: mmc@1560000 { 161 compatible = "fsl,ls1012a-esdhc", "fsl,esdhc"; 162 reg = <0x0 0x1560000 0x0 0x10000>; 163 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 164 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 165 QORIQ_CLK_PLL_DIV(1)>; 166 voltage-ranges = <1800 1800 3300 3300>; 167 sdhci,auto-cmd12; 168 bus-width = <4>; 169 status = "disabled"; 170 }; 171 172 scfg: scfg@1570000 { 173 compatible = "fsl,ls1012a-scfg", "syscon"; 174 reg = <0x0 0x1570000 0x0 0x10000>; 175 big-endian; 176 }; 177 178 esdhc1: mmc@1580000 { 179 compatible = "fsl,ls1012a-esdhc", "fsl,esdhc"; 180 reg = <0x0 0x1580000 0x0 0x10000>; 181 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 182 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 183 QORIQ_CLK_PLL_DIV(1)>; 184 voltage-ranges = <1800 1800 3300 3300>; 185 sdhci,auto-cmd12; 186 broken-cd; 187 bus-width = <4>; 188 status = "disabled"; 189 }; 190 191 crypto: crypto@1700000 { 192 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0", 193 "fsl,sec-v4.0"; 194 fsl,sec-era = <8>; 195 #address-cells = <1>; 196 #size-cells = <1>; 197 ranges = <0x0 0x00 0x1700000 0x100000>; 198 reg = <0x00 0x1700000 0x0 0x100000>; 199 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 200 dma-coherent; 201 202 sec_jr0: jr@10000 { 203 compatible = "fsl,sec-v5.4-job-ring", 204 "fsl,sec-v5.0-job-ring", 205 "fsl,sec-v4.0-job-ring"; 206 reg = <0x10000 0x10000>; 207 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 208 }; 209 210 sec_jr1: jr@20000 { 211 compatible = "fsl,sec-v5.4-job-ring", 212 "fsl,sec-v5.0-job-ring", 213 "fsl,sec-v4.0-job-ring"; 214 reg = <0x20000 0x10000>; 215 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 216 }; 217 218 sec_jr2: jr@30000 { 219 compatible = "fsl,sec-v5.4-job-ring", 220 "fsl,sec-v5.0-job-ring", 221 "fsl,sec-v4.0-job-ring"; 222 reg = <0x30000 0x10000>; 223 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 224 }; 225 226 sec_jr3: jr@40000 { 227 compatible = "fsl,sec-v5.4-job-ring", 228 "fsl,sec-v5.0-job-ring", 229 "fsl,sec-v4.0-job-ring"; 230 reg = <0x40000 0x10000>; 231 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 232 }; 233 234 rtic@60000 { 235 compatible = "fsl,sec-v5.4-rtic", 236 "fsl,sec-v5.0-rtic", 237 "fsl,sec-v4.0-rtic"; 238 #address-cells = <1>; 239 #size-cells = <1>; 240 reg = <0x60000 0x100>, <0x60e00 0x18>; 241 ranges = <0x0 0x60100 0x500>; 242 243 rtic_a: rtic-a@0 { 244 compatible = "fsl,sec-v5.4-rtic-memory", 245 "fsl,sec-v5.0-rtic-memory", 246 "fsl,sec-v4.0-rtic-memory"; 247 reg = <0x00 0x20>, <0x100 0x100>; 248 }; 249 250 rtic_b: rtic-b@20 { 251 compatible = "fsl,sec-v5.4-rtic-memory", 252 "fsl,sec-v5.0-rtic-memory", 253 "fsl,sec-v4.0-rtic-memory"; 254 reg = <0x20 0x20>, <0x200 0x100>; 255 }; 256 257 rtic_c: rtic-c@40 { 258 compatible = "fsl,sec-v5.4-rtic-memory", 259 "fsl,sec-v5.0-rtic-memory", 260 "fsl,sec-v4.0-rtic-memory"; 261 reg = <0x40 0x20>, <0x300 0x100>; 262 }; 263 264 rtic_d: rtic-d@60 { 265 compatible = "fsl,sec-v5.4-rtic-memory", 266 "fsl,sec-v5.0-rtic-memory", 267 "fsl,sec-v4.0-rtic-memory"; 268 reg = <0x60 0x20>, <0x400 0x100>; 269 }; 270 }; 271 }; 272 273 sfp: efuse@1e80000 { 274 compatible = "fsl,ls1021a-sfp"; 275 reg = <0x0 0x1e80000 0x0 0x10000>; 276 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 277 QORIQ_CLK_PLL_DIV(4)>; 278 clock-names = "sfp"; 279 }; 280 281 sec_mon: sec_mon@1e90000 { 282 compatible = "fsl,sec-v5.4-mon", "fsl,sec-v5.0-mon", 283 "fsl,sec-v4.0-mon"; 284 reg = <0x0 0x1e90000 0x0 0x10000>; 285 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 286 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 287 }; 288 289 dcfg: dcfg@1ee0000 { 290 compatible = "fsl,ls1012a-dcfg", 291 "syscon"; 292 reg = <0x0 0x1ee0000 0x0 0x1000>; 293 big-endian; 294 }; 295 296 clockgen: clocking@1ee1000 { 297 compatible = "fsl,ls1012a-clockgen"; 298 reg = <0x0 0x1ee1000 0x0 0x1000>; 299 #clock-cells = <2>; 300 clocks = <&sysclk &coreclk>; 301 clock-names = "sysclk", "coreclk"; 302 }; 303 304 tmu: tmu@1f00000 { 305 compatible = "fsl,qoriq-tmu"; 306 reg = <0x0 0x1f00000 0x0 0x10000>; 307 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 308 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x60062>; 309 fsl,tmu-calibration = 310 <0x00000000 0x00000025>, 311 <0x00000001 0x0000002c>, 312 <0x00000002 0x00000032>, 313 <0x00000003 0x00000039>, 314 <0x00000004 0x0000003f>, 315 <0x00000005 0x00000046>, 316 <0x00000006 0x0000004c>, 317 <0x00000007 0x00000053>, 318 <0x00000008 0x00000059>, 319 <0x00000009 0x0000005f>, 320 <0x0000000a 0x00000066>, 321 <0x0000000b 0x0000006c>, 322 323 <0x00010000 0x00000026>, 324 <0x00010001 0x0000002d>, 325 <0x00010002 0x00000035>, 326 <0x00010003 0x0000003d>, 327 <0x00010004 0x00000045>, 328 <0x00010005 0x0000004d>, 329 <0x00010006 0x00000055>, 330 <0x00010007 0x0000005d>, 331 <0x00010008 0x00000065>, 332 <0x00010009 0x0000006d>, 333 334 <0x00020000 0x00000026>, 335 <0x00020001 0x00000030>, 336 <0x00020002 0x0000003a>, 337 <0x00020003 0x00000044>, 338 <0x00020004 0x0000004e>, 339 <0x00020005 0x00000059>, 340 <0x00020006 0x00000063>, 341 342 <0x00030000 0x00000014>, 343 <0x00030001 0x00000021>, 344 <0x00030002 0x0000002e>, 345 <0x00030003 0x0000003a>, 346 <0x00030004 0x00000047>, 347 <0x00030005 0x00000053>, 348 <0x00030006 0x00000060>; 349 #thermal-sensor-cells = <1>; 350 }; 351 352 i2c0: i2c@2180000 { 353 compatible = "fsl,ls1012a-i2c", "fsl,vf610-i2c"; 354 #address-cells = <1>; 355 #size-cells = <0>; 356 reg = <0x0 0x2180000 0x0 0x10000>; 357 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 358 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 359 QORIQ_CLK_PLL_DIV(4)>; 360 scl-gpios = <&gpio0 2 0>; 361 status = "disabled"; 362 }; 363 364 i2c1: i2c@2190000 { 365 compatible = "fsl,ls1012a-i2c", "fsl,vf610-i2c"; 366 #address-cells = <1>; 367 #size-cells = <0>; 368 reg = <0x0 0x2190000 0x0 0x10000>; 369 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 370 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 371 QORIQ_CLK_PLL_DIV(4)>; 372 scl-gpios = <&gpio0 13 0>; 373 status = "disabled"; 374 }; 375 376 dspi: spi@2100000 { 377 compatible = "fsl,ls1012a-dspi", "fsl,ls1021a-v1.0-dspi"; 378 #address-cells = <1>; 379 #size-cells = <0>; 380 reg = <0x0 0x2100000 0x0 0x10000>; 381 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 382 clock-names = "dspi"; 383 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 384 QORIQ_CLK_PLL_DIV(1)>; 385 spi-num-chipselects = <5>; 386 big-endian; 387 status = "disabled"; 388 }; 389 390 duart0: serial@21c0500 { 391 compatible = "fsl,ns16550", "ns16550a"; 392 reg = <0x00 0x21c0500 0x0 0x100>; 393 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 394 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 395 QORIQ_CLK_PLL_DIV(1)>; 396 status = "disabled"; 397 }; 398 399 duart1: serial@21c0600 { 400 compatible = "fsl,ns16550", "ns16550a"; 401 reg = <0x00 0x21c0600 0x0 0x100>; 402 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 403 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 404 QORIQ_CLK_PLL_DIV(1)>; 405 status = "disabled"; 406 }; 407 408 gpio0: gpio@2300000 { 409 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; 410 reg = <0x0 0x2300000 0x0 0x10000>; 411 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 412 gpio-controller; 413 #gpio-cells = <2>; 414 interrupt-controller; 415 #interrupt-cells = <2>; 416 }; 417 418 gpio1: gpio@2310000 { 419 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; 420 reg = <0x0 0x2310000 0x0 0x10000>; 421 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 422 gpio-controller; 423 #gpio-cells = <2>; 424 interrupt-controller; 425 #interrupt-cells = <2>; 426 }; 427 428 wdog0: watchdog@2ad0000 { 429 compatible = "fsl,ls1012a-wdt", 430 "fsl,imx21-wdt"; 431 reg = <0x0 0x2ad0000 0x0 0x10000>; 432 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 433 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(1)>; 434 big-endian; 435 }; 436 437 sai1: sai@2b50000 { 438 #sound-dai-cells = <0>; 439 compatible = "fsl,vf610-sai"; 440 reg = <0x0 0x2b50000 0x0 0x10000>; 441 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 442 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 443 QORIQ_CLK_PLL_DIV(4)>, 444 <&clockgen QORIQ_CLK_PLATFORM_PLL 445 QORIQ_CLK_PLL_DIV(4)>, 446 <&clockgen QORIQ_CLK_PLATFORM_PLL 447 QORIQ_CLK_PLL_DIV(4)>, 448 <&clockgen QORIQ_CLK_PLATFORM_PLL 449 QORIQ_CLK_PLL_DIV(4)>; 450 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 451 dma-names = "rx", "tx"; 452 dmas = <&edma0 1 46>, 453 <&edma0 1 47>; 454 status = "disabled"; 455 }; 456 457 sai2: sai@2b60000 { 458 #sound-dai-cells = <0>; 459 compatible = "fsl,vf610-sai"; 460 reg = <0x0 0x2b60000 0x0 0x10000>; 461 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 462 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 463 QORIQ_CLK_PLL_DIV(4)>, 464 <&clockgen QORIQ_CLK_PLATFORM_PLL 465 QORIQ_CLK_PLL_DIV(4)>, 466 <&clockgen QORIQ_CLK_PLATFORM_PLL 467 QORIQ_CLK_PLL_DIV(4)>, 468 <&clockgen QORIQ_CLK_PLATFORM_PLL 469 QORIQ_CLK_PLL_DIV(4)>; 470 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 471 dma-names = "rx", "tx"; 472 dmas = <&edma0 1 44>, 473 <&edma0 1 45>; 474 status = "disabled"; 475 }; 476 477 edma0: dma-controller@2c00000 { 478 #dma-cells = <2>; 479 compatible = "fsl,vf610-edma"; 480 reg = <0x0 0x2c00000 0x0 0x10000>, 481 <0x0 0x2c10000 0x0 0x10000>, 482 <0x0 0x2c20000 0x0 0x10000>; 483 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 484 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 485 interrupt-names = "edma-tx", "edma-err"; 486 dma-channels = <32>; 487 big-endian; 488 clock-names = "dmamux0", "dmamux1"; 489 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 490 QORIQ_CLK_PLL_DIV(4)>, 491 <&clockgen QORIQ_CLK_PLATFORM_PLL 492 QORIQ_CLK_PLL_DIV(4)>; 493 }; 494 495 usb0: usb@2f00000 { 496 compatible = "fsl,ls1012a-dwc3", "fsl,ls1028a-dwc3"; 497 reg = <0x0 0x2f00000 0x0 0x10000>; 498 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 499 dr_mode = "host"; 500 dma-coherent; 501 snps,quirk-frame-length-adjustment = <0x20>; 502 snps,dis_rxdet_inp3_quirk; 503 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 504 }; 505 506 sata: sata@3200000 { 507 compatible = "fsl,ls1012a-ahci", "fsl,ls1043a-ahci"; 508 reg = <0x0 0x3200000 0x0 0x10000>, 509 <0x0 0x20140520 0x0 0x4>; 510 reg-names = "ahci", "sata-ecc"; 511 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 512 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 513 QORIQ_CLK_PLL_DIV(1)>; 514 dma-coherent; 515 status = "disabled"; 516 }; 517 518 usb1: usb@8600000 { 519 compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr"; 520 reg = <0x0 0x8600000 0x0 0x1000>; 521 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 522 dr_mode = "host"; 523 phy_type = "ulpi"; 524 }; 525 526 msi: msi-controller1@1572000 { 527 compatible = "fsl,ls1012a-msi"; 528 reg = <0x0 0x1572000 0x0 0x8>; 529 msi-controller; 530 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 531 }; 532 533 pcie1: pcie@3400000 { 534 compatible = "fsl,ls1012a-pcie"; 535 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ 536 <0x40 0x00000000 0x0 0x00002000>; /* configuration space */ 537 reg-names = "regs", "config"; 538 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 539 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 540 interrupt-names = "pme", "aer"; 541 #address-cells = <3>; 542 #size-cells = <2>; 543 device_type = "pci"; 544 bus-range = <0x0 0xff>; 545 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ 546 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 547 msi-parent = <&msi>; 548 #interrupt-cells = <1>; 549 interrupt-map-mask = <0 0 0 7>; 550 interrupt-map = <0000 0 0 1 &gic 0 110 IRQ_TYPE_LEVEL_HIGH>, 551 <0000 0 0 2 &gic 0 111 IRQ_TYPE_LEVEL_HIGH>, 552 <0000 0 0 3 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>, 553 <0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>; 554 big-endian; 555 status = "disabled"; 556 }; 557 558 rcpm: wakeup-controller@1ee2140 { 559 compatible = "fsl,ls1012a-rcpm", "fsl,qoriq-rcpm-2.1+"; 560 reg = <0x0 0x1ee2140 0x0 0x4>; 561 #fsl,rcpm-wakeup-cells = <1>; 562 }; 563 564 ftm_alarm0: rtc@29d0000 { 565 compatible = "fsl,ls1012a-ftm-alarm"; 566 reg = <0x0 0x29d0000 0x0 0x10000>; 567 fsl,rcpm-wakeup = <&rcpm 0x20000>; 568 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 569 big-endian; 570 }; 571 }; 572 573 firmware { 574 optee { 575 compatible = "linaro,optee-tz"; 576 method = "smc"; 577 }; 578 }; 579};
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