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gs101.dtsi
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linux-6.19.14/arch/arm64/boot/dts/exynos/google/gs101.dtsi
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * GS101 SoC 4 * 5 * Copyright 2019-2023 Google LLC 6 * Copyright 2023 Linaro Ltd - <peter.griffin@linaro.org> 7 */ 8 9#include <dt-bindings/clock/google,gs101.h> 10#include <dt-bindings/clock/google,gs101-acpm.h> 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/soc/samsung,exynos-usi.h> 14 15/ { 16 compatible = "google,gs101"; 17 #address-cells = <2>; 18 #size-cells = <1>; 19 20 interrupt-parent = <&gic>; 21 22 aliases { 23 pinctrl0 = &pinctrl_gpio_alive; 24 pinctrl1 = &pinctrl_far_alive; 25 pinctrl2 = &pinctrl_gsacore; 26 pinctrl3 = &pinctrl_gsactrl; 27 pinctrl4 = &pinctrl_peric0; 28 pinctrl5 = &pinctrl_peric1; 29 pinctrl6 = &pinctrl_hsi1; 30 pinctrl7 = &pinctrl_hsi2; 31 }; 32 33 cpus { 34 #address-cells = <1>; 35 #size-cells = <0>; 36 37 cpu-map { 38 cluster0 { 39 core0 { 40 cpu = <&cpu0>; 41 }; 42 core1 { 43 cpu = <&cpu1>; 44 }; 45 core2 { 46 cpu = <&cpu2>; 47 }; 48 core3 { 49 cpu = <&cpu3>; 50 }; 51 }; 52 53 cluster1 { 54 core0 { 55 cpu = <&cpu4>; 56 }; 57 core1 { 58 cpu = <&cpu5>; 59 }; 60 }; 61 62 cluster2 { 63 core0 { 64 cpu = <&cpu6>; 65 }; 66 core1 { 67 cpu = <&cpu7>; 68 }; 69 }; 70 }; 71 72 cpu0: cpu@0 { 73 device_type = "cpu"; 74 compatible = "arm,cortex-a55"; 75 reg = <0x0000>; 76 clocks = <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL0>; 77 enable-method = "psci"; 78 cpu-idle-states = <&ananke_cpu_sleep>; 79 capacity-dmips-mhz = <250>; 80 dynamic-power-coefficient = <70>; 81 operating-points-v2 = <&cpucl0_opp_table>; 82 }; 83 84 cpu1: cpu@100 { 85 device_type = "cpu"; 86 compatible = "arm,cortex-a55"; 87 reg = <0x0100>; 88 clocks = <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL0>; 89 enable-method = "psci"; 90 cpu-idle-states = <&ananke_cpu_sleep>; 91 capacity-dmips-mhz = <250>; 92 dynamic-power-coefficient = <70>; 93 operating-points-v2 = <&cpucl0_opp_table>; 94 }; 95 96 cpu2: cpu@200 { 97 device_type = "cpu"; 98 compatible = "arm,cortex-a55"; 99 reg = <0x0200>; 100 clocks = <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL0>; 101 enable-method = "psci"; 102 cpu-idle-states = <&ananke_cpu_sleep>; 103 capacity-dmips-mhz = <250>; 104 dynamic-power-coefficient = <70>; 105 operating-points-v2 = <&cpucl0_opp_table>; 106 }; 107 108 cpu3: cpu@300 { 109 device_type = "cpu"; 110 compatible = "arm,cortex-a55"; 111 reg = <0x0300>; 112 clocks = <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL0>; 113 enable-method = "psci"; 114 cpu-idle-states = <&ananke_cpu_sleep>; 115 capacity-dmips-mhz = <250>; 116 dynamic-power-coefficient = <70>; 117 operating-points-v2 = <&cpucl0_opp_table>; 118 }; 119 120 cpu4: cpu@400 { 121 device_type = "cpu"; 122 compatible = "arm,cortex-a76"; 123 reg = <0x0400>; 124 clocks = <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL1>; 125 enable-method = "psci"; 126 cpu-idle-states = <&enyo_cpu_sleep>; 127 capacity-dmips-mhz = <620>; 128 dynamic-power-coefficient = <284>; 129 operating-points-v2 = <&cpucl1_opp_table>; 130 }; 131 132 cpu5: cpu@500 { 133 device_type = "cpu"; 134 compatible = "arm,cortex-a76"; 135 reg = <0x0500>; 136 clocks = <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL1>; 137 enable-method = "psci"; 138 cpu-idle-states = <&enyo_cpu_sleep>; 139 capacity-dmips-mhz = <620>; 140 dynamic-power-coefficient = <284>; 141 operating-points-v2 = <&cpucl1_opp_table>; 142 }; 143 144 cpu6: cpu@600 { 145 device_type = "cpu"; 146 compatible = "arm,cortex-x1"; 147 reg = <0x0600>; 148 clocks = <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL2>; 149 enable-method = "psci"; 150 cpu-idle-states = <&hera_cpu_sleep>; 151 capacity-dmips-mhz = <1024>; 152 dynamic-power-coefficient = <650>; 153 operating-points-v2 = <&cpucl2_opp_table>; 154 }; 155 156 cpu7: cpu@700 { 157 device_type = "cpu"; 158 compatible = "arm,cortex-x1"; 159 reg = <0x0700>; 160 clocks = <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL2>; 161 enable-method = "psci"; 162 cpu-idle-states = <&hera_cpu_sleep>; 163 capacity-dmips-mhz = <1024>; 164 dynamic-power-coefficient = <650>; 165 operating-points-v2 = <&cpucl2_opp_table>; 166 }; 167 168 idle-states { 169 entry-method = "psci"; 170 171 ananke_cpu_sleep: cpu-ananke-sleep { 172 idle-state-name = "c2"; 173 compatible = "arm,idle-state"; 174 arm,psci-suspend-param = <0x0010000>; 175 local-timer-stop; 176 entry-latency-us = <70>; 177 exit-latency-us = <160>; 178 min-residency-us = <2000>; 179 }; 180 181 enyo_cpu_sleep: cpu-enyo-sleep { 182 idle-state-name = "c2"; 183 compatible = "arm,idle-state"; 184 arm,psci-suspend-param = <0x0010000>; 185 local-timer-stop; 186 entry-latency-us = <150>; 187 exit-latency-us = <190>; 188 min-residency-us = <2500>; 189 }; 190 191 hera_cpu_sleep: cpu-hera-sleep { 192 idle-state-name = "c2"; 193 compatible = "arm,idle-state"; 194 arm,psci-suspend-param = <0x0010000>; 195 local-timer-stop; 196 entry-latency-us = <235>; 197 exit-latency-us = <220>; 198 min-residency-us = <3500>; 199 }; 200 }; 201 }; 202 203 cpucl0_opp_table: opp-table-0 { 204 compatible = "operating-points-v2"; 205 opp-shared; 206 207 opp-300000000 { 208 opp-hz = /bits/ 64 <300000000>; 209 opp-microvolt = <537500>; 210 clock-latency-ns = <500000>; 211 }; 212 213 opp-574000000 { 214 opp-hz = /bits/ 64 <574000000>; 215 opp-microvolt = <600000>; 216 clock-latency-ns = <500000>; 217 }; 218 219 opp-738000000 { 220 opp-hz = /bits/ 64 <738000000>; 221 opp-microvolt = <618750>; 222 clock-latency-ns = <500000>; 223 }; 224 225 opp-930000000 { 226 opp-hz = /bits/ 64 <930000000>; 227 opp-microvolt = <668750>; 228 clock-latency-ns = <500000>; 229 }; 230 231 opp-1098000000 { 232 opp-hz = /bits/ 64 <1098000000>; 233 opp-microvolt = <712500>; 234 clock-latency-ns = <500000>; 235 }; 236 237 opp-1197000000 { 238 opp-hz = /bits/ 64 <1197000000>; 239 opp-microvolt = <731250>; 240 clock-latency-ns = <500000>; 241 }; 242 243 opp-1328000000 { 244 opp-hz = /bits/ 64 <1328000000>; 245 opp-microvolt = <762500>; 246 clock-latency-ns = <500000>; 247 }; 248 249 opp-1401000000 { 250 opp-hz = /bits/ 64 <1401000000>; 251 opp-microvolt = <781250>; 252 clock-latency-ns = <500000>; 253 }; 254 255 opp-1598000000 { 256 opp-hz = /bits/ 64 <1598000000>; 257 opp-microvolt = <831250>; 258 clock-latency-ns = <500000>; 259 }; 260 261 opp-1704000000 { 262 opp-hz = /bits/ 64 <1704000000>; 263 opp-microvolt = <862500>; 264 clock-latency-ns = <500000>; 265 }; 266 267 opp-1803000000 { 268 opp-hz = /bits/ 64 <1803000000>; 269 opp-microvolt = <906250>; 270 clock-latency-ns = <500000>; 271 }; 272 }; 273 274 cpucl1_opp_table: opp-table-1 { 275 compatible = "operating-points-v2"; 276 opp-shared; 277 278 opp-400000000 { 279 opp-hz = /bits/ 64 <400000000>; 280 opp-microvolt = <506250>; 281 clock-latency-ns = <500000>; 282 }; 283 284 opp-553000000 { 285 opp-hz = /bits/ 64 <553000000>; 286 opp-microvolt = <537500>; 287 clock-latency-ns = <500000>; 288 }; 289 290 opp-696000000 { 291 opp-hz = /bits/ 64 <696000000>; 292 opp-microvolt = <562500>; 293 clock-latency-ns = <500000>; 294 }; 295 296 opp-799000000 { 297 opp-hz = /bits/ 64 <799000000>; 298 opp-microvolt = <581250>; 299 clock-latency-ns = <500000>; 300 }; 301 302 opp-910000000 { 303 opp-hz = /bits/ 64 <910000000>; 304 opp-microvolt = <606250>; 305 clock-latency-ns = <500000>; 306 }; 307 308 opp-1024000000 { 309 opp-hz = /bits/ 64 <1024000000>; 310 opp-microvolt = <625000>; 311 clock-latency-ns = <500000>; 312 }; 313 314 opp-1197000000 { 315 opp-hz = /bits/ 64 <1197000000>; 316 opp-microvolt = <662500>; 317 clock-latency-ns = <500000>; 318 }; 319 320 opp-1328000000 { 321 opp-hz = /bits/ 64 <1328000000>; 322 opp-microvolt = <687500>; 323 clock-latency-ns = <500000>; 324 }; 325 326 opp-1491000000 { 327 opp-hz = /bits/ 64 <1491000000>; 328 opp-microvolt = <731250>; 329 clock-latency-ns = <500000>; 330 }; 331 332 opp-1663000000 { 333 opp-hz = /bits/ 64 <1663000000>; 334 opp-microvolt = <775000>; 335 clock-latency-ns = <500000>; 336 }; 337 338 opp-1836000000 { 339 opp-hz = /bits/ 64 <1836000000>; 340 opp-microvolt = <818750>; 341 clock-latency-ns = <500000>; 342 }; 343 344 opp-1999000000 { 345 opp-hz = /bits/ 64 <1999000000>; 346 opp-microvolt = <868750>; 347 clock-latency-ns = <500000>; 348 }; 349 350 opp-2130000000 { 351 opp-hz = /bits/ 64 <2130000000>; 352 opp-microvolt = <918750>; 353 clock-latency-ns = <500000>; 354 }; 355 356 opp-2253000000 { 357 opp-hz = /bits/ 64 <2253000000>; 358 opp-microvolt = <968750>; 359 clock-latency-ns = <500000>; 360 }; 361 }; 362 363 cpucl2_opp_table: opp-table-2 { 364 compatible = "operating-points-v2"; 365 opp-shared; 366 367 opp-500000000 { 368 opp-hz = /bits/ 64 <500000000>; 369 opp-microvolt = <500000>; 370 clock-latency-ns = <500000>; 371 }; 372 373 opp-851000000 { 374 opp-hz = /bits/ 64 <851000000>; 375 opp-microvolt = <556250>; 376 clock-latency-ns = <500000>; 377 }; 378 379 opp-984000000 { 380 opp-hz = /bits/ 64 <984000000>; 381 opp-microvolt = <575000>; 382 clock-latency-ns = <500000>; 383 }; 384 385 opp-1106000000 { 386 opp-hz = /bits/ 64 <1106000000>; 387 opp-microvolt = <606250>; 388 clock-latency-ns = <500000>; 389 }; 390 391 opp-1277000000 { 392 opp-hz = /bits/ 64 <1277000000>; 393 opp-microvolt = <631250>; 394 clock-latency-ns = <500000>; 395 }; 396 397 opp-1426000000 { 398 opp-hz = /bits/ 64 <1426000000>; 399 opp-microvolt = <662500>; 400 clock-latency-ns = <500000>; 401 }; 402 403 opp-1582000000 { 404 opp-hz = /bits/ 64 <1582000000>; 405 opp-microvolt = <693750>; 406 clock-latency-ns = <500000>; 407 }; 408 409 opp-1745000000 { 410 opp-hz = /bits/ 64 <1745000000>; 411 opp-microvolt = <731250>; 412 clock-latency-ns = <500000>; 413 }; 414 415 opp-1826000000 { 416 opp-hz = /bits/ 64 <1826000000>; 417 opp-microvolt = <750000>; 418 clock-latency-ns = <500000>; 419 }; 420 421 opp-2048000000 { 422 opp-hz = /bits/ 64 <2048000000>; 423 opp-microvolt = <793750>; 424 clock-latency-ns = <500000>; 425 }; 426 427 opp-2188000000 { 428 opp-hz = /bits/ 64 <2188000000>; 429 opp-microvolt = <831250>; 430 clock-latency-ns = <500000>; 431 }; 432 433 opp-2252000000 { 434 opp-hz = /bits/ 64 <2252000000>; 435 opp-microvolt = <850000>; 436 clock-latency-ns = <500000>; 437 }; 438 439 opp-2401000000 { 440 opp-hz = /bits/ 64 <2401000000>; 441 opp-microvolt = <887500>; 442 clock-latency-ns = <500000>; 443 }; 444 445 opp-2507000000 { 446 opp-hz = /bits/ 64 <2507000000>; 447 opp-microvolt = <925000>; 448 clock-latency-ns = <500000>; 449 }; 450 451 opp-2630000000 { 452 opp-hz = /bits/ 64 <2630000000>; 453 opp-microvolt = <968750>; 454 clock-latency-ns = <500000>; 455 }; 456 457 opp-2704000000 { 458 opp-hz = /bits/ 64 <2704000000>; 459 opp-microvolt = <1000000>; 460 clock-latency-ns = <500000>; 461 }; 462 463 opp-2802000000 { 464 opp-hz = /bits/ 64 <2802000000>; 465 opp-microvolt = <1056250>; 466 clock-latency-ns = <500000>; 467 }; 468 }; 469 470 /* ect node is required to be present by bootloader */ 471 ect { 472 }; 473 474 ext_24_5m: clock-1 { 475 compatible = "fixed-clock"; 476 #clock-cells = <0>; 477 clock-output-names = "oscclk"; 478 }; 479 480 ext_200m: clock-2 { 481 compatible = "fixed-clock"; 482 #clock-cells = <0>; 483 clock-output-names = "ext-200m"; 484 }; 485 486 firmware { 487 acpm_ipc: power-management { 488 compatible = "google,gs101-acpm-ipc"; 489 #clock-cells = <1>; 490 mboxes = <&ap2apm_mailbox>; 491 shmem = <&apm_sram>; 492 }; 493 }; 494 495 pmu-0 { 496 compatible = "arm,cortex-a55-pmu"; 497 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 498 }; 499 500 pmu-1 { 501 compatible = "arm,cortex-a76-pmu"; 502 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 503 }; 504 505 pmu-2 { 506 compatible = "arm,cortex-x1-pmu"; 507 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster2>; 508 }; 509 510 pmu-3 { 511 compatible = "arm,dsu-pmu"; 512 cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, 513 <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; 514 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>; 515 }; 516 517 psci { 518 compatible = "arm,psci-1.0"; 519 method = "smc"; 520 }; 521 522 reserved_memory: reserved-memory { 523 #address-cells = <2>; 524 #size-cells = <1>; 525 ranges; 526 527 gsa_reserved_protected: gsa@90200000 { 528 reg = <0x0 0x90200000 0x400000>; 529 no-map; 530 }; 531 532 tpu_fw_reserved: tpu-fw@93000000 { 533 reg = <0x0 0x93000000 0x1000000>; 534 no-map; 535 }; 536 537 aoc_reserve: aoc@94000000 { 538 reg = <0x0 0x94000000 0x03000000>; 539 no-map; 540 }; 541 542 abl_reserved: abl@f8800000 { 543 reg = <0x0 0xf8800000 0x02000000>; 544 no-map; 545 }; 546 547 dss_log_reserved: dss-log-reserved@fd3f0000 { 548 reg = <0x0 0xfd3f0000 0x0000e000>; 549 no-map; 550 }; 551 552 debug_kinfo_reserved: debug-kinfo-reserved@fd3fe000 { 553 reg = <0x0 0xfd3fe000 0x00001000>; 554 no-map; 555 }; 556 557 bldr_log_reserved: bldr-log-reserved@fd800000 { 558 reg = <0x0 0xfd800000 0x00100000>; 559 no-map; 560 }; 561 562 bldr_log_hist_reserved: bldr-log-hist-reserved@fd900000 { 563 reg = <0x0 0xfd900000 0x00002000>; 564 no-map; 565 }; 566 }; 567 568 soc: soc@0 { 569 compatible = "simple-bus"; 570 #address-cells = <1>; 571 #size-cells = <1>; 572 ranges = <0x0 0x0 0x0 0x40000000>; 573 574 cmu_misc: clock-controller@10010000 { 575 compatible = "google,gs101-cmu-misc"; 576 reg = <0x10010000 0x10000>; 577 #clock-cells = <1>; 578 clocks = <&cmu_top CLK_DOUT_CMU_MISC_BUS>, 579 <&cmu_top CLK_DOUT_CMU_MISC_SSS>; 580 clock-names = "bus", "sss"; 581 }; 582 583 sysreg_misc: syscon@10030000 { 584 compatible = "google,gs101-misc-sysreg", "syscon"; 585 reg = <0x10030000 0x10000>; 586 clocks = <&cmu_misc CLK_GOUT_MISC_SYSREG_MISC_PCLK>; 587 }; 588 589 timer@10050000 { 590 compatible = "google,gs101-mct", 591 "samsung,exynos4210-mct"; 592 reg = <0x10050000 0x800>; 593 clocks = <&ext_24_5m>, <&cmu_misc CLK_GOUT_MISC_MCT_PCLK>; 594 clock-names = "fin_pll", "mct"; 595 interrupts = <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH 0>, 596 <GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH 0>, 597 <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH 0>, 598 <GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH 0>, 599 <GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH 0>, 600 <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH 0>, 601 <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH 0>, 602 <GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH 0>, 603 <GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH 0>, 604 <GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH 0>, 605 <GIC_SPI 763 IRQ_TYPE_LEVEL_HIGH 0>, 606 <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH 0>; 607 }; 608 609 watchdog_cl0: watchdog@10060000 { 610 compatible = "google,gs101-wdt"; 611 reg = <0x10060000 0x100>; 612 clocks = <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER0_PCLK>, 613 <&ext_24_5m>; 614 clock-names = "watchdog", "watchdog_src"; 615 interrupts = <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH 0>; 616 samsung,syscon-phandle = <&pmu_system_controller>; 617 samsung,cluster-index = <0>; 618 status = "disabled"; 619 }; 620 621 watchdog_cl1: watchdog@10070000 { 622 compatible = "google,gs101-wdt"; 623 reg = <0x10070000 0x100>; 624 clocks = <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER1_PCLK>, 625 <&ext_24_5m>; 626 clock-names = "watchdog", "watchdog_src"; 627 interrupts = <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH 0>; 628 samsung,syscon-phandle = <&pmu_system_controller>; 629 samsung,cluster-index = <1>; 630 status = "disabled"; 631 }; 632 633 gic: interrupt-controller@10400000 { 634 compatible = "arm,gic-v3"; 635 #address-cells = <0>; 636 #interrupt-cells = <4>; 637 interrupt-controller; 638 reg = <0x10400000 0x10000>, /* GICD */ 639 <0x10440000 0x100000>;/* GICR * 8 */ 640 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 641 642 ppi-partitions { 643 ppi_cluster0: interrupt-partition-0 { 644 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 645 }; 646 647 ppi_cluster1: interrupt-partition-1 { 648 affinity = <&cpu4 &cpu5>; 649 }; 650 651 ppi_cluster2: interrupt-partition-2 { 652 affinity = <&cpu6 &cpu7>; 653 }; 654 }; 655 }; 656 657 cmu_peric0: clock-controller@10800000 { 658 compatible = "google,gs101-cmu-peric0"; 659 reg = <0x10800000 0x10000>; 660 #clock-cells = <1>; 661 clocks = <&ext_24_5m>, 662 <&cmu_top CLK_DOUT_CMU_PERIC0_BUS>, 663 <&cmu_top CLK_DOUT_CMU_PERIC0_IP>; 664 clock-names = "oscclk", "bus", "ip"; 665 }; 666 667 sysreg_peric0: syscon@10820000 { 668 compatible = "google,gs101-peric0-sysreg", "syscon"; 669 reg = <0x10820000 0x10000>; 670 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK>; 671 }; 672 673 pinctrl_peric0: pinctrl@10840000 { 674 compatible = "google,gs101-pinctrl"; 675 reg = <0x10840000 0x00001000>; 676 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_GPIO_PERIC0_PCLK>; 677 clock-names = "pclk"; 678 interrupts = <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH 0>; 679 }; 680 681 usi1: usi@109000c0 { 682 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 683 reg = <0x109000c0 0x20>; 684 ranges; 685 #address-cells = <1>; 686 #size-cells = <1>; 687 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0>, 688 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0>; 689 clock-names = "pclk", "ipclk"; 690 samsung,sysreg = <&sysreg_peric0 0x1000>; 691 status = "disabled"; 692 693 hsi2c_1: i2c@10900000 { 694 compatible = "google,gs101-hsi2c", 695 "samsung,exynosautov9-hsi2c"; 696 reg = <0x10900000 0xc0>; 697 #address-cells = <1>; 698 #size-cells = <0>; 699 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0>, 700 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0>; 701 clock-names = "hsi2c", "hsi2c_pclk"; 702 interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0>; 703 pinctrl-0 = <&hsi2c1_bus>; 704 pinctrl-names = "default"; 705 status = "disabled"; 706 }; 707 708 serial_1: serial@10900000 { 709 compatible = "google,gs101-uart"; 710 reg = <0x10900000 0xc0>; 711 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0>, 712 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0>; 713 clock-names = "uart", "clk_uart_baud0"; 714 interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0>; 715 pinctrl-0 = <&uart1_bus_single>; 716 pinctrl-names = "default"; 717 samsung,uart-fifosize = <64>; 718 status = "disabled"; 719 }; 720 721 spi_1: spi@10900000 { 722 compatible = "google,gs101-spi"; 723 reg = <0x10900000 0x30>; 724 #address-cells = <1>; 725 #size-cells = <0>; 726 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0>, 727 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0>; 728 clock-names = "spi", "spi_busclk0"; 729 interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0>; 730 pinctrl-0 = <&spi1_bus>; 731 pinctrl-names = "default"; 732 status = "disabled"; 733 }; 734 }; 735 736 usi2: usi@109100c0 { 737 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 738 reg = <0x109100c0 0x20>; 739 ranges; 740 #address-cells = <1>; 741 #size-cells = <1>; 742 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1>, 743 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1>; 744 clock-names = "pclk", "ipclk"; 745 samsung,sysreg = <&sysreg_peric0 0x1004>; 746 status = "disabled"; 747 748 hsi2c_2: i2c@10910000 { 749 compatible = "google,gs101-hsi2c", 750 "samsung,exynosautov9-hsi2c"; 751 reg = <0x10910000 0xc0>; 752 #address-cells = <1>; 753 #size-cells = <0>; 754 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1>, 755 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1>; 756 clock-names = "hsi2c", "hsi2c_pclk"; 757 interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>; 758 pinctrl-0 = <&hsi2c2_bus>; 759 pinctrl-names = "default"; 760 status = "disabled"; 761 }; 762 763 serial_2: serial@10910000 { 764 compatible = "google,gs101-uart"; 765 reg = <0x10910000 0xc0>; 766 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1>, 767 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1>; 768 clock-names = "uart", "clk_uart_baud0"; 769 interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>; 770 pinctrl-0 = <&uart2_bus_single>; 771 pinctrl-names = "default"; 772 samsung,uart-fifosize = <64>; 773 status = "disabled"; 774 }; 775 776 spi_2: spi@10910000 { 777 compatible = "google,gs101-spi"; 778 reg = <0x10910000 0x30>; 779 #address-cells = <1>; 780 #size-cells = <0>; 781 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1>, 782 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1>; 783 clock-names = "spi", "spi_busclk0"; 784 interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>; 785 pinctrl-0 = <&spi2_bus>; 786 pinctrl-names = "default"; 787 status = "disabled"; 788 }; 789 }; 790 791 usi3: usi@109200c0 { 792 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 793 reg = <0x109200c0 0x20>; 794 ranges; 795 #address-cells = <1>; 796 #size-cells = <1>; 797 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2>, 798 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2>; 799 clock-names = "pclk", "ipclk"; 800 samsung,sysreg = <&sysreg_peric0 0x1008>; 801 status = "disabled"; 802 803 hsi2c_3: i2c@10920000 { 804 compatible = "google,gs101-hsi2c", 805 "samsung,exynosautov9-hsi2c"; 806 reg = <0x10920000 0xc0>; 807 #address-cells = <1>; 808 #size-cells = <0>; 809 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2>, 810 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2>; 811 clock-names = "hsi2c", "hsi2c_pclk"; 812 interrupts = <GIC_SPI 637 IRQ_TYPE_LEVEL_HIGH 0>; 813 pinctrl-0 = <&hsi2c3_bus>; 814 pinctrl-names = "default"; 815 status = "disabled"; 816 }; 817 818 serial_3: serial@10920000 { 819 compatible = "google,gs101-uart"; 820 reg = <0x10920000 0xc0>; 821 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2>, 822 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2>; 823 clock-names = "uart", "clk_uart_baud0"; 824 interrupts = <GIC_SPI 637 IRQ_TYPE_LEVEL_HIGH 0>; 825 pinctrl-0 = <&uart3_bus_single>; 826 pinctrl-names = "default"; 827 samsung,uart-fifosize = <64>; 828 status = "disabled"; 829 }; 830 831 spi_3: spi@10920000 { 832 compatible = "google,gs101-spi"; 833 reg = <0x10920000 0x30>; 834 #address-cells = <1>; 835 #size-cells = <0>; 836 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2>, 837 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2>; 838 clock-names = "spi", "spi_busclk0"; 839 interrupts = <GIC_SPI 637 IRQ_TYPE_LEVEL_HIGH 0>; 840 pinctrl-0 = <&spi3_bus>; 841 pinctrl-names = "default"; 842 status = "disabled"; 843 }; 844 }; 845 846 usi4: usi@109300c0 { 847 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 848 reg = <0x109300c0 0x20>; 849 ranges; 850 #address-cells = <1>; 851 #size-cells = <1>; 852 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3>, 853 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3>; 854 clock-names = "pclk", "ipclk"; 855 samsung,sysreg = <&sysreg_peric0 0x100c>; 856 status = "disabled"; 857 858 hsi2c_4: i2c@10930000 { 859 compatible = "google,gs101-hsi2c", 860 "samsung,exynosautov9-hsi2c"; 861 reg = <0x10930000 0xc0>; 862 #address-cells = <1>; 863 #size-cells = <0>; 864 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3>, 865 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3>; 866 clock-names = "hsi2c", "hsi2c_pclk"; 867 interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>; 868 pinctrl-0 = <&hsi2c4_bus>; 869 pinctrl-names = "default"; 870 status = "disabled"; 871 }; 872 873 serial_4: serial@10930000 { 874 compatible = "google,gs101-uart"; 875 reg = <0x10930000 0xc0>; 876 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3>, 877 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3>; 878 clock-names = "uart", "clk_uart_baud0"; 879 interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>; 880 pinctrl-0 = <&uart4_bus_single>; 881 pinctrl-names = "default"; 882 samsung,uart-fifosize = <64>; 883 status = "disabled"; 884 }; 885 886 spi_4: spi@10930000 { 887 compatible = "google,gs101-spi"; 888 reg = <0x10930000 0x30>; 889 #address-cells = <1>; 890 #size-cells = <0>; 891 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3>, 892 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3>; 893 clock-names = "spi", "spi_busclk0"; 894 interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>; 895 pinctrl-0 = <&spi4_bus>; 896 pinctrl-names = "default"; 897 status = "disabled"; 898 }; 899 }; 900 901 usi5: usi@109400c0 { 902 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 903 reg = <0x109400c0 0x20>; 904 ranges; 905 #address-cells = <1>; 906 #size-cells = <1>; 907 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4>, 908 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4>; 909 clock-names = "pclk", "ipclk"; 910 samsung,sysreg = <&sysreg_peric0 0x1010>; 911 status = "disabled"; 912 913 hsi2c_5: i2c@10940000 { 914 compatible = "google,gs101-hsi2c", 915 "samsung,exynosautov9-hsi2c"; 916 reg = <0x10940000 0xc0>; 917 #address-cells = <1>; 918 #size-cells = <0>; 919 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4>, 920 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4>; 921 clock-names = "hsi2c", "hsi2c_pclk"; 922 interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>; 923 pinctrl-0 = <&hsi2c5_bus>; 924 pinctrl-names = "default"; 925 status = "disabled"; 926 }; 927 928 serial_5: serial@10940000 { 929 compatible = "google,gs101-uart"; 930 reg = <0x10940000 0xc0>; 931 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4>, 932 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4>; 933 clock-names = "uart", "clk_uart_baud0"; 934 interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>; 935 pinctrl-0 = <&uart5_bus_single>; 936 pinctrl-names = "default"; 937 samsung,uart-fifosize = <64>; 938 status = "disabled"; 939 }; 940 941 spi_5: spi@10940000 { 942 compatible = "google,gs101-spi"; 943 reg = <0x10940000 0x30>; 944 #address-cells = <1>; 945 #size-cells = <0>; 946 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4>, 947 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4>; 948 clock-names = "spi", "spi_busclk0"; 949 interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>; 950 pinctrl-0 = <&spi5_bus>; 951 pinctrl-names = "default"; 952 status = "disabled"; 953 }; 954 }; 955 956 usi6: usi@109500c0 { 957 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 958 reg = <0x109500c0 0x20>; 959 ranges; 960 #address-cells = <1>; 961 #size-cells = <1>; 962 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5>, 963 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5>; 964 clock-names = "pclk", "ipclk"; 965 samsung,sysreg = <&sysreg_peric0 0x1014>; 966 status = "disabled"; 967 968 hsi2c_6: i2c@10950000 { 969 compatible = "google,gs101-hsi2c", 970 "samsung,exynosautov9-hsi2c"; 971 reg = <0x10950000 0xc0>; 972 #address-cells = <1>; 973 #size-cells = <0>; 974 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5>, 975 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5>; 976 clock-names = "hsi2c", "hsi2c_pclk"; 977 interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>; 978 pinctrl-0 = <&hsi2c6_bus>; 979 pinctrl-names = "default"; 980 status = "disabled"; 981 }; 982 983 serial_6: serial@10950000 { 984 compatible = "google,gs101-uart"; 985 reg = <0x10950000 0xc0>; 986 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5>, 987 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5>; 988 clock-names = "uart", "clk_uart_baud0"; 989 interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>; 990 pinctrl-0 = <&uart6_bus_single>; 991 pinctrl-names = "default"; 992 samsung,uart-fifosize = <64>; 993 status = "disabled"; 994 }; 995 996 spi_6: spi@10950000 { 997 compatible = "google,gs101-spi"; 998 reg = <0x10950000 0x30>; 999 #address-cells = <1>; 1000 #size-cells = <0>; 1001 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5>, 1002 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5>; 1003 clock-names = "spi", "spi_busclk0"; 1004 interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>; 1005 pinctrl-0 = <&spi6_bus>; 1006 pinctrl-names = "default"; 1007 status = "disabled"; 1008 }; 1009 }; 1010 1011 usi7: usi@109600c0 { 1012 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 1013 reg = <0x109600c0 0x20>; 1014 ranges; 1015 #address-cells = <1>; 1016 #size-cells = <1>; 1017 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6>, 1018 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6>; 1019 clock-names = "pclk", "ipclk"; 1020 samsung,sysreg = <&sysreg_peric0 0x1018>; 1021 status = "disabled"; 1022 1023 hsi2c_7: i2c@10960000 { 1024 compatible = "google,gs101-hsi2c", 1025 "samsung,exynosautov9-hsi2c"; 1026 reg = <0x10960000 0xc0>; 1027 #address-cells = <1>; 1028 #size-cells = <0>; 1029 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6>, 1030 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6>; 1031 clock-names = "hsi2c", "hsi2c_pclk"; 1032 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>; 1033 pinctrl-0 = <&hsi2c7_bus>; 1034 pinctrl-names = "default"; 1035 status = "disabled"; 1036 }; 1037 1038 serial_7: serial@10960000 { 1039 compatible = "google,gs101-uart"; 1040 reg = <0x10960000 0xc0>; 1041 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6>, 1042 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6>; 1043 clock-names = "uart", "clk_uart_baud0"; 1044 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>; 1045 pinctrl-0 = <&uart7_bus_single>; 1046 pinctrl-names = "default"; 1047 samsung,uart-fifosize = <64>; 1048 status = "disabled"; 1049 }; 1050 1051 spi_7: spi@10960000 { 1052 compatible = "google,gs101-spi"; 1053 reg = <0x10960000 0x30>; 1054 #address-cells = <1>; 1055 #size-cells = <0>; 1056 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6>, 1057 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6>; 1058 clock-names = "spi", "spi_busclk0"; 1059 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>; 1060 pinctrl-0 = <&spi7_bus>; 1061 pinctrl-names = "default"; 1062 status = "disabled"; 1063 }; 1064 }; 1065 1066 usi8: usi@109700c0 { 1067 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 1068 reg = <0x109700c0 0x20>; 1069 ranges; 1070 #address-cells = <1>; 1071 #size-cells = <1>; 1072 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7>, 1073 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>; 1074 clock-names = "pclk", "ipclk"; 1075 samsung,sysreg = <&sysreg_peric0 0x101c>; 1076 status = "disabled"; 1077 1078 hsi2c_8: i2c@10970000 { 1079 compatible = "google,gs101-hsi2c", 1080 "samsung,exynosautov9-hsi2c"; 1081 reg = <0x10970000 0xc0>; 1082 #address-cells = <1>; 1083 #size-cells = <0>; 1084 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>, 1085 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7>; 1086 clock-names = "hsi2c", "hsi2c_pclk"; 1087 interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>; 1088 pinctrl-0 = <&hsi2c8_bus>; 1089 pinctrl-names = "default"; 1090 status = "disabled"; 1091 }; 1092 1093 serial_8: serial@10970000 { 1094 compatible = "google,gs101-uart"; 1095 reg = <0x10970000 0xc0>; 1096 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7>, 1097 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>; 1098 clock-names = "uart", "clk_uart_baud0"; 1099 interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>; 1100 pinctrl-0 = <&uart8_bus_single>; 1101 pinctrl-names = "default"; 1102 samsung,uart-fifosize = <64>; 1103 status = "disabled"; 1104 }; 1105 1106 spi_8: spi@10970000 { 1107 compatible = "google,gs101-spi"; 1108 reg = <0x10970000 0x30>; 1109 #address-cells = <1>; 1110 #size-cells = <0>; 1111 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7>, 1112 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>; 1113 clock-names = "spi", "spi_busclk0"; 1114 interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>; 1115 pinctrl-0 = <&spi8_bus>; 1116 pinctrl-names = "default"; 1117 status = "disabled"; 1118 }; 1119 }; 1120 1121 usi_uart: usi@10a000c0 { 1122 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 1123 reg = <0x10a000c0 0x20>; 1124 ranges; 1125 #address-cells = <1>; 1126 #size-cells = <1>; 1127 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0>, 1128 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0>; 1129 clock-names = "pclk", "ipclk"; 1130 samsung,sysreg = <&sysreg_peric0 0x1020>; 1131 samsung,mode = <USI_MODE_UART>; 1132 status = "disabled"; 1133 1134 serial_0: serial@10a00000 { 1135 compatible = "google,gs101-uart"; 1136 reg = <0x10a00000 0xc0>; 1137 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0>, 1138 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0>; 1139 clock-names = "uart", "clk_uart_baud0"; 1140 interrupts = <GIC_SPI 634 IRQ_TYPE_LEVEL_HIGH 0>; 1141 pinctrl-0 = <&uart0_bus>; 1142 pinctrl-names = "default"; 1143 samsung,uart-fifosize = <256>; 1144 status = "disabled"; 1145 }; 1146 }; 1147 1148 usi14: usi@10a200c0 { 1149 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 1150 reg = <0x10a200c0 0x20>; 1151 ranges; 1152 #address-cells = <1>; 1153 #size-cells = <1>; 1154 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2>, 1155 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2>; 1156 clock-names = "pclk", "ipclk"; 1157 samsung,sysreg = <&sysreg_peric0 0x1028>; 1158 status = "disabled"; 1159 1160 hsi2c_14: i2c@10a20000 { 1161 compatible = "google,gs101-hsi2c", 1162 "samsung,exynosautov9-hsi2c"; 1163 reg = <0x10a20000 0xc0>; 1164 #address-cells = <1>; 1165 #size-cells = <0>; 1166 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2>, 1167 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2>; 1168 clock-names = "hsi2c", "hsi2c_pclk"; 1169 interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>; 1170 pinctrl-0 = <&hsi2c14_bus>; 1171 pinctrl-names = "default"; 1172 status = "disabled"; 1173 }; 1174 1175 serial_14: serial@10a20000 { 1176 compatible = "google,gs101-uart"; 1177 reg = <0x10a20000 0xc0>; 1178 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2>, 1179 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2>; 1180 clock-names = "uart", "clk_uart_baud0"; 1181 interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>; 1182 pinctrl-0 = <&uart14_bus_single>; 1183 pinctrl-names = "default"; 1184 samsung,uart-fifosize = <64>; 1185 status = "disabled"; 1186 }; 1187 1188 spi_14: spi@10a20000 { 1189 compatible = "google,gs101-spi"; 1190 reg = <0x10a20000 0x30>; 1191 #address-cells = <1>; 1192 #size-cells = <0>; 1193 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2>, 1194 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2>; 1195 clock-names = "spi", "spi_busclk0"; 1196 interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>; 1197 pinctrl-0 = <&spi14_bus>; 1198 pinctrl-names = "default"; 1199 status = "disabled"; 1200 }; 1201 }; 1202 1203 cmu_peric1: clock-controller@10c00000 { 1204 compatible = "google,gs101-cmu-peric1"; 1205 reg = <0x10c00000 0x10000>; 1206 #clock-cells = <1>; 1207 clocks = <&ext_24_5m>, 1208 <&cmu_top CLK_DOUT_CMU_PERIC1_BUS>, 1209 <&cmu_top CLK_DOUT_CMU_PERIC1_IP>; 1210 clock-names = "oscclk", "bus", "ip"; 1211 }; 1212 1213 sysreg_peric1: syscon@10c20000 { 1214 compatible = "google,gs101-peric1-sysreg", "syscon"; 1215 reg = <0x10c20000 0x10000>; 1216 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK>; 1217 }; 1218 1219 pinctrl_peric1: pinctrl@10c40000 { 1220 compatible = "google,gs101-pinctrl"; 1221 reg = <0x10c40000 0x00001000>; 1222 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_GPIO_PERIC1_PCLK>; 1223 clock-names = "pclk"; 1224 interrupts = <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH 0>; 1225 }; 1226 1227 usi0: usi@10d100c0 { 1228 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 1229 reg = <0x10d100c0 0x20>; 1230 ranges; 1231 #address-cells = <1>; 1232 #size-cells = <1>; 1233 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1>, 1234 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1>; 1235 clock-names = "pclk", "ipclk"; 1236 samsung,sysreg = <&sysreg_peric1 0x1000>; 1237 status = "disabled"; 1238 1239 hsi2c_0: i2c@10d10000 { 1240 compatible = "google,gs101-hsi2c", 1241 "samsung,exynosautov9-hsi2c"; 1242 reg = <0x10d10000 0xc0>; 1243 #address-cells = <1>; 1244 #size-cells = <0>; 1245 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1>, 1246 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1>; 1247 clock-names = "hsi2c", "hsi2c_pclk"; 1248 interrupts = <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH 0>; 1249 pinctrl-0 = <&hsi2c0_bus>; 1250 pinctrl-names = "default"; 1251 status = "disabled"; 1252 }; 1253 1254 serial_usi0: serial@10d10000 { 1255 compatible = "google,gs101-uart"; 1256 reg = <0x10d10000 0xc0>; 1257 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1>, 1258 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1>; 1259 clock-names = "uart", "clk_uart_baud0"; 1260 interrupts = <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH 0>; 1261 pinctrl-0 = <&uart0_bus_single>; 1262 pinctrl-names = "default"; 1263 samsung,uart-fifosize = <64>; 1264 status = "disabled"; 1265 }; 1266 1267 spi_0: spi@10d10000 { 1268 compatible = "google,gs101-spi"; 1269 reg = <0x10d10000 0x30>; 1270 #address-cells = <1>; 1271 #size-cells = <0>; 1272 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1>, 1273 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1>; 1274 clock-names = "spi", "spi_busclk0"; 1275 interrupts = <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH 0>; 1276 pinctrl-0 = <&spi0_bus>; 1277 pinctrl-names = "default"; 1278 status = "disabled"; 1279 }; 1280 }; 1281 1282 usi9: usi@10d200c0 { 1283 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 1284 reg = <0x10d200c0 0x20>; 1285 ranges; 1286 #address-cells = <1>; 1287 #size-cells = <1>; 1288 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2>, 1289 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2>; 1290 clock-names = "pclk", "ipclk"; 1291 samsung,sysreg = <&sysreg_peric1 0x1004>; 1292 status = "disabled"; 1293 1294 hsi2c_9: i2c@10d20000 { 1295 compatible = "google,gs101-hsi2c", 1296 "samsung,exynosautov9-hsi2c"; 1297 reg = <0x10d20000 0xc0>; 1298 #address-cells = <1>; 1299 #size-cells = <0>; 1300 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2>, 1301 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2>; 1302 clock-names = "hsi2c", "hsi2c_pclk"; 1303 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH 0>; 1304 pinctrl-0 = <&hsi2c9_bus>; 1305 pinctrl-names = "default"; 1306 status = "disabled"; 1307 }; 1308 1309 serial_9: serial@10d20000 { 1310 compatible = "google,gs101-uart"; 1311 reg = <0x10d20000 0xc0>; 1312 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2>, 1313 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2>; 1314 clock-names = "uart", "clk_uart_baud0"; 1315 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH 0>; 1316 pinctrl-0 = <&uart9_bus_single>; 1317 pinctrl-names = "default"; 1318 samsung,uart-fifosize = <64>; 1319 status = "disabled"; 1320 }; 1321 1322 spi_9: spi@10d20000 { 1323 compatible = "google,gs101-spi"; 1324 reg = <0x10d20000 0x30>; 1325 #address-cells = <1>; 1326 #size-cells = <0>; 1327 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2>, 1328 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2>; 1329 clock-names = "spi", "spi_busclk0"; 1330 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH 0>; 1331 pinctrl-0 = <&spi9_bus>; 1332 pinctrl-names = "default"; 1333 status = "disabled"; 1334 }; 1335 }; 1336 1337 usi10: usi@10d300c0 { 1338 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 1339 reg = <0x10d300c0 0x20>; 1340 ranges; 1341 #address-cells = <1>; 1342 #size-cells = <1>; 1343 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3>, 1344 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3>; 1345 clock-names = "pclk", "ipclk"; 1346 samsung,sysreg = <&sysreg_peric1 0x1008>; 1347 status = "disabled"; 1348 1349 hsi2c_10: i2c@10d30000 { 1350 compatible = "google,gs101-hsi2c", 1351 "samsung,exynosautov9-hsi2c"; 1352 reg = <0x10d30000 0xc0>; 1353 #address-cells = <1>; 1354 #size-cells = <0>; 1355 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3>, 1356 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3>; 1357 clock-names = "hsi2c", "hsi2c_pclk"; 1358 interrupts = <GIC_SPI 653 IRQ_TYPE_LEVEL_HIGH 0>; 1359 pinctrl-0 = <&hsi2c10_bus>; 1360 pinctrl-names = "default"; 1361 status = "disabled"; 1362 }; 1363 1364 serial_10: serial@10d30000 { 1365 compatible = "google,gs101-uart"; 1366 reg = <0x10d30000 0xc0>; 1367 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3>, 1368 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3>; 1369 clock-names = "uart", "clk_uart_baud0"; 1370 interrupts = <GIC_SPI 653 IRQ_TYPE_LEVEL_HIGH 0>; 1371 pinctrl-0 = <&uart10_bus_single>; 1372 pinctrl-names = "default"; 1373 samsung,uart-fifosize = <64>; 1374 status = "disabled"; 1375 }; 1376 1377 spi_10: spi@10d30000 { 1378 compatible = "google,gs101-spi"; 1379 reg = <0x10d30000 0x30>; 1380 #address-cells = <1>; 1381 #size-cells = <0>; 1382 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3>, 1383 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3>; 1384 clock-names = "spi", "spi_busclk0"; 1385 interrupts = <GIC_SPI 653 IRQ_TYPE_LEVEL_HIGH 0>; 1386 pinctrl-0 = <&spi10_bus>; 1387 pinctrl-names = "default"; 1388 status = "disabled"; 1389 }; 1390 }; 1391 1392 usi11: usi@10d400c0 { 1393 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 1394 reg = <0x10d400c0 0x20>; 1395 ranges; 1396 #address-cells = <1>; 1397 #size-cells = <1>; 1398 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4>, 1399 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4>; 1400 clock-names = "pclk", "ipclk"; 1401 samsung,sysreg = <&sysreg_peric1 0x100c>; 1402 status = "disabled"; 1403 1404 hsi2c_11: i2c@10d40000 { 1405 compatible = "google,gs101-hsi2c", 1406 "samsung,exynosautov9-hsi2c"; 1407 reg = <0x10d40000 0xc0>; 1408 #address-cells = <1>; 1409 #size-cells = <0>; 1410 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4>, 1411 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4>; 1412 clock-names = "hsi2c", "hsi2c_pclk"; 1413 interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH 0>; 1414 pinctrl-0 = <&hsi2c11_bus>; 1415 pinctrl-names = "default"; 1416 status = "disabled"; 1417 }; 1418 1419 serial_11: serial@10d40000 { 1420 compatible = "google,gs101-uart"; 1421 reg = <0x10d40000 0xc0>; 1422 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4>, 1423 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4>; 1424 clock-names = "uart", "clk_uart_baud0"; 1425 interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH 0>; 1426 pinctrl-0 = <&uart11_bus_single>; 1427 pinctrl-names = "default"; 1428 samsung,uart-fifosize = <64>; 1429 status = "disabled"; 1430 }; 1431 1432 spi_11: spi@10d40000 { 1433 compatible = "google,gs101-spi"; 1434 reg = <0x10d40000 0x30>; 1435 #address-cells = <1>; 1436 #size-cells = <0>; 1437 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4>, 1438 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4>; 1439 clock-names = "spi", "spi_busclk0"; 1440 interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH 0>; 1441 pinctrl-0 = <&spi11_bus>; 1442 pinctrl-names = "default"; 1443 status = "disabled"; 1444 }; 1445 }; 1446 1447 usi12: usi@10d500c0 { 1448 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 1449 reg = <0x10d500c0 0x20>; 1450 ranges; 1451 #address-cells = <1>; 1452 #size-cells = <1>; 1453 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5>, 1454 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5>; 1455 clock-names = "pclk", "ipclk"; 1456 samsung,sysreg = <&sysreg_peric1 0x1010>; 1457 status = "disabled"; 1458 1459 hsi2c_12: i2c@10d50000 { 1460 compatible = "google,gs101-hsi2c", 1461 "samsung,exynosautov9-hsi2c"; 1462 reg = <0x10d50000 0xc0>; 1463 #address-cells = <1>; 1464 #size-cells = <0>; 1465 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5>, 1466 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5>; 1467 clock-names = "hsi2c", "hsi2c_pclk"; 1468 interrupts = <GIC_SPI 655 IRQ_TYPE_LEVEL_HIGH 0>; 1469 pinctrl-0 = <&hsi2c12_bus>; 1470 pinctrl-names = "default"; 1471 status = "disabled"; 1472 }; 1473 1474 serial_12: serial@10d50000 { 1475 compatible = "google,gs101-uart"; 1476 reg = <0x10d50000 0xc0>; 1477 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5>, 1478 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5>; 1479 clock-names = "uart", "clk_uart_baud0"; 1480 interrupts = <GIC_SPI 655 IRQ_TYPE_LEVEL_HIGH 0>; 1481 pinctrl-0 = <&uart12_bus_single>; 1482 pinctrl-names = "default"; 1483 samsung,uart-fifosize = <64>; 1484 status = "disabled"; 1485 }; 1486 1487 spi_12: spi@10d50000 { 1488 compatible = "google,gs101-spi"; 1489 reg = <0x10d50000 0x30>; 1490 #address-cells = <1>; 1491 #size-cells = <0>; 1492 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5>, 1493 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5>; 1494 clock-names = "spi", "spi_busclk0"; 1495 interrupts = <GIC_SPI 655 IRQ_TYPE_LEVEL_HIGH 0>; 1496 pinctrl-0 = <&spi12_bus>; 1497 pinctrl-names = "default"; 1498 status = "disabled"; 1499 }; 1500 }; 1501 1502 usi13: usi@10d600c0 { 1503 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 1504 reg = <0x10d600c0 0x20>; 1505 ranges; 1506 #address-cells = <1>; 1507 #size-cells = <1>; 1508 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6>, 1509 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6>; 1510 clock-names = "pclk", "ipclk"; 1511 samsung,sysreg = <&sysreg_peric1 0x1014>; 1512 status = "disabled"; 1513 1514 hsi2c_13: i2c@10d60000 { 1515 compatible = "google,gs101-hsi2c", 1516 "samsung,exynosautov9-hsi2c"; 1517 reg = <0x10d60000 0xc0>; 1518 #address-cells = <1>; 1519 #size-cells = <0>; 1520 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6>, 1521 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6>; 1522 clock-names = "hsi2c", "hsi2c_pclk"; 1523 interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>; 1524 pinctrl-0 = <&hsi2c13_bus>; 1525 pinctrl-names = "default"; 1526 status = "disabled"; 1527 }; 1528 1529 serial_13: serial@10d60000 { 1530 compatible = "google,gs101-uart"; 1531 reg = <0x10d60000 0xc0>; 1532 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6>, 1533 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6>; 1534 clock-names = "uart", "clk_uart_baud0"; 1535 interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>; 1536 pinctrl-0 = <&uart13_bus_single>; 1537 pinctrl-names = "default"; 1538 samsung,uart-fifosize = <64>; 1539 status = "disabled"; 1540 }; 1541 1542 spi_13: spi@10d60000 { 1543 compatible = "google,gs101-spi"; 1544 reg = <0x10d60000 0x30>; 1545 #address-cells = <1>; 1546 #size-cells = <0>; 1547 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6>, 1548 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6>; 1549 clock-names = "spi", "spi_busclk0"; 1550 interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>; 1551 pinctrl-0 = <&spi13_bus>; 1552 pinctrl-names = "default"; 1553 status = "disabled"; 1554 }; 1555 }; 1556 1557 cmu_hsi0: clock-controller@11000000 { 1558 compatible = "google,gs101-cmu-hsi0"; 1559 reg = <0x11000000 0x10000>; 1560 #clock-cells = <1>; 1561 1562 clocks = <&ext_24_5m>, 1563 <&cmu_top CLK_DOUT_CMU_HSI0_BUS>, 1564 <&cmu_top CLK_DOUT_CMU_HSI0_DPGTC>, 1565 <&cmu_top CLK_DOUT_CMU_HSI0_USB31DRD>, 1566 <&cmu_top CLK_DOUT_CMU_HSI0_USBDPDBG>; 1567 clock-names = "oscclk", "bus", "dpgtc", "usb31drd", 1568 "usbdpdbg"; 1569 }; 1570 1571 sysreg_hsi0: syscon@11020000 { 1572 compatible = "google,gs101-hsi0-sysreg", "syscon"; 1573 reg = <0x11020000 0x10000>; 1574 clocks = <&cmu_hsi0 CLK_GOUT_HSI0_SYSREG_HSI0_PCLK>; 1575 }; 1576 1577 usbdrd31_phy: phy@11100000 { 1578 compatible = "google,gs101-usb31drd-phy"; 1579 reg = <0x11100000 0x0200>, 1580 <0x110f0000 0x0800>, 1581 <0x110e0000 0x2800>; 1582 reg-names = "phy", "pcs", "pma"; 1583 clocks = <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_ACLK_PHYCTRL>, 1584 <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_I_USB20_PHY_REFCLK_26>, 1585 <&cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_CTRL_ACLK>, 1586 <&cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_CTRL_PCLK>, 1587 <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_I_USBDPPHY_SCL_APB_PCLK>; 1588 clock-names = "phy", "ref", "ctrl_aclk", "ctrl_pclk", "scl_pclk"; 1589 #phy-cells = <1>; 1590 samsung,pmu-syscon = <&pmu_system_controller>; 1591 status = "disabled"; 1592 }; 1593 1594 usbdrd31: usb@11110000 { 1595 compatible = "google,gs101-dwusb3"; 1596 ranges = <0x0 0x11110000 0x10000>; 1597 clocks = <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_BUS_CLK_EARLY>, 1598 <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_SUSPEND_CLK_26>, 1599 <&cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_LINK_ACLK>, 1600 <&cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_LINK_PCLK>; 1601 clock-names = "bus_early", "susp_clk", "link_aclk", "link_pclk"; 1602 #address-cells = <1>; 1603 #size-cells = <1>; 1604 status = "disabled"; 1605 1606 usbdrd31_dwc3: usb@0 { 1607 compatible = "snps,dwc3"; 1608 reg = <0x0 0x10000>; 1609 clocks = <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_REF_CLK_40>; 1610 clock-names = "ref"; 1611 interrupts = <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH 0>; 1612 phys = <&usbdrd31_phy 0>, <&usbdrd31_phy 1>; 1613 phy-names = "usb2-phy", "usb3-phy"; 1614 snps,has-lpm-erratum; 1615 snps,dis_u2_susphy_quirk; 1616 snps,dis_u3_susphy_quirk; 1617 status = "disabled"; 1618 }; 1619 }; 1620 1621 pinctrl_hsi1: pinctrl@11840000 { 1622 compatible = "google,gs101-pinctrl"; 1623 reg = <0x11840000 0x00001000>; 1624 /* TODO: update once support for this CMU exists */ 1625 clocks = <0>; 1626 clock-names = "pclk"; 1627 interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH 0>; 1628 }; 1629 1630 cmu_hsi2: clock-controller@14400000 { 1631 compatible = "google,gs101-cmu-hsi2"; 1632 reg = <0x14400000 0x10000>; 1633 #clock-cells = <1>; 1634 clocks = <&ext_24_5m>, 1635 <&cmu_top CLK_DOUT_CMU_HSI2_BUS>, 1636 <&cmu_top CLK_DOUT_CMU_HSI2_PCIE>, 1637 <&cmu_top CLK_DOUT_CMU_HSI2_UFS_EMBD>, 1638 <&cmu_top CLK_DOUT_CMU_HSI2_MMC_CARD>; 1639 clock-names = "oscclk", "bus", "pcie", "ufs", "mmc"; 1640 }; 1641 1642 sysreg_hsi2: syscon@14420000 { 1643 compatible = "google,gs101-hsi2-sysreg", "syscon"; 1644 reg = <0x14420000 0x10000>; 1645 clocks = <&cmu_hsi2 CLK_GOUT_HSI2_SYSREG_HSI2_PCLK>; 1646 }; 1647 1648 pinctrl_hsi2: pinctrl@14440000 { 1649 compatible = "google,gs101-pinctrl"; 1650 reg = <0x14440000 0x00001000>; 1651 clocks = <&cmu_hsi2 CLK_GOUT_HSI2_GPIO_HSI2_PCLK>; 1652 clock-names = "pclk"; 1653 interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>; 1654 }; 1655 1656 ufs_0: ufs@14700000 { 1657 compatible = "google,gs101-ufs"; 1658 reg = <0x14700000 0x200>, 1659 <0x14701100 0x200>, 1660 <0x14780000 0xa000>, 1661 <0x14600000 0x100>; 1662 reg-names = "hci", "vs_hci", "unipro", "ufsp"; 1663 interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH 0>; 1664 clocks = <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_ACLK>, 1665 <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_CLK_UNIPRO>, 1666 <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_FMP_CLK>, 1667 <&cmu_hsi2 CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_ACLK>, 1668 <&cmu_hsi2 CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_PCLK>, 1669 <&cmu_hsi2 CLK_GOUT_HSI2_SYSREG_HSI2_PCLK>; 1670 clock-names = "core_clk", "sclk_unipro_main", "fmp", 1671 "aclk", "pclk", "sysreg"; 1672 dma-coherent; 1673 freq-table-hz = <0 0>, <0 0>, <0 0>, <0 0>, <0 0>, <0 0>; 1674 pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>; 1675 pinctrl-names = "default"; 1676 phys = <&ufs_0_phy>; 1677 phy-names = "ufs-phy"; 1678 samsung,sysreg = <&sysreg_hsi2 0x710>; 1679 status = "disabled"; 1680 }; 1681 1682 ufs_0_phy: phy@14704000 { 1683 compatible = "google,gs101-ufs-phy"; 1684 reg = <0x14704000 0x3000>; 1685 reg-names = "phy-pma"; 1686 samsung,pmu-syscon = <&pmu_system_controller>; 1687 #phy-cells = <0>; 1688 clocks = <&ext_24_5m>; 1689 clock-names = "ref_clk"; 1690 status = "disabled"; 1691 }; 1692 1693 cmu_apm: clock-controller@17400000 { 1694 compatible = "google,gs101-cmu-apm"; 1695 reg = <0x17400000 0x10000>; 1696 #clock-cells = <1>; 1697 1698 clocks = <&ext_24_5m>; 1699 clock-names = "oscclk"; 1700 }; 1701 1702 sysreg_apm: syscon@17420000 { 1703 compatible = "google,gs101-apm-sysreg", "syscon"; 1704 reg = <0x17420000 0x10000>; 1705 }; 1706 1707 pmu_system_controller: system-controller@17460000 { 1708 compatible = "google,gs101-pmu", "syscon"; 1709 reg = <0x17460000 0x10000>; 1710 google,pmu-intr-gen-syscon = <&pmu_intr_gen>; 1711 1712 poweroff: syscon-poweroff { 1713 compatible = "syscon-poweroff"; 1714 offset = <0x3e9c>; /* PAD_CTRL_PWR_HOLD */ 1715 mask = <0x00000100>; 1716 value = <0x0>; 1717 }; 1718 1719 reboot: syscon-reboot { 1720 compatible = "google,gs101-reboot"; 1721 }; 1722 1723 reboot-mode { 1724 compatible = "syscon-reboot-mode"; 1725 offset = <0x0810>; /* EXYNOS_PMU_SYSIP_DAT0 */ 1726 mode-bootloader = <0xfc>; 1727 mode-charge = <0x0a>; 1728 mode-dm-verity-device-corrupted = <0x50>; 1729 mode-fastboot = <0xfa>; 1730 mode-reboot-ab-update = <0x52>; 1731 mode-recovery = <0xff>; 1732 mode-rescue = <0xf9>; 1733 mode-shutdown-thermal = <0x51>; 1734 mode-shutdown-thermal-battery = <0x51>; 1735 }; 1736 }; 1737 1738 pmu_intr_gen: syscon@17470000 { 1739 compatible = "google,gs101-pmu-intr-gen", "syscon"; 1740 reg = <0x17470000 0x10000>; 1741 }; 1742 1743 pinctrl_gpio_alive: pinctrl@174d0000 { 1744 compatible = "google,gs101-pinctrl"; 1745 reg = <0x174d0000 0x00001000>; 1746 clocks = <&cmu_apm CLK_GOUT_APM_APBIF_GPIO_ALIVE_PCLK>; 1747 clock-names = "pclk"; 1748 1749 wakeup-interrupt-controller { 1750 compatible = "google,gs101-wakeup-eint", 1751 "samsung,exynos850-wakeup-eint", 1752 "samsung,exynos7-wakeup-eint"; 1753 }; 1754 }; 1755 1756 pinctrl_far_alive: pinctrl@174e0000 { 1757 compatible = "google,gs101-pinctrl"; 1758 reg = <0x174e0000 0x00001000>; 1759 clocks = <&cmu_apm CLK_GOUT_APM_APBIF_GPIO_FAR_ALIVE_PCLK>; 1760 clock-names = "pclk"; 1761 1762 wakeup-interrupt-controller { 1763 compatible = "google,gs101-wakeup-eint", 1764 "samsung,exynos850-wakeup-eint", 1765 "samsung,exynos7-wakeup-eint"; 1766 }; 1767 }; 1768 1769 ap2apm_mailbox: mailbox@17610000 { 1770 compatible = "google,gs101-mbox"; 1771 reg = <0x17610000 0x1000>; 1772 clocks = <&cmu_apm CLK_GOUT_APM_MAILBOX_APM_AP_PCLK>; 1773 clock-names = "pclk"; 1774 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH 0>; 1775 #mbox-cells = <0>; 1776 }; 1777 1778 pinctrl_gsactrl: pinctrl@17940000 { 1779 compatible = "google,gs101-pinctrl"; 1780 reg = <0x17940000 0x00001000>; 1781 /* TODO: update once support for this CMU exists */ 1782 clocks = <0>; 1783 clock-names = "pclk"; 1784 }; 1785 1786 pinctrl_gsacore: pinctrl@17a80000 { 1787 compatible = "google,gs101-pinctrl"; 1788 reg = <0x17a80000 0x00001000>; 1789 /* TODO: update once support for this CMU exists */ 1790 clocks = <0>; 1791 clock-names = "pclk"; 1792 status = "disabled"; 1793 }; 1794 1795 cmu_top: clock-controller@1e080000 { 1796 compatible = "google,gs101-cmu-top"; 1797 reg = <0x1e080000 0x10000>; 1798 #clock-cells = <1>; 1799 1800 clocks = <&ext_24_5m>; 1801 clock-names = "oscclk"; 1802 }; 1803 }; 1804 1805 apm_sram: sram@2039000 { 1806 compatible = "mmio-sram"; 1807 reg = <0x0 0x2039000 0x40000>; 1808 #address-cells = <1>; 1809 #size-cells = <1>; 1810 ranges = <0x0 0x0 0x2039000 0x40000>; 1811 }; 1812 1813 timer { 1814 compatible = "arm,armv8-timer"; 1815 interrupts = 1816 <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>, 1817 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>, 1818 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>, 1819 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>; 1820 }; 1821}; 1822 1823#include "gs101-pinctrl.dtsi"
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