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exynosautov920.dtsi
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linux-6.19.14/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Samsung's ExynosAutov920 SoC device tree source 4 * 5 * Copyright (c) 2023 Samsung Electronics Co., Ltd. 6 * 7 */ 8 9#include <dt-bindings/clock/samsung,exynosautov920.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/soc/samsung,exynos-usi.h> 12 13/ { 14 compatible = "samsung,exynosautov920"; 15 #address-cells = <2>; 16 #size-cells = <1>; 17 18 interrupt-parent = <&gic>; 19 20 aliases { 21 pinctrl0 = &pinctrl_alive; 22 pinctrl1 = &pinctrl_aud; 23 pinctrl2 = &pinctrl_hsi0; 24 pinctrl3 = &pinctrl_hsi1; 25 pinctrl4 = &pinctrl_hsi2; 26 pinctrl5 = &pinctrl_hsi2ufs; 27 pinctrl6 = &pinctrl_peric0; 28 pinctrl7 = &pinctrl_peric1; 29 }; 30 31 arm-pmu { 32 compatible = "arm,cortex-a78-pmu"; 33 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 34 }; 35 36 xtcxo: clock { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 clock-output-names = "oscclk"; 40 }; 41 42 cpus: cpus { 43 #address-cells = <2>; 44 #size-cells = <0>; 45 46 cpu-map { 47 cluster0 { 48 core0 { 49 cpu = <&cpu0>; 50 }; 51 core1 { 52 cpu = <&cpu1>; 53 }; 54 core2 { 55 cpu = <&cpu2>; 56 }; 57 core3 { 58 cpu = <&cpu3>; 59 }; 60 }; 61 62 cluster1 { 63 core0 { 64 cpu = <&cpu4>; 65 }; 66 core1 { 67 cpu = <&cpu5>; 68 }; 69 core2 { 70 cpu = <&cpu6>; 71 }; 72 core3 { 73 cpu = <&cpu7>; 74 }; 75 }; 76 77 cluster2 { 78 core0 { 79 cpu = <&cpu8>; 80 }; 81 core1 { 82 cpu = <&cpu9>; 83 }; 84 }; 85 }; 86 87 cpu0: cpu@0 { 88 device_type = "cpu"; 89 compatible = "arm,cortex-a78ae"; 90 reg = <0x0 0x0>; 91 enable-method = "psci"; 92 i-cache-size = <0x10000>; 93 i-cache-line-size = <64>; 94 i-cache-sets = <256>; 95 d-cache-size = <0x10000>; 96 d-cache-line-size = <64>; 97 d-cache-sets = <256>; 98 next-level-cache = <&l2_cache_cl0>; 99 }; 100 101 cpu1: cpu@100 { 102 device_type = "cpu"; 103 compatible = "arm,cortex-a78ae"; 104 reg = <0x0 0x100>; 105 enable-method = "psci"; 106 i-cache-size = <0x10000>; 107 i-cache-line-size = <64>; 108 i-cache-sets = <256>; 109 d-cache-size = <0x10000>; 110 d-cache-line-size = <64>; 111 d-cache-sets = <256>; 112 next-level-cache = <&l2_cache_cl0>; 113 }; 114 115 cpu2: cpu@200 { 116 device_type = "cpu"; 117 compatible = "arm,cortex-a78ae"; 118 reg = <0x0 0x200>; 119 enable-method = "psci"; 120 i-cache-size = <0x10000>; 121 i-cache-line-size = <64>; 122 i-cache-sets = <256>; 123 d-cache-size = <0x10000>; 124 d-cache-line-size = <64>; 125 d-cache-sets = <256>; 126 next-level-cache = <&l2_cache_cl0>; 127 }; 128 129 cpu3: cpu@300 { 130 device_type = "cpu"; 131 compatible = "arm,cortex-a78ae"; 132 reg = <0x0 0x300>; 133 enable-method = "psci"; 134 i-cache-size = <0x10000>; 135 i-cache-line-size = <64>; 136 i-cache-sets = <256>; 137 d-cache-size = <0x10000>; 138 d-cache-line-size = <64>; 139 d-cache-sets = <256>; 140 next-level-cache = <&l2_cache_cl0>; 141 }; 142 143 cpu4: cpu@10000 { 144 device_type = "cpu"; 145 compatible = "arm,cortex-a78ae"; 146 reg = <0x0 0x10000>; 147 enable-method = "psci"; 148 i-cache-size = <0x10000>; 149 i-cache-line-size = <64>; 150 i-cache-sets = <256>; 151 d-cache-size = <0x10000>; 152 d-cache-line-size = <64>; 153 d-cache-sets = <256>; 154 next-level-cache = <&l2_cache_cl1>; 155 }; 156 157 cpu5: cpu@10100 { 158 device_type = "cpu"; 159 compatible = "arm,cortex-a78ae"; 160 reg = <0x0 0x10100>; 161 enable-method = "psci"; 162 i-cache-size = <0x10000>; 163 i-cache-line-size = <64>; 164 i-cache-sets = <256>; 165 d-cache-size = <0x10000>; 166 d-cache-line-size = <64>; 167 d-cache-sets = <256>; 168 next-level-cache = <&l2_cache_cl1>; 169 }; 170 171 cpu6: cpu@10200 { 172 device_type = "cpu"; 173 compatible = "arm,cortex-a78ae"; 174 reg = <0x0 0x10200>; 175 enable-method = "psci"; 176 i-cache-size = <0x10000>; 177 i-cache-line-size = <64>; 178 i-cache-sets = <256>; 179 d-cache-size = <0x10000>; 180 d-cache-line-size = <64>; 181 d-cache-sets = <256>; 182 next-level-cache = <&l2_cache_cl1>; 183 }; 184 185 cpu7: cpu@10300 { 186 device_type = "cpu"; 187 compatible = "arm,cortex-a78ae"; 188 reg = <0x0 0x10300>; 189 enable-method = "psci"; 190 i-cache-size = <0x10000>; 191 i-cache-line-size = <64>; 192 i-cache-sets = <256>; 193 d-cache-size = <0x10000>; 194 d-cache-line-size = <64>; 195 d-cache-sets = <256>; 196 next-level-cache = <&l2_cache_cl1>; 197 }; 198 199 cpu8: cpu@20000 { 200 device_type = "cpu"; 201 compatible = "arm,cortex-a78ae"; 202 reg = <0x0 0x20000>; 203 enable-method = "psci"; 204 i-cache-size = <0x10000>; 205 i-cache-line-size = <64>; 206 i-cache-sets = <256>; 207 d-cache-size = <0x10000>; 208 d-cache-line-size = <64>; 209 d-cache-sets = <256>; 210 next-level-cache = <&l2_cache_cl2>; 211 }; 212 213 cpu9: cpu@20100 { 214 device_type = "cpu"; 215 compatible = "arm,cortex-a78ae"; 216 reg = <0x0 0x20100>; 217 enable-method = "psci"; 218 i-cache-size = <0x10000>; 219 i-cache-line-size = <64>; 220 i-cache-sets = <256>; 221 d-cache-size = <0x10000>; 222 d-cache-line-size = <64>; 223 d-cache-sets = <256>; 224 next-level-cache = <&l2_cache_cl2>; 225 }; 226 227 l2_cache_cl0: l2-cache0 { 228 compatible = "cache"; 229 cache-level = <2>; 230 cache-unified; 231 cache-size = <0x40000>; 232 cache-line-size = <64>; 233 cache-sets = <512>; 234 next-level-cache = <&l3_cache_cl0>; 235 }; 236 237 l2_cache_cl1: l2-cache1 { 238 compatible = "cache"; 239 cache-level = <2>; 240 cache-unified; 241 cache-size = <0x40000>; 242 cache-line-size = <64>; 243 cache-sets = <512>; 244 next-level-cache = <&l3_cache_cl1>; 245 }; 246 247 l2_cache_cl2: l2-cache2 { 248 compatible = "cache"; 249 cache-level = <2>; 250 cache-unified; 251 cache-size = <0x40000>; 252 cache-line-size = <64>; 253 cache-sets = <512>; 254 next-level-cache = <&l3_cache_cl2>; 255 }; 256 257 l3_cache_cl0: l3-cache0 { 258 compatible = "cache"; 259 cache-level = <3>; 260 cache-unified; 261 cache-size = <0x200000>;/* 2MB L3 cache for cpu cluster-0 */ 262 cache-line-size = <64>; 263 cache-sets = <2048>; 264 }; 265 266 l3_cache_cl1: l3-cache1 { 267 compatible = "cache"; 268 cache-level = <3>; 269 cache-unified; 270 cache-size = <0x200000>;/* 2MB L3 cache for cpu cluster-1 */ 271 cache-line-size = <64>; 272 cache-sets = <2048>; 273 }; 274 275 l3_cache_cl2: l3-cache2 { 276 compatible = "cache"; 277 cache-level = <3>; 278 cache-unified; 279 cache-size = <0x100000>;/* 1MB L3 cache for cpu cluster-2 */ 280 cache-line-size = <64>; 281 cache-sets = <1365>; 282 }; 283 }; 284 285 psci { 286 compatible = "arm,psci-1.0"; 287 method = "smc"; 288 }; 289 290 soc: soc@0 { 291 compatible = "simple-bus"; 292 #address-cells = <1>; 293 #size-cells = <1>; 294 ranges = <0x0 0x0 0x0 0x20000000>; 295 296 chipid@10000000 { 297 compatible = "samsung,exynosautov920-chipid", 298 "samsung,exynos850-chipid"; 299 reg = <0x10000000 0x24>; 300 }; 301 302 cmu_misc: clock-controller@10020000 { 303 compatible = "samsung,exynosautov920-cmu-misc"; 304 reg = <0x10020000 0x8000>; 305 #clock-cells = <1>; 306 307 clocks = <&xtcxo>, 308 <&cmu_top DOUT_CLKCMU_MISC_NOC>; 309 clock-names = "oscclk", 310 "noc"; 311 }; 312 313 watchdog_cl0: watchdog@10060000 { 314 compatible = "samsung,exynosautov920-wdt"; 315 reg = <0x10060000 0x100>; 316 interrupts = <GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH>; 317 clocks = <&xtcxo>, <&xtcxo>; 318 clock-names = "watchdog", "watchdog_src"; 319 samsung,syscon-phandle = <&pmu_system_controller>; 320 samsung,cluster-index = <0>; 321 }; 322 323 watchdog_cl1: watchdog@10070000 { 324 compatible = "samsung,exynosautov920-wdt"; 325 reg = <0x10070000 0x100>; 326 interrupts = <GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH>; 327 clocks = <&xtcxo>, <&xtcxo>; 328 clock-names = "watchdog", "watchdog_src"; 329 samsung,syscon-phandle = <&pmu_system_controller>; 330 samsung,cluster-index = <1>; 331 }; 332 333 gic: interrupt-controller@10400000 { 334 compatible = "arm,gic-v3"; 335 #interrupt-cells = <3>; 336 #address-cells = <0>; 337 interrupt-controller; 338 reg = <0x10400000 0x10000>, 339 <0x10460000 0x140000>; 340 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 341 }; 342 343 spdma0: dma-controller@10180000 { 344 compatible = "arm,pl330", "arm,primecell"; 345 reg = <0x10180000 0x1000>; 346 interrupts = <GIC_SPI 918 IRQ_TYPE_LEVEL_HIGH>; 347 clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>; 348 clock-names = "apb_pclk"; 349 #dma-cells = <1>; 350 }; 351 352 spdma1: dma-controller@10190000 { 353 compatible = "arm,pl330", "arm,primecell"; 354 reg = <0x10190000 0x1000>; 355 interrupts = <GIC_SPI 917 IRQ_TYPE_LEVEL_HIGH>; 356 clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>; 357 clock-names = "apb_pclk"; 358 #dma-cells = <1>; 359 }; 360 361 pdma0: dma-controller@101a0000 { 362 compatible = "arm,pl330", "arm,primecell"; 363 reg = <0x101a0000 0x1000>; 364 interrupts = <GIC_SPI 916 IRQ_TYPE_LEVEL_HIGH>; 365 clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>; 366 clock-names = "apb_pclk"; 367 #dma-cells = <1>; 368 }; 369 370 pdma1: dma-controller@101b0000 { 371 compatible = "arm,pl330", "arm,primecell"; 372 reg = <0x101b0000 0x1000>; 373 interrupts = <GIC_SPI 915 IRQ_TYPE_LEVEL_HIGH>; 374 clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>; 375 clock-names = "apb_pclk"; 376 #dma-cells = <1>; 377 }; 378 379 pdma2: dma-controller@101c0000 { 380 compatible = "arm,pl330", "arm,primecell"; 381 reg = <0x101c0000 0x1000>; 382 interrupts = <GIC_SPI 914 IRQ_TYPE_LEVEL_HIGH>; 383 clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>; 384 clock-names = "apb_pclk"; 385 #dma-cells = <1>; 386 }; 387 388 pdma3: dma-controller@101d0000 { 389 compatible = "arm,pl330", "arm,primecell"; 390 reg = <0x101d0000 0x1000>; 391 interrupts = <GIC_SPI 913 IRQ_TYPE_LEVEL_HIGH>; 392 clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>; 393 clock-names = "apb_pclk"; 394 #dma-cells = <1>; 395 }; 396 397 pdma4: dma-controller@101e0000 { 398 compatible = "arm,pl330", "arm,primecell"; 399 reg = <0x101e0000 0x1000>; 400 interrupts = <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>; 401 clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>; 402 clock-names = "apb_pclk"; 403 #dma-cells = <1>; 404 }; 405 406 cmu_peric0: clock-controller@10800000 { 407 compatible = "samsung,exynosautov920-cmu-peric0"; 408 reg = <0x10800000 0x8000>; 409 #clock-cells = <1>; 410 411 clocks = <&xtcxo>, 412 <&cmu_top DOUT_CLKCMU_PERIC0_NOC>, 413 <&cmu_top DOUT_CLKCMU_PERIC0_IP>; 414 clock-names = "oscclk", 415 "noc", 416 "ip"; 417 }; 418 419 syscon_peric0: syscon@10820000 { 420 compatible = "samsung,exynosautov920-peric0-sysreg", 421 "syscon"; 422 reg = <0x10820000 0x2000>; 423 }; 424 425 pinctrl_peric0: pinctrl@10830000 { 426 compatible = "samsung,exynosautov920-pinctrl"; 427 reg = <0x10830000 0x10000>; 428 interrupts = <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>; 429 }; 430 431 usi_0: usi@108800c0 { 432 compatible = "samsung,exynosautov920-usi", 433 "samsung,exynos850-usi"; 434 reg = <0x108800c0 0x20>; 435 samsung,sysreg = <&syscon_peric0 0x1000>; 436 samsung,mode = <USI_MODE_UART>; 437 #address-cells = <1>; 438 #size-cells = <1>; 439 ranges; 440 clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, 441 <&cmu_peric0 CLK_DOUT_PERIC0_USI00_USI>; 442 clock-names = "pclk", "ipclk"; 443 status = "disabled"; 444 445 serial_0: serial@10880000 { 446 compatible = "samsung,exynosautov920-uart", 447 "samsung,exynos850-uart"; 448 reg = <0x10880000 0xc0>; 449 interrupts = <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>; 450 pinctrl-names = "default"; 451 pinctrl-0 = <&uart0_bus>; 452 clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, 453 <&cmu_peric0 CLK_DOUT_PERIC0_USI00_USI>; 454 clock-names = "uart", "clk_uart_baud0"; 455 samsung,uart-fifosize = <256>; 456 status = "disabled"; 457 }; 458 459 spi_0: spi@10880000 { 460 compatible = "samsung,exynosautov920-spi", 461 "samsung,exynos850-spi"; 462 reg = <0x10880000 0x30>; 463 interrupts = <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>; 464 pinctrl-names = "default"; 465 pinctrl-0 = <&spi0_bus &spi0_cs_func>; 466 clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, 467 <&cmu_peric0 CLK_DOUT_PERIC0_USI00_USI>; 468 clock-names = "spi", "spi_busclk0"; 469 samsung,spi-src-clk = <0>; 470 dmas = <&pdma0 1>, <&pdma0 0>; 471 dma-names = "tx", "rx"; 472 num-cs = <1>; 473 #address-cells = <1>; 474 #size-cells = <0>; 475 fifo-depth = <256>; 476 status = "disabled"; 477 }; 478 }; 479 480 usi_1: usi@108a00c0 { 481 compatible = "samsung,exynosautov920-usi", 482 "samsung,exynos850-usi"; 483 reg = <0x108a00c0 0x20>; 484 samsung,sysreg = <&syscon_peric0 0x1008>; 485 samsung,mode = <USI_V2_UART>; 486 #address-cells = <1>; 487 #size-cells = <1>; 488 ranges; 489 clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, 490 <&cmu_peric0 CLK_DOUT_PERIC0_USI01_USI>; 491 clock-names = "pclk", "ipclk"; 492 status = "disabled"; 493 494 serial_1: serial@108a0000 { 495 compatible = "samsung,exynosautov920-uart", 496 "samsung,exynos850-uart"; 497 reg = <0x108a0000 0xc0>; 498 interrupts = <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>; 499 pinctrl-names = "default"; 500 pinctrl-0 = <&uart1_bus>; 501 clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, 502 <&cmu_peric0 CLK_DOUT_PERIC0_USI01_USI>; 503 clock-names = "uart", "clk_uart_baud0"; 504 samsung,uart-fifosize = <256>; 505 status = "disabled"; 506 }; 507 508 spi_1: spi@108a0000 { 509 compatible = "samsung,exynosautov920-spi", 510 "samsung,exynos850-spi"; 511 reg = <0x108a0000 0x30>; 512 interrupts = <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>; 513 pinctrl-names = "default"; 514 pinctrl-0 = <&spi1_bus &spi1_cs_func>; 515 clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, 516 <&cmu_peric0 CLK_DOUT_PERIC0_USI01_USI>; 517 clock-names = "spi", "spi_busclk0"; 518 samsung,spi-src-clk = <0>; 519 dmas = <&pdma0 3>, <&pdma0 2>; 520 dma-names = "tx", "rx"; 521 num-cs = <1>; 522 #address-cells = <1>; 523 #size-cells = <0>; 524 fifo-depth = <256>; 525 status = "disabled"; 526 }; 527 }; 528 529 usi_2: usi@108c00c0 { 530 compatible = "samsung,exynosautov920-usi", 531 "samsung,exynos850-usi"; 532 reg = <0x108c00c0 0x20>; 533 samsung,sysreg = <&syscon_peric0 0x1010>; 534 samsung,mode = <USI_V2_UART>; 535 #address-cells = <1>; 536 #size-cells = <1>; 537 ranges; 538 clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, 539 <&cmu_peric0 CLK_DOUT_PERIC0_USI02_USI>; 540 clock-names = "pclk", "ipclk"; 541 status = "disabled"; 542 543 serial_2: serial@108c0000 { 544 compatible = "samsung,exynosautov920-uart", 545 "samsung,exynos850-uart"; 546 reg = <0x108c0000 0xc0>; 547 interrupts = <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>; 548 pinctrl-names = "default"; 549 pinctrl-0 = <&uart2_bus>; 550 clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, 551 <&cmu_peric0 CLK_DOUT_PERIC0_USI02_USI>; 552 clock-names = "uart", "clk_uart_baud0"; 553 samsung,uart-fifosize = <64>; 554 status = "disabled"; 555 }; 556 557 spi_2: spi@108c0000 { 558 compatible = "samsung,exynosautov920-spi", 559 "samsung,exynos850-spi"; 560 reg = <0x108c0000 0x30>; 561 interrupts = <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>; 562 pinctrl-names = "default"; 563 pinctrl-0 = <&spi2_bus &spi2_cs_func>; 564 clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, 565 <&cmu_peric0 CLK_DOUT_PERIC0_USI02_USI>; 566 clock-names = "spi", "spi_busclk0"; 567 samsung,spi-src-clk = <0>; 568 dmas = <&pdma0 5>, <&pdma0 4>; 569 dma-names = "tx", "rx"; 570 num-cs = <1>; 571 #address-cells = <1>; 572 #size-cells = <0>; 573 fifo-depth = <64>; 574 status = "disabled"; 575 }; 576 }; 577 578 usi_3: usi@108e00c0 { 579 compatible = "samsung,exynosautov920-usi", 580 "samsung,exynos850-usi"; 581 reg = <0x108e00c0 0x20>; 582 samsung,sysreg = <&syscon_peric0 0x1018>; 583 samsung,mode = <USI_V2_UART>; 584 #address-cells = <1>; 585 #size-cells = <1>; 586 ranges; 587 clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, 588 <&cmu_peric0 CLK_DOUT_PERIC0_USI03_USI>; 589 clock-names = "pclk", "ipclk"; 590 status = "disabled"; 591 592 serial_3: serial@108e0000 { 593 compatible = "samsung,exynosautov920-uart", 594 "samsung,exynos850-uart"; 595 reg = <0x108e0000 0xc0>; 596 interrupts = <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>; 597 pinctrl-names = "default"; 598 pinctrl-0 = <&uart3_bus>; 599 clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, 600 <&cmu_peric0 CLK_DOUT_PERIC0_USI03_USI>; 601 clock-names = "uart", "clk_uart_baud0"; 602 samsung,uart-fifosize = <64>; 603 status = "disabled"; 604 }; 605 606 spi_3: spi@108e0000 { 607 compatible = "samsung,exynosautov920-spi", 608 "samsung,exynos850-spi"; 609 reg = <0x108e0000 0x30>; 610 interrupts = <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>; 611 pinctrl-names = "default"; 612 pinctrl-0 = <&spi3_bus &spi3_cs_func>; 613 clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, 614 <&cmu_peric0 CLK_DOUT_PERIC0_USI03_USI>; 615 clock-names = "spi", "spi_busclk0"; 616 samsung,spi-src-clk = <0>; 617 dmas = <&pdma0 7>, <&pdma0 6>; 618 dma-names = "tx", "rx"; 619 num-cs = <1>; 620 #address-cells = <1>; 621 #size-cells = <0>; 622 fifo-depth = <64>; 623 status = "disabled"; 624 }; 625 }; 626 627 usi_4: usi@109000c0 { 628 compatible = "samsung,exynosautov920-usi", 629 "samsung,exynos850-usi"; 630 reg = <0x109000c0 0x20>; 631 samsung,sysreg = <&syscon_peric0 0x1020>; 632 samsung,mode = <USI_V2_UART>; 633 #address-cells = <1>; 634 #size-cells = <1>; 635 ranges; 636 clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, 637 <&cmu_peric0 CLK_DOUT_PERIC0_USI04_USI>; 638 clock-names = "pclk", "ipclk"; 639 status = "disabled"; 640 641 serial_4: serial@10900000 { 642 compatible = "samsung,exynosautov920-uart", 643 "samsung,exynos850-uart"; 644 reg = <0x10900000 0xc0>; 645 interrupts = <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>; 646 pinctrl-names = "default"; 647 pinctrl-0 = <&uart4_bus>; 648 clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, 649 <&cmu_peric0 CLK_DOUT_PERIC0_USI04_USI>; 650 clock-names = "uart", "clk_uart_baud0"; 651 samsung,uart-fifosize = <64>; 652 status = "disabled"; 653 }; 654 655 spi_4: spi@10900000 { 656 compatible = "samsung,exynosautov920-spi", 657 "samsung,exynos850-spi"; 658 reg = <0x10900000 0x30>; 659 interrupts = <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>; 660 pinctrl-names = "default"; 661 pinctrl-0 = <&spi4_bus &spi4_cs_func>; 662 clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, 663 <&cmu_peric0 CLK_DOUT_PERIC0_USI04_USI>; 664 clock-names = "spi", "spi_busclk0"; 665 samsung,spi-src-clk = <0>; 666 dmas = <&pdma0 9>, <&pdma0 8>; 667 dma-names = "tx", "rx"; 668 num-cs = <1>; 669 #address-cells = <1>; 670 #size-cells = <0>; 671 fifo-depth = <64>; 672 status = "disabled"; 673 }; 674 }; 675 676 usi_5: usi@109200c0 { 677 compatible = "samsung,exynosautov920-usi", 678 "samsung,exynos850-usi"; 679 reg = <0x109200c0 0x20>; 680 samsung,sysreg = <&syscon_peric0 0x1028>; 681 samsung,mode = <USI_V2_UART>; 682 #address-cells = <1>; 683 #size-cells = <1>; 684 ranges; 685 clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, 686 <&cmu_peric0 CLK_DOUT_PERIC0_USI05_USI>; 687 clock-names = "pclk", "ipclk"; 688 status = "disabled"; 689 690 serial_5: serial@10920000 { 691 compatible = "samsung,exynosautov920-uart", 692 "samsung,exynos850-uart"; 693 reg = <0x10920000 0xc0>; 694 interrupts = <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>; 695 pinctrl-names = "default"; 696 pinctrl-0 = <&uart5_bus>; 697 clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, 698 <&cmu_peric0 CLK_DOUT_PERIC0_USI05_USI>; 699 clock-names = "uart", "clk_uart_baud0"; 700 samsung,uart-fifosize = <64>; 701 status = "disabled"; 702 }; 703 704 spi_5: spi@10920000 { 705 compatible = "samsung,exynosautov920-spi", 706 "samsung,exynos850-spi"; 707 reg = <0x10920000 0x30>; 708 interrupts = <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>; 709 pinctrl-names = "default"; 710 pinctrl-0 = <&spi5_bus &spi5_cs_func>; 711 clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, 712 <&cmu_peric0 CLK_DOUT_PERIC0_USI05_USI>; 713 clock-names = "spi", "spi_busclk0"; 714 samsung,spi-src-clk = <0>; 715 dmas = <&pdma0 11>, <&pdma0 10>; 716 dma-names = "tx", "rx"; 717 num-cs = <1>; 718 #address-cells = <1>; 719 #size-cells = <0>; 720 fifo-depth = <64>; 721 status = "disabled"; 722 }; 723 }; 724 725 usi_6: usi@109400c0 { 726 compatible = "samsung,exynosautov920-usi", 727 "samsung,exynos850-usi"; 728 reg = <0x109400c0 0x20>; 729 samsung,sysreg = <&syscon_peric0 0x1030>; 730 samsung,mode = <USI_V2_UART>; 731 #address-cells = <1>; 732 #size-cells = <1>; 733 ranges; 734 clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, 735 <&cmu_peric0 CLK_DOUT_PERIC0_USI06_USI>; 736 clock-names = "pclk", "ipclk"; 737 status = "disabled"; 738 739 serial_6: serial@10940000 { 740 compatible = "samsung,exynosautov920-uart", 741 "samsung,exynos850-uart"; 742 reg = <0x10940000 0xc0>; 743 interrupts = <GIC_SPI 776 IRQ_TYPE_LEVEL_HIGH>; 744 pinctrl-names = "default"; 745 pinctrl-0 = <&uart6_bus>; 746 clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, 747 <&cmu_peric0 CLK_DOUT_PERIC0_USI06_USI>; 748 clock-names = "uart", "clk_uart_baud0"; 749 samsung,uart-fifosize = <64>; 750 status = "disabled"; 751 }; 752 753 spi_6: spi@10940000 { 754 compatible = "samsung,exynosautov920-spi", 755 "samsung,exynos850-spi"; 756 reg = <0x10940000 0x30>; 757 interrupts = <GIC_SPI 776 IRQ_TYPE_LEVEL_HIGH>; 758 pinctrl-names = "default"; 759 pinctrl-0 = <&spi6_bus &spi6_cs_func>; 760 clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, 761 <&cmu_peric0 CLK_DOUT_PERIC0_USI06_USI>; 762 clock-names = "spi", "spi_busclk0"; 763 samsung,spi-src-clk = <0>; 764 dmas = <&pdma0 13>, <&pdma0 12>; 765 dma-names = "tx", "rx"; 766 num-cs = <1>; 767 #address-cells = <1>; 768 #size-cells = <0>; 769 fifo-depth = <64>; 770 status = "disabled"; 771 }; 772 }; 773 774 usi_7: usi@109600c0 { 775 compatible = "samsung,exynosautov920-usi", 776 "samsung,exynos850-usi"; 777 reg = <0x109600c0 0x20>; 778 samsung,sysreg = <&syscon_peric0 0x1038>; 779 samsung,mode = <USI_V2_UART>; 780 #address-cells = <1>; 781 #size-cells = <1>; 782 ranges; 783 clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, 784 <&cmu_peric0 CLK_DOUT_PERIC0_USI07_USI>; 785 clock-names = "pclk", "ipclk"; 786 status = "disabled"; 787 788 serial_7: serial@10960000 { 789 compatible = "samsung,exynosautov920-uart", 790 "samsung,exynos850-uart"; 791 reg = <0x10960000 0xc0>; 792 interrupts = <GIC_SPI 778 IRQ_TYPE_LEVEL_HIGH>; 793 pinctrl-names = "default"; 794 pinctrl-0 = <&uart7_bus>; 795 clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, 796 <&cmu_peric0 CLK_DOUT_PERIC0_USI07_USI>; 797 clock-names = "uart", "clk_uart_baud0"; 798 samsung,uart-fifosize = <64>; 799 status = "disabled"; 800 }; 801 802 spi_7: spi@10960000 { 803 compatible = "samsung,exynosautov920-spi", 804 "samsung,exynos850-spi"; 805 reg = <0x10960000 0x30>; 806 interrupts = <GIC_SPI 778 IRQ_TYPE_LEVEL_HIGH>; 807 pinctrl-names = "default"; 808 pinctrl-0 = <&spi7_bus &spi7_cs_func>; 809 clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, 810 <&cmu_peric0 CLK_DOUT_PERIC0_USI07_USI>; 811 clock-names = "spi", "spi_busclk0"; 812 samsung,spi-src-clk = <0>; 813 dmas = <&pdma0 15>, <&pdma0 14>; 814 dma-names = "tx", "rx"; 815 num-cs = <1>; 816 #address-cells = <1>; 817 #size-cells = <0>; 818 fifo-depth = <64>; 819 status = "disabled"; 820 }; 821 }; 822 823 usi_8: usi@109800c0 { 824 compatible = "samsung,exynosautov920-usi", 825 "samsung,exynos850-usi"; 826 reg = <0x109800c0 0x20>; 827 samsung,sysreg = <&syscon_peric0 0x1040>; 828 samsung,mode = <USI_V2_UART>; 829 #address-cells = <1>; 830 #size-cells = <1>; 831 ranges; 832 clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, 833 <&cmu_peric0 CLK_DOUT_PERIC0_USI08_USI>; 834 clock-names = "pclk", "ipclk"; 835 status = "disabled"; 836 837 serial_8: serial@10980000 { 838 compatible = "samsung,exynosautov920-uart", 839 "samsung,exynos850-uart"; 840 reg = <0x10980000 0xc0>; 841 interrupts = <GIC_SPI 780 IRQ_TYPE_LEVEL_HIGH>; 842 pinctrl-names = "default"; 843 pinctrl-0 = <&uart8_bus>; 844 clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, 845 <&cmu_peric0 CLK_DOUT_PERIC0_USI08_USI>; 846 clock-names = "uart", "clk_uart_baud0"; 847 samsung,uart-fifosize = <64>; 848 status = "disabled"; 849 }; 850 851 spi_8: spi@10980000 { 852 compatible = "samsung,exynosautov920-spi", 853 "samsung,exynos850-spi"; 854 reg = <0x10980000 0x30>; 855 interrupts = <GIC_SPI 780 IRQ_TYPE_LEVEL_HIGH>; 856 pinctrl-names = "default"; 857 pinctrl-0 = <&spi8_bus &spi8_cs_func>; 858 clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, 859 <&cmu_peric0 CLK_DOUT_PERIC0_USI08_USI>; 860 clock-names = "spi", "spi_busclk0"; 861 samsung,spi-src-clk = <0>; 862 dmas = <&pdma0 17>, <&pdma0 16>; 863 dma-names = "tx", "rx"; 864 num-cs = <1>; 865 #address-cells = <1>; 866 #size-cells = <0>; 867 fifo-depth = <64>; 868 status = "disabled"; 869 }; 870 871 }; 872 873 pwm: pwm@109b0000 { 874 compatible = "samsung,exynosautov920-pwm", 875 "samsung,exynos4210-pwm"; 876 reg = <0x109b0000 0x100>; 877 samsung,pwm-outputs = <0>, <1>, <2>, <3>; 878 #pwm-cells = <3>; 879 clocks = <&xtcxo>; 880 clock-names = "timers"; 881 status = "disabled"; 882 }; 883 884 cmu_peric1: clock-controller@10c00000 { 885 compatible = "samsung,exynosautov920-cmu-peric1"; 886 reg = <0x10c00000 0x8000>; 887 #clock-cells = <1>; 888 889 clocks = <&xtcxo>, 890 <&cmu_top DOUT_CLKCMU_PERIC1_NOC>, 891 <&cmu_top DOUT_CLKCMU_PERIC1_IP>; 892 clock-names = "oscclk", 893 "noc", 894 "ip"; 895 }; 896 897 syscon_peric1: syscon@10c20000 { 898 compatible = "samsung,exynosautov920-peric1-sysreg", 899 "syscon"; 900 reg = <0x10c20000 0x2000>; 901 }; 902 903 pinctrl_peric1: pinctrl@10c30000 { 904 compatible = "samsung,exynosautov920-pinctrl"; 905 reg = <0x10c30000 0x10000>; 906 interrupts = <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>; 907 }; 908 909 usi_9: usi@10c800c0 { 910 compatible = "samsung,exynosautov920-usi", 911 "samsung,exynos850-usi"; 912 reg = <0x10c800c0 0x20>; 913 samsung,sysreg = <&syscon_peric1 0x1000>; 914 samsung,mode = <USI_V2_UART>; 915 #address-cells = <1>; 916 #size-cells = <1>; 917 ranges; 918 clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, 919 <&cmu_peric1 CLK_DOUT_PERIC1_USI09_USI>; 920 clock-names = "pclk", "ipclk"; 921 status = "disabled"; 922 923 serial_9: serial@10c8000 { 924 compatible = "samsung,exynosautov920-uart", 925 "samsung,exynos850-uart"; 926 reg = <0x10c80000 0xc0>; 927 interrupts = <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>; 928 pinctrl-names = "default"; 929 pinctrl-0 = <&uart9_bus>; 930 clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, 931 <&cmu_peric1 CLK_DOUT_PERIC1_USI09_USI>; 932 clock-names = "uart", "clk_uart_baud0"; 933 samsung,uart-fifosize = <256>; 934 status = "disabled"; 935 }; 936 937 spi_9: spi@10c80000 { 938 compatible = "samsung,exynosautov920-spi", 939 "samsung,exynos850-spi"; 940 reg = <0x10c80000 0x30>; 941 interrupts = <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>; 942 pinctrl-names = "default"; 943 pinctrl-0 = <&spi9_bus &spi9_cs_func>; 944 clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, 945 <&cmu_peric1 CLK_DOUT_PERIC1_USI09_USI>; 946 clock-names = "spi", "spi_busclk0"; 947 samsung,spi-src-clk = <0>; 948 dmas = <&pdma1 1>, <&pdma1 0>; 949 dma-names = "tx", "rx"; 950 num-cs = <1>; 951 #address-cells = <1>; 952 #size-cells = <0>; 953 fifo-depth = <256>; 954 status = "disabled"; 955 }; 956 }; 957 958 usi_10: usi@10ca00c0 { 959 compatible = "samsung,exynosautov920-usi", 960 "samsung,exynos850-usi"; 961 reg = <0x10ca00c0 0x20>; 962 samsung,sysreg = <&syscon_peric1 0x1008>; 963 samsung,mode = <USI_V2_UART>; 964 #address-cells = <1>; 965 #size-cells = <1>; 966 ranges; 967 clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, 968 <&cmu_peric1 CLK_DOUT_PERIC1_USI10_USI>; 969 clock-names = "pclk", "ipclk"; 970 status = "disabled"; 971 972 serial_10: serial@10ca0000 { 973 compatible = "samsung,exynosautov920-uart", 974 "samsung,exynos850-uart"; 975 reg = <0x10ca0000 0xc0>; 976 interrupts = <GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH>; 977 pinctrl-names = "default"; 978 pinctrl-0 = <&uart10_bus>; 979 clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, 980 <&cmu_peric1 CLK_DOUT_PERIC1_USI10_USI>; 981 clock-names = "uart", "clk_uart_baud0"; 982 samsung,uart-fifosize = <64>; 983 status = "disabled"; 984 }; 985 986 spi_10: spi@10ca0000 { 987 compatible = "samsung,exynosautov920-spi", 988 "samsung,exynos850-spi"; 989 reg = <0x10ca0000 0x30>; 990 interrupts = <GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH>; 991 pinctrl-names = "default"; 992 pinctrl-0 = <&spi10_bus &spi10_cs_func>; 993 clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, 994 <&cmu_peric1 CLK_DOUT_PERIC1_USI10_USI>; 995 clock-names = "spi", "spi_busclk0"; 996 samsung,spi-src-clk = <0>; 997 dmas = <&pdma1 3>, <&pdma1 2>; 998 dma-names = "tx", "rx"; 999 num-cs = <1>; 1000 #address-cells = <1>; 1001 #size-cells = <0>; 1002 fifo-depth = <64>; 1003 status = "disabled"; 1004 }; 1005 }; 1006 1007 usi_11: usi@10cc00c0 { 1008 compatible = "samsung,exynosautov920-usi", 1009 "samsung,exynos850-usi"; 1010 reg = <0x10cc00c0 0x20>; 1011 samsung,sysreg = <&syscon_peric1 0x1010>; 1012 samsung,mode = <USI_V2_UART>; 1013 #address-cells = <1>; 1014 #size-cells = <1>; 1015 ranges; 1016 clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, 1017 <&cmu_peric1 CLK_DOUT_PERIC1_USI11_USI>; 1018 clock-names = "pclk", "ipclk"; 1019 status = "disabled"; 1020 1021 serial_11: serial@10cc0000 { 1022 compatible = "samsung,exynosautov920-uart", 1023 "samsung,exynos850-uart"; 1024 reg = <0x10cc0000 0xc0>; 1025 interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>; 1026 pinctrl-names = "default"; 1027 pinctrl-0 = <&uart11_bus>; 1028 clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, 1029 <&cmu_peric1 CLK_DOUT_PERIC1_USI11_USI>; 1030 clock-names = "uart", "clk_uart_baud0"; 1031 samsung,uart-fifosize = <64>; 1032 status = "disabled"; 1033 }; 1034 1035 spi_11: spi@10cc0000 { 1036 compatible = "samsung,exynosautov920-spi", 1037 "samsung,exynos850-spi"; 1038 reg = <0x10cc0000 0x30>; 1039 interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>; 1040 pinctrl-names = "default"; 1041 pinctrl-0 = <&spi11_bus &spi11_cs_func>; 1042 clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, 1043 <&cmu_peric1 CLK_DOUT_PERIC1_USI11_USI>; 1044 clock-names = "spi", "spi_busclk0"; 1045 samsung,spi-src-clk = <0>; 1046 dmas = <&pdma1 5>, <&pdma1 4>; 1047 dma-names = "tx", "rx"; 1048 num-cs = <1>; 1049 #address-cells = <1>; 1050 #size-cells = <0>; 1051 fifo-depth = <64>; 1052 status = "disabled"; 1053 }; 1054 }; 1055 1056 usi_12: usi@10ce00c0 { 1057 compatible = "samsung,exynosautov920-usi", 1058 "samsung,exynos850-usi"; 1059 reg = <0x10ce00c0 0x20>; 1060 samsung,sysreg = <&syscon_peric1 0x1018>; 1061 samsung,mode = <USI_V2_UART>; 1062 #address-cells = <1>; 1063 #size-cells = <1>; 1064 ranges; 1065 clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, 1066 <&cmu_peric1 CLK_DOUT_PERIC1_USI12_USI>; 1067 clock-names = "pclk", "ipclk"; 1068 status = "disabled"; 1069 1070 serial_12: serial@10ce0000 { 1071 compatible = "samsung,exynosautov920-uart", 1072 "samsung,exynos850-uart"; 1073 reg = <0x10ce0000 0xc0>; 1074 interrupts = <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>; 1075 pinctrl-names = "default"; 1076 pinctrl-0 = <&uart12_bus>; 1077 clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, 1078 <&cmu_peric1 CLK_DOUT_PERIC1_USI12_USI>; 1079 clock-names = "uart", "clk_uart_baud0"; 1080 samsung,uart-fifosize = <64>; 1081 status = "disabled"; 1082 }; 1083 1084 spi_12: spi@10ce0000 { 1085 compatible = "samsung,exynosautov920-spi", 1086 "samsung,exynos850-spi"; 1087 reg = <0x10ce0000 0x30>; 1088 interrupts = <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>; 1089 pinctrl-names = "default"; 1090 pinctrl-0 = <&spi12_bus &spi12_cs_func>; 1091 clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, 1092 <&cmu_peric1 CLK_DOUT_PERIC1_USI12_USI>; 1093 clock-names = "spi", "spi_busclk0"; 1094 samsung,spi-src-clk = <0>; 1095 dmas = <&pdma1 7>, <&pdma1 6>; 1096 dma-names = "tx", "rx"; 1097 num-cs = <1>; 1098 #address-cells = <1>; 1099 #size-cells = <0>; 1100 fifo-depth = <64>; 1101 status = "disabled"; 1102 }; 1103 }; 1104 1105 usi_13: usi@10d000c0 { 1106 compatible = "samsung,exynosautov920-usi", 1107 "samsung,exynos850-usi"; 1108 reg = <0x10d000c0 0x20>; 1109 samsung,sysreg = <&syscon_peric1 0x1020>; 1110 samsung,mode = <USI_V2_UART>; 1111 #address-cells = <1>; 1112 #size-cells = <1>; 1113 ranges; 1114 clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, 1115 <&cmu_peric1 CLK_DOUT_PERIC1_USI13_USI>; 1116 clock-names = "pclk", "ipclk"; 1117 status = "disabled"; 1118 1119 serial_13: serial@10d00000 { 1120 compatible = "samsung,exynosautov920-uart", 1121 "samsung,exynos850-uart"; 1122 reg = <0x10d00000 0xc0>; 1123 interrupts = <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>; 1124 pinctrl-names = "default"; 1125 pinctrl-0 = <&uart13_bus>; 1126 clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, 1127 <&cmu_peric1 CLK_DOUT_PERIC1_USI13_USI>; 1128 clock-names = "uart", "clk_uart_baud0"; 1129 samsung,uart-fifosize = <64>; 1130 status = "disabled"; 1131 }; 1132 1133 spi_13: spi@10d00000 { 1134 compatible = "samsung,exynosautov920-spi", 1135 "samsung,exynos850-spi"; 1136 reg = <0x10d00000 0x30>; 1137 interrupts = <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>; 1138 pinctrl-names = "default"; 1139 pinctrl-0 = <&spi13_bus &spi13_cs_func>; 1140 clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, 1141 <&cmu_peric1 CLK_DOUT_PERIC1_USI13_USI>; 1142 clock-names = "spi", "spi_busclk0"; 1143 samsung,spi-src-clk = <0>; 1144 dmas = <&pdma1 9>, <&pdma1 8>; 1145 dma-names = "tx", "rx"; 1146 num-cs = <1>; 1147 #address-cells = <1>; 1148 #size-cells = <0>; 1149 fifo-depth = <64>; 1150 status = "disabled"; 1151 }; 1152 }; 1153 1154 usi_14: usi@10d200c0 { 1155 compatible = "samsung,exynosautov920-usi", 1156 "samsung,exynos850-usi"; 1157 reg = <0x10d200c0 0x20>; 1158 samsung,sysreg = <&syscon_peric1 0x1028>; 1159 samsung,mode = <USI_V2_UART>; 1160 #address-cells = <1>; 1161 #size-cells = <1>; 1162 ranges; 1163 clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, 1164 <&cmu_peric1 CLK_DOUT_PERIC1_USI14_USI>; 1165 clock-names = "pclk", "ipclk"; 1166 status = "disabled"; 1167 1168 serial_14: serial@10d20000 { 1169 compatible = "samsung,exynosautov920-uart", 1170 "samsung,exynos850-uart"; 1171 reg = <0x10d20000 0xc0>; 1172 interrupts = <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH>; 1173 pinctrl-names = "default"; 1174 pinctrl-0 = <&uart14_bus>; 1175 clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, 1176 <&cmu_peric1 CLK_DOUT_PERIC1_USI14_USI>; 1177 clock-names = "uart", "clk_uart_baud0"; 1178 samsung,uart-fifosize = <64>; 1179 status = "disabled"; 1180 }; 1181 1182 spi_14: spi@10d20000 { 1183 compatible = "samsung,exynosautov920-spi", 1184 "samsung,exynos850-spi"; 1185 reg = <0x10d20000 0x30>; 1186 interrupts = <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH>; 1187 pinctrl-names = "default"; 1188 pinctrl-0 = <&spi14_bus &spi14_cs_func>; 1189 clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, 1190 <&cmu_peric1 CLK_DOUT_PERIC1_USI14_USI>; 1191 clock-names = "spi", "spi_busclk0"; 1192 samsung,spi-src-clk = <0>; 1193 dmas = <&pdma1 11>, <&pdma1 10>; 1194 dma-names = "tx", "rx"; 1195 num-cs = <1>; 1196 #address-cells = <1>; 1197 #size-cells = <0>; 1198 fifo-depth = <64>; 1199 status = "disabled"; 1200 }; 1201 }; 1202 1203 usi_15: usi@10d400c0 { 1204 compatible = "samsung,exynosautov920-usi", 1205 "samsung,exynos850-usi"; 1206 reg = <0x10d400c0 0x20>; 1207 samsung,sysreg = <&syscon_peric1 0x1030>; 1208 samsung,mode = <USI_V2_UART>; 1209 #address-cells = <1>; 1210 #size-cells = <1>; 1211 ranges; 1212 clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, 1213 <&cmu_peric1 CLK_DOUT_PERIC1_USI15_USI>; 1214 clock-names = "pclk", "ipclk"; 1215 status = "disabled"; 1216 1217 serial_15: serial@10d40000 { 1218 compatible = "samsung,exynosautov920-uart", 1219 "samsung,exynos850-uart"; 1220 reg = <0x10d40000 0xc0>; 1221 interrupts = <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH>; 1222 pinctrl-names = "default"; 1223 pinctrl-0 = <&uart15_bus>; 1224 clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, 1225 <&cmu_peric1 CLK_DOUT_PERIC1_USI15_USI>; 1226 clock-names = "uart", "clk_uart_baud0"; 1227 samsung,uart-fifosize = <64>; 1228 status = "disabled"; 1229 }; 1230 1231 spi_15: spi@10d40000 { 1232 compatible = "samsung,exynosautov920-spi", 1233 "samsung,exynos850-spi"; 1234 reg = <0x10d40000 0x30>; 1235 interrupts = <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH>; 1236 pinctrl-names = "default"; 1237 pinctrl-0 = <&spi15_bus &spi15_cs_func>; 1238 clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, 1239 <&cmu_peric1 CLK_DOUT_PERIC1_USI15_USI>; 1240 clock-names = "spi", "spi_busclk0"; 1241 samsung,spi-src-clk = <0>; 1242 dmas = <&pdma1 13>, <&pdma1 12>; 1243 dma-names = "tx", "rx"; 1244 num-cs = <1>; 1245 #address-cells = <1>; 1246 #size-cells = <0>; 1247 fifo-depth = <64>; 1248 status = "disabled"; 1249 }; 1250 }; 1251 1252 usi_16: usi@10d600c0 { 1253 compatible = "samsung,exynosautov920-usi", 1254 "samsung,exynos850-usi"; 1255 reg = <0x10d600c0 0x20>; 1256 samsung,sysreg = <&syscon_peric1 0x1038>; 1257 samsung,mode = <USI_V2_UART>; 1258 #address-cells = <1>; 1259 #size-cells = <1>; 1260 ranges; 1261 clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, 1262 <&cmu_peric1 CLK_DOUT_PERIC1_USI16_USI>; 1263 clock-names = "pclk", "ipclk"; 1264 status = "disabled"; 1265 1266 serial_16: serial@10d60000 { 1267 compatible = "samsung,exynosautov920-uart", 1268 "samsung,exynos850-uart"; 1269 reg = <0x10d60000 0xc0>; 1270 interrupts = <GIC_SPI 801 IRQ_TYPE_LEVEL_HIGH>; 1271 pinctrl-names = "default"; 1272 pinctrl-0 = <&uart16_bus>; 1273 clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, 1274 <&cmu_peric1 CLK_DOUT_PERIC1_USI16_USI>; 1275 clock-names = "uart", "clk_uart_baud0"; 1276 samsung,uart-fifosize = <64>; 1277 status = "disabled"; 1278 }; 1279 1280 spi_16: spi@10d60000 { 1281 compatible = "samsung,exynosautov920-spi", 1282 "samsung,exynos850-spi"; 1283 reg = <0x10d60000 0x30>; 1284 interrupts = <GIC_SPI 801 IRQ_TYPE_LEVEL_HIGH>; 1285 pinctrl-names = "default"; 1286 pinctrl-0 = <&spi16_bus &spi16_cs_func>; 1287 clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, 1288 <&cmu_peric1 CLK_DOUT_PERIC1_USI16_USI>; 1289 clock-names = "spi", "spi_busclk0"; 1290 samsung,spi-src-clk = <0>; 1291 dmas = <&pdma1 15>, <&pdma1 14>; 1292 dma-names = "tx", "rx"; 1293 num-cs = <1>; 1294 #address-cells = <1>; 1295 #size-cells = <0>; 1296 fifo-depth = <64>; 1297 status = "disabled"; 1298 }; 1299 }; 1300 1301 usi_17: usi@10d800c0 { 1302 compatible = "samsung,exynosautov920-usi", 1303 "samsung,exynos850-usi"; 1304 reg = <0x10d800c0 0x20>; 1305 samsung,sysreg = <&syscon_peric1 0x1040>; 1306 samsung,mode = <USI_V2_UART>; 1307 #address-cells = <1>; 1308 #size-cells = <1>; 1309 ranges; 1310 clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, 1311 <&cmu_peric1 CLK_DOUT_PERIC1_USI17_USI>; 1312 clock-names = "pclk", "ipclk"; 1313 status = "disabled"; 1314 1315 serial_17: serial@10d80000 { 1316 compatible = "samsung,exynosautov920-uart", 1317 "samsung,exynos850-uart"; 1318 reg = <0x10d80000 0xc0>; 1319 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>; 1320 pinctrl-names = "default"; 1321 pinctrl-0 = <&uart17_bus>; 1322 clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, 1323 <&cmu_peric1 CLK_DOUT_PERIC1_USI17_USI>; 1324 clock-names = "uart", "clk_uart_baud0"; 1325 samsung,uart-fifosize = <64>; 1326 status = "disabled"; 1327 }; 1328 1329 spi_17: spi@10d80000 { 1330 compatible = "samsung,exynosautov920-spi", 1331 "samsung,exynos850-spi"; 1332 reg = <0x10d80000 0x30>; 1333 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>; 1334 pinctrl-names = "default"; 1335 pinctrl-0 = <&spi17_bus &spi17_cs_func>; 1336 clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, 1337 <&cmu_peric1 CLK_DOUT_PERIC1_USI17_USI>; 1338 clock-names = "spi", "spi_busclk0"; 1339 samsung,spi-src-clk = <0>; 1340 dmas = <&pdma1 17>, <&pdma1 16>; 1341 dma-names = "tx", "rx"; 1342 num-cs = <1>; 1343 #address-cells = <1>; 1344 #size-cells = <0>; 1345 fifo-depth = <64>; 1346 status = "disabled"; 1347 }; 1348 }; 1349 1350 cmu_top: clock-controller@11000000 { 1351 compatible = "samsung,exynosautov920-cmu-top"; 1352 reg = <0x11000000 0x8000>; 1353 #clock-cells = <1>; 1354 1355 clocks = <&xtcxo>; 1356 clock-names = "oscclk"; 1357 }; 1358 1359 pinctrl_alive: pinctrl@11850000 { 1360 compatible = "samsung,exynosautov920-pinctrl"; 1361 reg = <0x11850000 0x10000>; 1362 1363 wakeup-interrupt-controller { 1364 compatible = "samsung,exynosautov920-wakeup-eint"; 1365 }; 1366 }; 1367 1368 pmu_system_controller: system-controller@11860000 { 1369 compatible = "samsung,exynosautov920-pmu", 1370 "samsung,exynos7-pmu","syscon"; 1371 reg = <0x11860000 0x10000>; 1372 }; 1373 1374 cmu_hsi0: clock-controller@16000000 { 1375 compatible = "samsung,exynosautov920-cmu-hsi0"; 1376 reg = <0x16000000 0x8000>; 1377 #clock-cells = <1>; 1378 1379 clocks = <&xtcxo>, 1380 <&cmu_top DOUT_CLKCMU_HSI0_NOC>; 1381 clock-names = "oscclk", 1382 "noc"; 1383 }; 1384 1385 pinctrl_hsi0: pinctrl@16040000 { 1386 compatible = "samsung,exynosautov920-pinctrl"; 1387 reg = <0x16040000 0x10000>; 1388 interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>; 1389 }; 1390 1391 cmu_hsi1: clock-controller@16400000 { 1392 compatible = "samsung,exynosautov920-cmu-hsi1"; 1393 reg = <0x16400000 0x8000>; 1394 #clock-cells = <1>; 1395 1396 clocks = <&xtcxo>, 1397 <&cmu_top DOUT_CLKCMU_HSI1_NOC>, 1398 <&cmu_top DOUT_CLKCMU_HSI1_USBDRD>, 1399 <&cmu_top DOUT_CLKCMU_HSI1_MMC_CARD>; 1400 clock-names = "oscclk", 1401 "noc", 1402 "usbdrd", 1403 "mmc_card"; 1404 }; 1405 1406 pinctrl_hsi1: pinctrl@16450000 { 1407 compatible = "samsung,exynosautov920-pinctrl"; 1408 reg = <0x16450000 0x10000>; 1409 interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>; 1410 }; 1411 1412 cmu_hsi2: clock-controller@16b00000 { 1413 compatible = "samsung,exynosautov920-cmu-hsi2"; 1414 reg = <0x16b00000 0x8000>; 1415 #clock-cells = <1>; 1416 1417 clocks = <&xtcxo>, 1418 <&cmu_top DOUT_CLKCMU_HSI2_NOC>, 1419 <&cmu_top DOUT_CLKCMU_HSI2_NOC_UFS>, 1420 <&cmu_top DOUT_CLKCMU_HSI2_UFS_EMBD>, 1421 <&cmu_top DOUT_CLKCMU_HSI2_ETHERNET>; 1422 clock-names = "oscclk", 1423 "noc", 1424 "ufs", 1425 "embd", 1426 "ethernet"; 1427 }; 1428 1429 pinctrl_hsi2: pinctrl@16c10000 { 1430 compatible = "samsung,exynosautov920-pinctrl"; 1431 reg = <0x16c10000 0x10000>; 1432 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1433 }; 1434 1435 pinctrl_hsi2ufs: pinctrl@16d20000 { 1436 compatible = "samsung,exynosautov920-pinctrl"; 1437 reg = <0x16d20000 0x10000>; 1438 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1439 }; 1440 1441 ufs_0_phy: phy@16e04000 { 1442 compatible = "samsung,exynosautov920-ufs-phy"; 1443 reg = <0x16e04000 0x4000>; 1444 reg-names = "phy-pma"; 1445 clocks = <&xtcxo>; 1446 clock-names = "ref_clk"; 1447 samsung,pmu-syscon = <&pmu_system_controller>; 1448 #phy-cells = <0>; 1449 status = "disabled"; 1450 }; 1451 1452 cmu_mfc: clock-controller@19c00000 { 1453 compatible = "samsung,exynosautov920-cmu-mfc"; 1454 reg = <0x19c00000 0x8000>; 1455 #clock-cells = <1>; 1456 1457 clocks = <&xtcxo>, 1458 <&cmu_top DOUT_CLKCMU_MFC_MFC>, 1459 <&cmu_top DOUT_CLKCMU_MFC_WFD>; 1460 clock-names = "oscclk", 1461 "mfc", 1462 "wfd"; 1463 }; 1464 1465 pinctrl_aud: pinctrl@1a460000 { 1466 compatible = "samsung,exynosautov920-pinctrl"; 1467 reg = <0x1a460000 0x10000>; 1468 }; 1469 1470 cmu_m2m: clock-controller@1a800000 { 1471 compatible = "samsung,exynosautov920-cmu-m2m"; 1472 reg = <0x1a800000 0x8000>; 1473 #clock-cells = <1>; 1474 1475 clocks = <&xtcxo>, 1476 <&cmu_top DOUT_CLKCMU_M2M_NOC>, 1477 <&cmu_top DOUT_CLKCMU_M2M_JPEG>; 1478 clock-names = "oscclk", 1479 "noc", 1480 "jpeg"; 1481 }; 1482 1483 cmu_cpucl0: clock-controller@1ec00000 { 1484 compatible = "samsung,exynosautov920-cmu-cpucl0"; 1485 reg = <0x1ec00000 0x8000>; 1486 #clock-cells = <1>; 1487 1488 clocks = <&xtcxo>, 1489 <&cmu_top DOUT_CLKCMU_CPUCL0_SWITCH>, 1490 <&cmu_top DOUT_CLKCMU_CPUCL0_CLUSTER>, 1491 <&cmu_top DOUT_CLKCMU_CPUCL0_DBG>; 1492 clock-names = "oscclk", 1493 "switch", 1494 "cluster", 1495 "dbg"; 1496 }; 1497 1498 cmu_cpucl1: clock-controller@1ed00000 { 1499 compatible = "samsung,exynosautov920-cmu-cpucl1"; 1500 reg = <0x1ed00000 0x8000>; 1501 #clock-cells = <1>; 1502 1503 clocks = <&xtcxo>, 1504 <&cmu_top DOUT_CLKCMU_CPUCL1_SWITCH>, 1505 <&cmu_top DOUT_CLKCMU_CPUCL1_CLUSTER>; 1506 clock-names = "oscclk", 1507 "switch", 1508 "cluster"; 1509 }; 1510 1511 cmu_cpucl2: clock-controller@1ee00000 { 1512 compatible = "samsung,exynosautov920-cmu-cpucl2"; 1513 reg = <0x1ee00000 0x8000>; 1514 #clock-cells = <1>; 1515 1516 clocks = <&xtcxo>, 1517 <&cmu_top DOUT_CLKCMU_CPUCL2_SWITCH>, 1518 <&cmu_top DOUT_CLKCMU_CPUCL2_CLUSTER>; 1519 clock-names = "oscclk", 1520 "switch", 1521 "cluster"; 1522 }; 1523 }; 1524 1525 timer { 1526 compatible = "arm,armv8-timer"; 1527 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 1528 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 1529 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 1530 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 1531 <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 1532 }; 1533}; 1534 1535#include "exynosautov920-pinctrl.dtsi"
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