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exynosautov9.dtsi
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linux-6.19.14/arch/arm64/boot/dts/exynos/exynosautov9.dtsi
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Samsung's ExynosAuto v9 SoC device tree source 4 * 5 * Copyright (c) 2021 Samsung Electronics Co., Ltd. 6 * 7 */ 8 9#include <dt-bindings/clock/samsung,exynosautov9.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/soc/samsung,boot-mode.h> 12#include <dt-bindings/soc/samsung,exynos-usi.h> 13 14/ { 15 compatible = "samsung,exynosautov9"; 16 #address-cells = <2>; 17 #size-cells = <1>; 18 19 interrupt-parent = <&gic>; 20 21 aliases { 22 pinctrl0 = &pinctrl_alive; 23 pinctrl1 = &pinctrl_aud; 24 pinctrl2 = &pinctrl_fsys0; 25 pinctrl3 = &pinctrl_fsys1; 26 pinctrl4 = &pinctrl_fsys2; 27 pinctrl5 = &pinctrl_peric0; 28 pinctrl6 = &pinctrl_peric1; 29 }; 30 31 arm-pmu { 32 compatible = "arm,cortex-a76-pmu"; 33 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 34 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 35 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 36 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 37 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 38 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 41 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, 42 <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; 43 }; 44 45 cpus { 46 #address-cells = <1>; 47 #size-cells = <0>; 48 49 cpu-map { 50 cluster0 { 51 core0 { 52 cpu = <&cpu0>; 53 }; 54 core1 { 55 cpu = <&cpu1>; 56 }; 57 core2 { 58 cpu = <&cpu2>; 59 }; 60 core3 { 61 cpu = <&cpu3>; 62 }; 63 }; 64 65 cluster1 { 66 core0 { 67 cpu = <&cpu4>; 68 }; 69 core1 { 70 cpu = <&cpu5>; 71 }; 72 core2 { 73 cpu = <&cpu6>; 74 }; 75 core3 { 76 cpu = <&cpu7>; 77 }; 78 }; 79 }; 80 81 cpu0: cpu@0 { 82 device_type = "cpu"; 83 compatible = "arm,cortex-a76"; 84 reg = <0x0>; 85 enable-method = "psci"; 86 }; 87 88 cpu1: cpu@100 { 89 device_type = "cpu"; 90 compatible = "arm,cortex-a76"; 91 reg = <0x100>; 92 enable-method = "psci"; 93 }; 94 95 cpu2: cpu@200 { 96 device_type = "cpu"; 97 compatible = "arm,cortex-a76"; 98 reg = <0x200>; 99 enable-method = "psci"; 100 }; 101 102 cpu3: cpu@300 { 103 device_type = "cpu"; 104 compatible = "arm,cortex-a76"; 105 reg = <0x300>; 106 enable-method = "psci"; 107 }; 108 109 cpu4: cpu@10000 { 110 device_type = "cpu"; 111 compatible = "arm,cortex-a76"; 112 reg = <0x10000>; 113 enable-method = "psci"; 114 }; 115 116 cpu5: cpu@10100 { 117 device_type = "cpu"; 118 compatible = "arm,cortex-a76"; 119 reg = <0x10100>; 120 enable-method = "psci"; 121 }; 122 123 cpu6: cpu@10200 { 124 device_type = "cpu"; 125 compatible = "arm,cortex-a76"; 126 reg = <0x10200>; 127 enable-method = "psci"; 128 }; 129 130 cpu7: cpu@10300 { 131 device_type = "cpu"; 132 compatible = "arm,cortex-a76"; 133 reg = <0x10300>; 134 enable-method = "psci"; 135 }; 136 }; 137 138 psci { 139 compatible = "arm,psci-1.0"; 140 method = "smc"; 141 cpu_suspend = <0xc4000001>; 142 cpu_off = <0x84000002>; 143 cpu_on = <0xc4000003>; 144 }; 145 146 timer { 147 compatible = "arm,armv8-timer"; 148 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 149 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 150 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 151 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 152 }; 153 154 fixed-rate-clocks { 155 xtcxo: clock { 156 compatible = "fixed-clock"; 157 #clock-cells = <0>; 158 clock-output-names = "oscclk"; 159 }; 160 }; 161 162 soc: soc@0 { 163 compatible = "simple-bus"; 164 #address-cells = <1>; 165 #size-cells = <1>; 166 ranges = <0x0 0x0 0x0 0x20000000>; 167 168 chipid@10000000 { 169 compatible = "samsung,exynosautov9-chipid", 170 "samsung,exynos850-chipid"; 171 reg = <0x10000000 0x24>; 172 }; 173 174 cmu_peris: clock-controller@10020000 { 175 compatible = "samsung,exynosautov9-cmu-peris"; 176 reg = <0x10020000 0x8000>; 177 #clock-cells = <1>; 178 179 clocks = <&xtcxo>, 180 <&cmu_top DOUT_CLKCMU_PERIS_BUS>; 181 clock-names = "oscclk", 182 "dout_clkcmu_peris_bus"; 183 }; 184 185 cmu_peric0: clock-controller@10200000 { 186 compatible = "samsung,exynosautov9-cmu-peric0"; 187 reg = <0x10200000 0x8000>; 188 #clock-cells = <1>; 189 190 clocks = <&xtcxo>, 191 <&cmu_top DOUT_CLKCMU_PERIC0_BUS>, 192 <&cmu_top DOUT_CLKCMU_PERIC0_IP>; 193 clock-names = "oscclk", 194 "dout_clkcmu_peric0_bus", 195 "dout_clkcmu_peric0_ip"; 196 }; 197 198 cmu_peric1: clock-controller@10800000 { 199 compatible = "samsung,exynosautov9-cmu-peric1"; 200 reg = <0x10800000 0x8000>; 201 #clock-cells = <1>; 202 203 clocks = <&xtcxo>, 204 <&cmu_top DOUT_CLKCMU_PERIC1_BUS>, 205 <&cmu_top DOUT_CLKCMU_PERIC1_IP>; 206 clock-names = "oscclk", 207 "dout_clkcmu_peric1_bus", 208 "dout_clkcmu_peric1_ip"; 209 }; 210 211 cmu_fsys1: clock-controller@17040000 { 212 compatible = "samsung,exynosautov9-cmu-fsys1"; 213 reg = <0x17040000 0x8000>; 214 #clock-cells = <1>; 215 216 clocks = <&xtcxo>, 217 <&cmu_top DOUT_CLKCMU_FSYS1_BUS>, 218 <&cmu_top GOUT_CLKCMU_FSYS1_MMC_CARD>, 219 <&cmu_top DOUT_CLKCMU_FSYS1_USBDRD>; 220 clock-names = "oscclk", 221 "dout_clkcmu_fsys1_bus", 222 "gout_clkcmu_fsys1_mmc_card", 223 "dout_clkcmu_fsys1_usbdrd"; 224 }; 225 226 cmu_fsys0: clock-controller@17700000 { 227 compatible = "samsung,exynosautov9-cmu-fsys0"; 228 reg = <0x17700000 0x8000>; 229 #clock-cells = <1>; 230 231 clocks = <&xtcxo>, 232 <&cmu_top DOUT_CLKCMU_FSYS0_BUS>, 233 <&cmu_top DOUT_CLKCMU_FSYS0_PCIE>; 234 clock-names = "oscclk", 235 "dout_clkcmu_fsys0_bus", 236 "dout_clkcmu_fsys0_pcie"; 237 }; 238 239 cmu_fsys2: clock-controller@17c00000 { 240 compatible = "samsung,exynosautov9-cmu-fsys2"; 241 reg = <0x17c00000 0x8000>; 242 #clock-cells = <1>; 243 244 clocks = <&xtcxo>, 245 <&cmu_top DOUT_CLKCMU_FSYS2_BUS>, 246 <&cmu_top DOUT_CLKCMU_FSYS2_UFS_EMBD>, 247 <&cmu_top DOUT_CLKCMU_FSYS2_ETHERNET>; 248 clock-names = "oscclk", 249 "dout_clkcmu_fsys2_bus", 250 "dout_fsys2_clkcmu_ufs_embd", 251 "dout_fsys2_clkcmu_ethernet"; 252 }; 253 254 cmu_dpum: clock-controller@18c00000 { 255 compatible = "samsung,exynosautov9-cmu-dpum"; 256 reg = <0x18c00000 0x8000>; 257 #clock-cells = <1>; 258 259 clocks = <&xtcxo>, 260 <&cmu_top DOUT_CLKCMU_DPUM_BUS>; 261 clock-names = "oscclk", "bus"; 262 }; 263 264 sysmmu_dpum_0: sysmmu@18c80000 { 265 compatible = "samsung,exynos-sysmmu"; 266 reg = <0x18c80000 0x10000>; 267 interrupts = <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>; 268 clocks = <&cmu_dpum CLK_GOUT_DPUM_SYSMMU_D0_CLK>; 269 clock-names = "sysmmu"; 270 #iommu-cells = <0>; 271 }; 272 273 sysmmu_dpum_1: sysmmu@18c90000 { 274 compatible = "samsung,exynos-sysmmu"; 275 reg = <0x18c90000 0x10000>; 276 interrupts = <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>; 277 clocks = <&cmu_dpum CLK_GOUT_DPUM_SYSMMU_D1_CLK>; 278 clock-names = "sysmmu"; 279 #iommu-cells = <0>; 280 }; 281 282 sysmmu_dpum_2: sysmmu@18ca0000 { 283 compatible = "samsung,exynos-sysmmu"; 284 reg = <0x18ca0000 0x10000>; 285 interrupts = <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>; 286 clocks = <&cmu_dpum CLK_GOUT_DPUM_SYSMMU_D2_CLK>; 287 clock-names = "sysmmu"; 288 #iommu-cells = <0>; 289 }; 290 291 sysmmu_dpum_3: sysmmu@18cb0000 { 292 compatible = "samsung,exynos-sysmmu"; 293 reg = <0x18cb0000 0x10000>; 294 interrupts = <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>; 295 clocks = <&cmu_dpum CLK_GOUT_DPUM_SYSMMU_D3_CLK>; 296 clock-names = "sysmmu"; 297 #iommu-cells = <0>; 298 }; 299 300 cmu_core: clock-controller@1b030000 { 301 compatible = "samsung,exynosautov9-cmu-core"; 302 reg = <0x1b030000 0x8000>; 303 #clock-cells = <1>; 304 305 clocks = <&xtcxo>, 306 <&cmu_top DOUT_CLKCMU_CORE_BUS>; 307 clock-names = "oscclk", 308 "dout_clkcmu_core_bus"; 309 }; 310 311 cmu_busmc: clock-controller@1b200000 { 312 compatible = "samsung,exynosautov9-cmu-busmc"; 313 reg = <0x1b200000 0x8000>; 314 #clock-cells = <1>; 315 316 clocks = <&xtcxo>, 317 <&cmu_top DOUT_CLKCMU_BUSMC_BUS>; 318 clock-names = "oscclk", 319 "dout_clkcmu_busmc_bus"; 320 }; 321 322 cmu_top: clock-controller@1b240000 { 323 compatible = "samsung,exynosautov9-cmu-top"; 324 reg = <0x1b240000 0x8000>; 325 #clock-cells = <1>; 326 327 clocks = <&xtcxo>; 328 clock-names = "oscclk"; 329 }; 330 331 gic: interrupt-controller@10101000 { 332 compatible = "arm,gic-400"; 333 #interrupt-cells = <3>; 334 #address-cells = <0>; 335 interrupt-controller; 336 reg = <0x10101000 0x1000>, 337 <0x10102000 0x2000>, 338 <0x10104000 0x2000>, 339 <0x10106000 0x2000>; 340 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | 341 IRQ_TYPE_LEVEL_HIGH)>; 342 }; 343 344 pdma0: dma-controller@1b2e0000 { 345 compatible = "arm,pl330", "arm,primecell"; 346 reg = <0x1b2e0000 0x1000>; 347 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 348 clocks = <&cmu_busmc CLK_GOUT_BUSMC_PDMA0_PCLK>; 349 clock-names = "apb_pclk"; 350 arm,pl330-broken-no-flushp; 351 #dma-cells = <1>; 352 }; 353 354 pinctrl_alive: pinctrl@10450000 { 355 compatible = "samsung,exynosautov9-pinctrl"; 356 reg = <0x10450000 0x1000>; 357 358 wakeup-interrupt-controller { 359 compatible = "samsung,exynosautov9-wakeup-eint", 360 "samsung,exynos850-wakeup-eint", 361 "samsung,exynos7-wakeup-eint"; 362 }; 363 }; 364 365 pinctrl_aud: pinctrl@19c60000 { 366 compatible = "samsung,exynosautov9-pinctrl"; 367 reg = <0x19c60000 0x1000>; 368 }; 369 370 pinctrl_fsys0: pinctrl@17740000 { 371 compatible = "samsung,exynosautov9-pinctrl"; 372 reg = <0x17740000 0x1000>; 373 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 374 }; 375 376 pinctrl_fsys1: pinctrl@17060000 { 377 compatible = "samsung,exynosautov9-pinctrl"; 378 reg = <0x17060000 0x1000>; 379 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 380 }; 381 382 pinctrl_fsys2: pinctrl@17c30000 { 383 compatible = "samsung,exynosautov9-pinctrl"; 384 reg = <0x17c30000 0x1000>; 385 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>; 386 }; 387 388 pinctrl_peric0: pinctrl@10230000 { 389 compatible = "samsung,exynosautov9-pinctrl"; 390 reg = <0x10230000 0x1000>; 391 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>; 392 }; 393 394 pinctrl_peric1: pinctrl@10830000 { 395 compatible = "samsung,exynosautov9-pinctrl"; 396 reg = <0x10830000 0x1000>; 397 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 398 }; 399 400 pmu_system_controller: system-controller@10460000 { 401 compatible = "samsung,exynosautov9-pmu", 402 "samsung,exynos7-pmu", "syscon"; 403 reg = <0x10460000 0x10000>; 404 405 reboot: syscon-reboot { 406 compatible = "syscon-reboot"; 407 regmap = <&pmu_system_controller>; 408 offset = <0x3a00>; /* SYSTEM_CONFIGURATION */ 409 value = <0x2>; 410 mask = <0x2>; 411 }; 412 413 reboot-mode { 414 compatible = "syscon-reboot-mode"; 415 offset = <0x810>; /* SYSIP_DAT0 */ 416 mode-bootloader = <EXYNOSAUTOV9_BOOT_BOOTLOADER>; 417 mode-fastboot = <EXYNOSAUTOV9_BOOT_FASTBOOT>; 418 mode-recovery = <EXYNOSAUTOV9_BOOT_RECOVERY>; 419 }; 420 }; 421 422 syscon_fsys2: syscon@17c20000 { 423 compatible = "samsung,exynosautov9-fsys2-sysreg", 424 "samsung,exynosautov9-sysreg", "syscon"; 425 reg = <0x17c20000 0x1000>; 426 }; 427 428 syscon_peric0: syscon@10220000 { 429 compatible = "samsung,exynosautov9-peric0-sysreg", 430 "samsung,exynosautov9-sysreg", "syscon"; 431 reg = <0x10220000 0x2000>; 432 }; 433 434 syscon_peric1: syscon@10820000 { 435 compatible = "samsung,exynosautov9-peric1-sysreg", 436 "samsung,exynosautov9-sysreg", "syscon"; 437 reg = <0x10820000 0x2000>; 438 }; 439 440 usi_0: usi@103000c0 { 441 compatible = "samsung,exynosautov9-usi", 442 "samsung,exynos850-usi"; 443 reg = <0x103000c0 0x20>; 444 samsung,sysreg = <&syscon_peric0 0x1000>; 445 samsung,mode = <USI_MODE_UART>; 446 #address-cells = <1>; 447 #size-cells = <1>; 448 ranges; 449 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_0>, 450 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_0>; 451 clock-names = "pclk", "ipclk"; 452 status = "disabled"; 453 454 serial_0: serial@10300000 { 455 compatible = "samsung,exynosautov9-uart", 456 "samsung,exynos850-uart"; 457 reg = <0x10300000 0xc0>; 458 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; 459 pinctrl-names = "default"; 460 pinctrl-0 = <&uart0_bus>; 461 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_0>, 462 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_0>; 463 clock-names = "uart", "clk_uart_baud0"; 464 samsung,uart-fifosize = <256>; 465 status = "disabled"; 466 }; 467 468 spi_0: spi@10300000 { 469 compatible = "samsung,exynosautov9-spi"; 470 reg = <0x10300000 0x30>; 471 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; 472 pinctrl-names = "default"; 473 pinctrl-0 = <&spi0_bus &spi0_cs_func>; 474 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_0>, 475 <&cmu_peric0 CLK_DOUT_PERIC0_USI00_USI>, 476 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_0>; 477 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 478 samsung,spi-src-clk = <0>; 479 dmas = <&pdma0 1>, <&pdma0 0>; 480 dma-names = "tx", "rx"; 481 num-cs = <1>; 482 #address-cells = <1>; 483 #size-cells = <0>; 484 fifo-depth = <256>; 485 status = "disabled"; 486 }; 487 488 hsi2c_0: i2c@10300000 { 489 compatible = "samsung,exynosautov9-hsi2c"; 490 reg = <0x10300000 0xc0>; 491 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; 492 pinctrl-names = "default"; 493 pinctrl-0 = <&hsi2c0_bus>; 494 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_0>, 495 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_0>; 496 clock-names = "hsi2c", "hsi2c_pclk"; 497 #address-cells = <1>; 498 #size-cells = <0>; 499 status = "disabled"; 500 }; 501 }; 502 503 usi_i2c_0: usi@103100c0 { 504 compatible = "samsung,exynosautov9-usi", 505 "samsung,exynos850-usi"; 506 reg = <0x103100c0 0x20>; 507 samsung,sysreg = <&syscon_peric0 0x1004>; 508 samsung,mode = <USI_MODE_I2C>; 509 #address-cells = <1>; 510 #size-cells = <1>; 511 ranges; 512 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_1>, 513 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_1>; 514 clock-names = "pclk", "ipclk"; 515 status = "disabled"; 516 517 hsi2c_1: i2c@10310000 { 518 compatible = "samsung,exynosautov9-hsi2c"; 519 reg = <0x10310000 0xc0>; 520 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 521 pinctrl-names = "default"; 522 pinctrl-0 = <&hsi2c1_bus>; 523 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_1>, 524 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_1>; 525 clock-names = "hsi2c", "hsi2c_pclk"; 526 #address-cells = <1>; 527 #size-cells = <0>; 528 status = "disabled"; 529 }; 530 }; 531 532 usi_1: usi@103200c0 { 533 compatible = "samsung,exynosautov9-usi", 534 "samsung,exynos850-usi"; 535 reg = <0x103200c0 0x20>; 536 samsung,sysreg = <&syscon_peric0 0x1008>; 537 samsung,mode = <USI_MODE_UART>; 538 #address-cells = <1>; 539 #size-cells = <1>; 540 ranges; 541 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_2>, 542 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_2>; 543 clock-names = "pclk", "ipclk"; 544 status = "disabled"; 545 546 serial_1: serial@10320000 { 547 compatible = "samsung,exynosautov9-uart", 548 "samsung,exynos850-uart"; 549 reg = <0x10320000 0xc0>; 550 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>; 551 pinctrl-names = "default"; 552 pinctrl-0 = <&uart1_bus>; 553 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_2>, 554 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_2>; 555 clock-names = "uart", "clk_uart_baud0"; 556 samsung,uart-fifosize = <256>; 557 status = "disabled"; 558 }; 559 560 spi_1: spi@10320000 { 561 compatible = "samsung,exynosautov9-spi"; 562 reg = <0x10320000 0x30>; 563 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>; 564 pinctrl-names = "default"; 565 pinctrl-0 = <&spi1_bus &spi1_cs_func>; 566 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_2>, 567 <&cmu_peric0 CLK_DOUT_PERIC0_USI01_USI>, 568 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_2>; 569 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 570 samsung,spi-src-clk = <0>; 571 dmas = <&pdma0 3>, <&pdma0 2>; 572 dma-names = "tx", "rx"; 573 num-cs = <1>; 574 #address-cells = <1>; 575 #size-cells = <0>; 576 fifo-depth = <256>; 577 status = "disabled"; 578 }; 579 580 hsi2c_2: i2c@10320000 { 581 compatible = "samsung,exynosautov9-hsi2c"; 582 reg = <0x10320000 0xc0>; 583 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>; 584 pinctrl-names = "default"; 585 pinctrl-0 = <&hsi2c2_bus>; 586 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_2>, 587 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_2>; 588 clock-names = "hsi2c", "hsi2c_pclk"; 589 #address-cells = <1>; 590 #size-cells = <0>; 591 status = "disabled"; 592 }; 593 }; 594 595 usi_i2c_1: usi@103300c0 { 596 compatible = "samsung,exynosautov9-usi", 597 "samsung,exynos850-usi"; 598 reg = <0x103300c0 0x20>; 599 samsung,sysreg = <&syscon_peric0 0x100c>; 600 samsung,mode = <USI_MODE_I2C>; 601 #address-cells = <1>; 602 #size-cells = <1>; 603 ranges; 604 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_3>, 605 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_3>; 606 clock-names = "pclk", "ipclk"; 607 status = "disabled"; 608 609 hsi2c_3: i2c@10330000 { 610 compatible = "samsung,exynosautov9-hsi2c"; 611 reg = <0x10330000 0xc0>; 612 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>; 613 pinctrl-names = "default"; 614 pinctrl-0 = <&hsi2c3_bus>; 615 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_3>, 616 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_3>; 617 clock-names = "hsi2c", "hsi2c_pclk"; 618 #address-cells = <1>; 619 #size-cells = <0>; 620 status = "disabled"; 621 }; 622 }; 623 624 usi_2: usi@103400c0 { 625 compatible = "samsung,exynosautov9-usi", 626 "samsung,exynos850-usi"; 627 reg = <0x103400c0 0x20>; 628 samsung,sysreg = <&syscon_peric0 0x1010>; 629 samsung,mode = <USI_MODE_UART>; 630 #address-cells = <1>; 631 #size-cells = <1>; 632 ranges; 633 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_4>, 634 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_4>; 635 clock-names = "pclk", "ipclk"; 636 status = "disabled"; 637 638 serial_2: serial@10340000 { 639 compatible = "samsung,exynosautov9-uart", 640 "samsung,exynos850-uart"; 641 reg = <0x10340000 0xc0>; 642 interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>; 643 pinctrl-names = "default"; 644 pinctrl-0 = <&uart2_bus>; 645 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_4>, 646 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_4>; 647 clock-names = "uart", "clk_uart_baud0"; 648 samsung,uart-fifosize = <64>; 649 status = "disabled"; 650 }; 651 652 spi_2: spi@10340000 { 653 compatible = "samsung,exynosautov9-spi"; 654 reg = <0x10340000 0x30>; 655 interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>; 656 pinctrl-names = "default"; 657 pinctrl-0 = <&spi2_bus &spi2_cs_func>; 658 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_4>, 659 <&cmu_peric0 CLK_DOUT_PERIC0_USI02_USI>, 660 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_4>; 661 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 662 samsung,spi-src-clk = <0>; 663 dmas = <&pdma0 5>, <&pdma0 4>; 664 dma-names = "tx", "rx"; 665 num-cs = <1>; 666 #address-cells = <1>; 667 #size-cells = <0>; 668 fifo-depth = <64>; 669 status = "disabled"; 670 }; 671 672 hsi2c_4: i2c@10340000 { 673 compatible = "samsung,exynosautov9-hsi2c"; 674 reg = <0x10340000 0xc0>; 675 interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>; 676 pinctrl-names = "default"; 677 pinctrl-0 = <&hsi2c4_bus>; 678 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_4>, 679 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_4>; 680 clock-names = "hsi2c", "hsi2c_pclk"; 681 #address-cells = <1>; 682 #size-cells = <0>; 683 status = "disabled"; 684 }; 685 }; 686 687 usi_i2c_2: usi@103500c0 { 688 compatible = "samsung,exynosautov9-usi", 689 "samsung,exynos850-usi"; 690 reg = <0x103500c0 0x20>; 691 samsung,sysreg = <&syscon_peric0 0x1014>; 692 samsung,mode = <USI_MODE_I2C>; 693 #address-cells = <1>; 694 #size-cells = <1>; 695 ranges; 696 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_5>, 697 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_5>; 698 clock-names = "pclk", "ipclk"; 699 status = "disabled"; 700 701 hsi2c_5: i2c@10350000 { 702 compatible = "samsung,exynosautov9-hsi2c"; 703 reg = <0x10350000 0xc0>; 704 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>; 705 pinctrl-names = "default"; 706 pinctrl-0 = <&hsi2c5_bus>; 707 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_5>, 708 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_5>; 709 clock-names = "hsi2c", "hsi2c_pclk"; 710 #address-cells = <1>; 711 #size-cells = <0>; 712 status = "disabled"; 713 }; 714 }; 715 716 usi_3: usi@103600c0 { 717 compatible = "samsung,exynosautov9-usi", 718 "samsung,exynos850-usi"; 719 reg = <0x103600c0 0x20>; 720 samsung,sysreg = <&syscon_peric0 0x1018>; 721 samsung,mode = <USI_MODE_UART>; 722 #address-cells = <1>; 723 #size-cells = <1>; 724 ranges; 725 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_6>, 726 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_6>; 727 clock-names = "pclk", "ipclk"; 728 status = "disabled"; 729 730 serial_3: serial@10360000 { 731 compatible = "samsung,exynosautov9-uart", 732 "samsung,exynos850-uart"; 733 reg = <0x10360000 0xc0>; 734 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>; 735 pinctrl-names = "default"; 736 pinctrl-0 = <&uart3_bus>; 737 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_6>, 738 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_6>; 739 clock-names = "uart", "clk_uart_baud0"; 740 samsung,uart-fifosize = <64>; 741 status = "disabled"; 742 }; 743 744 spi_3: spi@10360000 { 745 compatible = "samsung,exynosautov9-spi"; 746 reg = <0x10360000 0x30>; 747 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>; 748 pinctrl-names = "default"; 749 pinctrl-0 = <&spi3_bus &spi3_cs_func>; 750 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_6>, 751 <&cmu_peric0 CLK_DOUT_PERIC0_USI03_USI>, 752 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_6>; 753 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 754 samsung,spi-src-clk = <0>; 755 dmas = <&pdma0 7>, <&pdma0 6>; 756 dma-names = "tx", "rx"; 757 num-cs = <1>; 758 #address-cells = <1>; 759 #size-cells = <0>; 760 fifo-depth = <64>; 761 status = "disabled"; 762 }; 763 764 hsi2c_6: i2c@10360000 { 765 compatible = "samsung,exynosautov9-hsi2c"; 766 reg = <0x10360000 0xc0>; 767 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>; 768 pinctrl-names = "default"; 769 pinctrl-0 = <&hsi2c6_bus>; 770 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_6>, 771 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_6>; 772 clock-names = "hsi2c", "hsi2c_pclk"; 773 #address-cells = <1>; 774 #size-cells = <0>; 775 status = "disabled"; 776 }; 777 }; 778 779 usi_i2c_3: usi@103700c0 { 780 compatible = "samsung,exynosautov9-usi", 781 "samsung,exynos850-usi"; 782 reg = <0x103700c0 0x20>; 783 samsung,sysreg = <&syscon_peric0 0x101c>; 784 samsung,mode = <USI_MODE_I2C>; 785 #address-cells = <1>; 786 #size-cells = <1>; 787 ranges; 788 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_7>, 789 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_7>; 790 clock-names = "pclk", "ipclk"; 791 status = "disabled"; 792 793 hsi2c_7: i2c@10370000 { 794 compatible = "samsung,exynosautov9-hsi2c"; 795 reg = <0x10370000 0xc0>; 796 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>; 797 pinctrl-names = "default"; 798 pinctrl-0 = <&hsi2c7_bus>; 799 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_7>, 800 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_7>; 801 clock-names = "hsi2c", "hsi2c_pclk"; 802 #address-cells = <1>; 803 #size-cells = <0>; 804 status = "disabled"; 805 }; 806 }; 807 808 usi_4: usi@103800c0 { 809 compatible = "samsung,exynosautov9-usi", 810 "samsung,exynos850-usi"; 811 reg = <0x103800c0 0x20>; 812 samsung,sysreg = <&syscon_peric0 0x1020>; 813 samsung,mode = <USI_MODE_UART>; 814 #address-cells = <1>; 815 #size-cells = <1>; 816 ranges; 817 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_8>, 818 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_8>; 819 clock-names = "pclk", "ipclk"; 820 status = "disabled"; 821 822 serial_4: serial@10380000 { 823 compatible = "samsung,exynosautov9-uart", 824 "samsung,exynos850-uart"; 825 reg = <0x10380000 0xc0>; 826 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 827 pinctrl-names = "default"; 828 pinctrl-0 = <&uart4_bus>; 829 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_8>, 830 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_8>; 831 clock-names = "uart", "clk_uart_baud0"; 832 samsung,uart-fifosize = <64>; 833 status = "disabled"; 834 }; 835 836 spi_4: spi@10380000 { 837 compatible = "samsung,exynosautov9-spi"; 838 reg = <0x10380000 0x30>; 839 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 840 pinctrl-names = "default"; 841 pinctrl-0 = <&spi4_bus &spi4_cs_func>; 842 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_8>, 843 <&cmu_peric0 CLK_DOUT_PERIC0_USI04_USI>, 844 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_8>; 845 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 846 samsung,spi-src-clk = <0>; 847 dmas = <&pdma0 9>, <&pdma0 8>; 848 dma-names = "tx", "rx"; 849 num-cs = <1>; 850 #address-cells = <1>; 851 #size-cells = <0>; 852 fifo-depth = <64>; 853 status = "disabled"; 854 }; 855 856 hsi2c_8: i2c@10380000 { 857 compatible = "samsung,exynosautov9-hsi2c"; 858 reg = <0x10380000 0xc0>; 859 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 860 pinctrl-names = "default"; 861 pinctrl-0 = <&hsi2c8_bus>; 862 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_8>, 863 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_8>; 864 clock-names = "hsi2c", "hsi2c_pclk"; 865 #address-cells = <1>; 866 #size-cells = <0>; 867 status = "disabled"; 868 }; 869 }; 870 871 usi_i2c_4: usi@103900c0 { 872 compatible = "samsung,exynosautov9-usi", 873 "samsung,exynos850-usi"; 874 reg = <0x103900c0 0x20>; 875 samsung,sysreg = <&syscon_peric0 0x1024>; 876 samsung,mode = <USI_MODE_I2C>; 877 #address-cells = <1>; 878 #size-cells = <1>; 879 ranges; 880 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_9>, 881 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_9>; 882 clock-names = "pclk", "ipclk"; 883 status = "disabled"; 884 885 hsi2c_9: i2c@10390000 { 886 compatible = "samsung,exynosautov9-hsi2c"; 887 reg = <0x10390000 0xc0>; 888 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 889 pinctrl-names = "default"; 890 pinctrl-0 = <&hsi2c9_bus>; 891 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_9>, 892 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_9>; 893 clock-names = "hsi2c", "hsi2c_pclk"; 894 #address-cells = <1>; 895 #size-cells = <0>; 896 status = "disabled"; 897 }; 898 }; 899 900 usi_5: usi@103a00c0 { 901 compatible = "samsung,exynosautov9-usi", 902 "samsung,exynos850-usi"; 903 reg = <0x103a00c0 0x20>; 904 samsung,sysreg = <&syscon_peric0 0x1028>; 905 samsung,mode = <USI_MODE_UART>; 906 #address-cells = <1>; 907 #size-cells = <1>; 908 ranges; 909 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_10>, 910 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_10>; 911 clock-names = "pclk", "ipclk"; 912 status = "disabled"; 913 914 serial_5: serial@103a0000 { 915 compatible = "samsung,exynosautov9-uart", 916 "samsung,exynos850-uart"; 917 reg = <0x103a0000 0xc0>; 918 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 919 pinctrl-names = "default"; 920 pinctrl-0 = <&uart5_bus>; 921 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_10>, 922 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_10>; 923 clock-names = "uart", "clk_uart_baud0"; 924 samsung,uart-fifosize = <64>; 925 status = "disabled"; 926 }; 927 928 spi_5: spi@103a0000 { 929 compatible = "samsung,exynosautov9-spi"; 930 reg = <0x103a0000 0x30>; 931 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 932 pinctrl-names = "default"; 933 pinctrl-0 = <&spi5_bus &spi5_cs_func>; 934 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_10>, 935 <&cmu_peric0 CLK_DOUT_PERIC0_USI05_USI>, 936 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_10>; 937 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 938 samsung,spi-src-clk = <0>; 939 dmas = <&pdma0 11>, <&pdma0 10>; 940 dma-names = "tx", "rx"; 941 num-cs = <1>; 942 #address-cells = <1>; 943 #size-cells = <0>; 944 fifo-depth = <64>; 945 status = "disabled"; 946 }; 947 948 hsi2c_10: i2c@103a0000 { 949 compatible = "samsung,exynosautov9-hsi2c"; 950 reg = <0x103a0000 0xc0>; 951 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 952 pinctrl-names = "default"; 953 pinctrl-0 = <&hsi2c10_bus>; 954 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_10>, 955 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_10>; 956 clock-names = "hsi2c", "hsi2c_pclk"; 957 #address-cells = <1>; 958 #size-cells = <0>; 959 status = "disabled"; 960 }; 961 }; 962 963 usi_i2c_5: usi@103b00c0 { 964 compatible = "samsung,exynosautov9-usi", 965 "samsung,exynos850-usi"; 966 reg = <0x103b00c0 0x20>; 967 samsung,sysreg = <&syscon_peric0 0x102c>; 968 samsung,mode = <USI_MODE_I2C>; 969 #address-cells = <1>; 970 #size-cells = <1>; 971 ranges; 972 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_11>, 973 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_11>; 974 clock-names = "pclk", "ipclk"; 975 status = "disabled"; 976 977 hsi2c_11: i2c@103b0000 { 978 compatible = "samsung,exynosautov9-hsi2c"; 979 reg = <0x103b0000 0xc0>; 980 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 981 pinctrl-names = "default"; 982 pinctrl-0 = <&hsi2c11_bus>; 983 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_11>, 984 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_11>; 985 clock-names = "hsi2c", "hsi2c_pclk"; 986 #address-cells = <1>; 987 #size-cells = <0>; 988 status = "disabled"; 989 }; 990 }; 991 992 usi_6: usi@109000c0 { 993 compatible = "samsung,exynosautov9-usi", 994 "samsung,exynos850-usi"; 995 reg = <0x109000c0 0x20>; 996 samsung,sysreg = <&syscon_peric1 0x1000>; 997 samsung,mode = <USI_MODE_UART>; 998 #address-cells = <1>; 999 #size-cells = <1>; 1000 ranges; 1001 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_0>, 1002 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_0>; 1003 clock-names = "pclk", "ipclk"; 1004 status = "disabled"; 1005 1006 serial_6: serial@10900000 { 1007 compatible = "samsung,exynosautov9-uart", 1008 "samsung,exynos850-uart"; 1009 reg = <0x10900000 0xc0>; 1010 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1011 pinctrl-names = "default"; 1012 pinctrl-0 = <&uart6_bus>; 1013 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_0>, 1014 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_0>; 1015 clock-names = "uart", "clk_uart_baud0"; 1016 samsung,uart-fifosize = <256>; 1017 status = "disabled"; 1018 }; 1019 1020 spi_6: spi@10900000 { 1021 compatible = "samsung,exynosautov9-spi"; 1022 reg = <0x10900000 0x30>; 1023 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1024 pinctrl-names = "default"; 1025 pinctrl-0 = <&spi6_bus &spi6_cs_func>; 1026 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_0>, 1027 <&cmu_peric1 CLK_DOUT_PERIC1_USI06_USI>, 1028 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_0>; 1029 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 1030 samsung,spi-src-clk = <0>; 1031 dmas = <&pdma0 13>, <&pdma0 12>; 1032 dma-names = "tx", "rx"; 1033 num-cs = <1>; 1034 #address-cells = <1>; 1035 #size-cells = <0>; 1036 fifo-depth = <256>; 1037 status = "disabled"; 1038 }; 1039 1040 hsi2c_12: i2c@10900000 { 1041 compatible = "samsung,exynosautov9-hsi2c"; 1042 reg = <0x10900000 0xc0>; 1043 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1044 pinctrl-names = "default"; 1045 pinctrl-0 = <&hsi2c12_bus>; 1046 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_0>, 1047 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_0>; 1048 clock-names = "hsi2c", "hsi2c_pclk"; 1049 #address-cells = <1>; 1050 #size-cells = <0>; 1051 status = "disabled"; 1052 }; 1053 }; 1054 1055 usi_i2c_6: usi@109100c0 { 1056 compatible = "samsung,exynosautov9-usi", 1057 "samsung,exynos850-usi"; 1058 reg = <0x109100c0 0x20>; 1059 samsung,sysreg = <&syscon_peric1 0x1004>; 1060 samsung,mode = <USI_MODE_I2C>; 1061 #address-cells = <1>; 1062 #size-cells = <1>; 1063 ranges; 1064 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_1>, 1065 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_1>; 1066 clock-names = "pclk", "ipclk"; 1067 status = "disabled"; 1068 1069 hsi2c_13: i2c@10910000 { 1070 compatible = "samsung,exynosautov9-hsi2c"; 1071 reg = <0x10910000 0xc0>; 1072 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1073 pinctrl-names = "default"; 1074 pinctrl-0 = <&hsi2c13_bus>; 1075 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_1>, 1076 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_1>; 1077 clock-names = "hsi2c", "hsi2c_pclk"; 1078 #address-cells = <1>; 1079 #size-cells = <0>; 1080 status = "disabled"; 1081 }; 1082 }; 1083 1084 usi_7: usi@109200c0 { 1085 compatible = "samsung,exynosautov9-usi", 1086 "samsung,exynos850-usi"; 1087 reg = <0x109200c0 0x20>; 1088 samsung,sysreg = <&syscon_peric1 0x1008>; 1089 samsung,mode = <USI_MODE_UART>; 1090 #address-cells = <1>; 1091 #size-cells = <1>; 1092 ranges; 1093 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_2>, 1094 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_2>; 1095 clock-names = "pclk", "ipclk"; 1096 status = "disabled"; 1097 1098 serial_7: serial@10920000 { 1099 compatible = "samsung,exynosautov9-uart", 1100 "samsung,exynos850-uart"; 1101 reg = <0x10920000 0xc0>; 1102 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1103 pinctrl-names = "default"; 1104 pinctrl-0 = <&uart7_bus>; 1105 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_2>, 1106 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_2>; 1107 clock-names = "uart", "clk_uart_baud0"; 1108 samsung,uart-fifosize = <64>; 1109 status = "disabled"; 1110 }; 1111 1112 spi_7: spi@10920000 { 1113 compatible = "samsung,exynosautov9-spi"; 1114 reg = <0x10920000 0x30>; 1115 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1116 pinctrl-names = "default"; 1117 pinctrl-0 = <&spi7_bus &spi7_cs_func>; 1118 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_2>, 1119 <&cmu_peric1 CLK_DOUT_PERIC1_USI07_USI>, 1120 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_2>; 1121 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 1122 samsung,spi-src-clk = <0>; 1123 dmas = <&pdma0 15>, <&pdma0 14>; 1124 dma-names = "tx", "rx"; 1125 num-cs = <1>; 1126 #address-cells = <1>; 1127 #size-cells = <0>; 1128 fifo-depth = <64>; 1129 status = "disabled"; 1130 }; 1131 1132 hsi2c_14: i2c@10920000 { 1133 compatible = "samsung,exynosautov9-hsi2c"; 1134 reg = <0x10920000 0xc0>; 1135 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1136 pinctrl-names = "default"; 1137 pinctrl-0 = <&hsi2c14_bus>; 1138 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_2>, 1139 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_2>; 1140 clock-names = "hsi2c", "hsi2c_pclk"; 1141 #address-cells = <1>; 1142 #size-cells = <0>; 1143 status = "disabled"; 1144 }; 1145 }; 1146 1147 usi_i2c_7: usi@109300c0 { 1148 compatible = "samsung,exynosautov9-usi", 1149 "samsung,exynos850-usi"; 1150 reg = <0x109300c0 0x20>; 1151 samsung,sysreg = <&syscon_peric1 0x100c>; 1152 samsung,mode = <USI_MODE_I2C>; 1153 #address-cells = <1>; 1154 #size-cells = <1>; 1155 ranges; 1156 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_3>, 1157 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_3>; 1158 clock-names = "pclk", "ipclk"; 1159 status = "disabled"; 1160 1161 hsi2c_15: i2c@10930000 { 1162 compatible = "samsung,exynosautov9-hsi2c"; 1163 reg = <0x10930000 0xc0>; 1164 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1165 pinctrl-names = "default"; 1166 pinctrl-0 = <&hsi2c15_bus>; 1167 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_3>, 1168 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_3>; 1169 clock-names = "hsi2c", "hsi2c_pclk"; 1170 #address-cells = <1>; 1171 #size-cells = <0>; 1172 status = "disabled"; 1173 }; 1174 }; 1175 1176 usi_8: usi@109400c0 { 1177 compatible = "samsung,exynosautov9-usi", 1178 "samsung,exynos850-usi"; 1179 reg = <0x109400c0 0x20>; 1180 samsung,sysreg = <&syscon_peric1 0x1010>; 1181 samsung,mode = <USI_MODE_UART>; 1182 #address-cells = <1>; 1183 #size-cells = <1>; 1184 ranges; 1185 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_4>, 1186 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_4>; 1187 clock-names = "pclk", "ipclk"; 1188 status = "disabled"; 1189 1190 serial_8: serial@10940000 { 1191 compatible = "samsung,exynosautov9-uart", 1192 "samsung,exynos850-uart"; 1193 reg = <0x10940000 0xc0>; 1194 interrupts = <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>; 1195 pinctrl-names = "default"; 1196 pinctrl-0 = <&uart8_bus>; 1197 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_4>, 1198 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_4>; 1199 clock-names = "uart", "clk_uart_baud0"; 1200 samsung,uart-fifosize = <64>; 1201 status = "disabled"; 1202 }; 1203 1204 spi_8: spi@10940000 { 1205 compatible = "samsung,exynosautov9-spi"; 1206 reg = <0x10940000 0x30>; 1207 interrupts = <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>; 1208 pinctrl-names = "default"; 1209 pinctrl-0 = <&spi8_bus &spi8_cs_func>; 1210 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_4>, 1211 <&cmu_peric1 CLK_DOUT_PERIC1_USI08_USI>, 1212 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_4>; 1213 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 1214 samsung,spi-src-clk = <0>; 1215 dmas = <&pdma0 17>, <&pdma0 16>; 1216 dma-names = "tx", "rx"; 1217 num-cs = <1>; 1218 #address-cells = <1>; 1219 #size-cells = <0>; 1220 fifo-depth = <64>; 1221 status = "disabled"; 1222 }; 1223 1224 hsi2c_16: i2c@10940000 { 1225 compatible = "samsung,exynosautov9-hsi2c"; 1226 reg = <0x10940000 0xc0>; 1227 interrupts = <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>; 1228 pinctrl-names = "default"; 1229 pinctrl-0 = <&hsi2c16_bus>; 1230 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_4>, 1231 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_4>; 1232 clock-names = "hsi2c", "hsi2c_pclk"; 1233 #address-cells = <1>; 1234 #size-cells = <0>; 1235 status = "disabled"; 1236 }; 1237 }; 1238 1239 usi_i2c_8: usi@109500c0 { 1240 compatible = "samsung,exynosautov9-usi", 1241 "samsung,exynos850-usi"; 1242 reg = <0x109500c0 0x20>; 1243 samsung,sysreg = <&syscon_peric1 0x1014>; 1244 samsung,mode = <USI_MODE_I2C>; 1245 #address-cells = <1>; 1246 #size-cells = <1>; 1247 ranges; 1248 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_5>, 1249 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_5>; 1250 clock-names = "pclk", "ipclk"; 1251 status = "disabled"; 1252 1253 hsi2c_17: i2c@10950000 { 1254 compatible = "samsung,exynosautov9-hsi2c"; 1255 reg = <0x10950000 0xc0>; 1256 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; 1257 pinctrl-names = "default"; 1258 pinctrl-0 = <&hsi2c17_bus>; 1259 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_5>, 1260 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_5>; 1261 clock-names = "hsi2c", "hsi2c_pclk"; 1262 #address-cells = <1>; 1263 #size-cells = <0>; 1264 status = "disabled"; 1265 }; 1266 }; 1267 1268 usi_9: usi@109600c0 { 1269 compatible = "samsung,exynosautov9-usi", 1270 "samsung,exynos850-usi"; 1271 reg = <0x109600c0 0x20>; 1272 samsung,sysreg = <&syscon_peric1 0x1018>; 1273 samsung,mode = <USI_MODE_UART>; 1274 #address-cells = <1>; 1275 #size-cells = <1>; 1276 ranges; 1277 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_6>, 1278 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_6>; 1279 clock-names = "pclk", "ipclk"; 1280 status = "disabled"; 1281 1282 serial_9: serial@10960000 { 1283 compatible = "samsung,exynosautov9-uart", 1284 "samsung,exynos850-uart"; 1285 reg = <0x10960000 0xc0>; 1286 interrupts = <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>; 1287 pinctrl-names = "default"; 1288 pinctrl-0 = <&uart9_bus>; 1289 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_6>, 1290 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_6>; 1291 clock-names = "uart", "clk_uart_baud0"; 1292 samsung,uart-fifosize = <64>; 1293 status = "disabled"; 1294 }; 1295 1296 spi_9: spi@10960000 { 1297 compatible = "samsung,exynosautov9-spi"; 1298 reg = <0x10960000 0x30>; 1299 interrupts = <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>; 1300 pinctrl-names = "default"; 1301 pinctrl-0 = <&spi9_bus &spi9_cs_func>; 1302 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_6>, 1303 <&cmu_peric1 CLK_DOUT_PERIC1_USI09_USI>, 1304 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_6>; 1305 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 1306 samsung,spi-src-clk = <0>; 1307 dmas = <&pdma0 19>, <&pdma0 18>; 1308 dma-names = "tx", "rx"; 1309 num-cs = <1>; 1310 #address-cells = <1>; 1311 #size-cells = <0>; 1312 fifo-depth = <64>; 1313 status = "disabled"; 1314 }; 1315 1316 hsi2c_18: i2c@10960000 { 1317 compatible = "samsung,exynosautov9-hsi2c"; 1318 reg = <0x10960000 0xc0>; 1319 interrupts = <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>; 1320 pinctrl-names = "default"; 1321 pinctrl-0 = <&hsi2c18_bus>; 1322 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_6>, 1323 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_6>; 1324 clock-names = "hsi2c", "hsi2c_pclk"; 1325 #address-cells = <1>; 1326 #size-cells = <0>; 1327 status = "disabled"; 1328 }; 1329 }; 1330 1331 usi_i2c_9: usi@109700c0 { 1332 compatible = "samsung,exynosautov9-usi", 1333 "samsung,exynos850-usi"; 1334 reg = <0x109700c0 0x20>; 1335 samsung,sysreg = <&syscon_peric1 0x101c>; 1336 samsung,mode = <USI_MODE_I2C>; 1337 #address-cells = <1>; 1338 #size-cells = <1>; 1339 ranges; 1340 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_7>, 1341 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_7>; 1342 clock-names = "pclk", "ipclk"; 1343 status = "disabled"; 1344 1345 hsi2c_19: i2c@10970000 { 1346 compatible = "samsung,exynosautov9-hsi2c"; 1347 reg = <0x10970000 0xc0>; 1348 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1349 pinctrl-names = "default"; 1350 pinctrl-0 = <&hsi2c19_bus>; 1351 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_7>, 1352 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_7>; 1353 clock-names = "hsi2c", "hsi2c_pclk"; 1354 #address-cells = <1>; 1355 #size-cells = <0>; 1356 status = "disabled"; 1357 }; 1358 }; 1359 1360 usi_10: usi@109800c0 { 1361 compatible = "samsung,exynosautov9-usi", 1362 "samsung,exynos850-usi"; 1363 reg = <0x109800c0 0x20>; 1364 samsung,sysreg = <&syscon_peric1 0x1020>; 1365 samsung,mode = <USI_MODE_UART>; 1366 #address-cells = <1>; 1367 #size-cells = <1>; 1368 ranges; 1369 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_8>, 1370 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_8>; 1371 clock-names = "pclk", "ipclk"; 1372 status = "disabled"; 1373 1374 serial_10: serial@10980000 { 1375 compatible = "samsung,exynosautov9-uart", 1376 "samsung,exynos850-uart"; 1377 reg = <0x10980000 0xc0>; 1378 interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>; 1379 pinctrl-names = "default"; 1380 pinctrl-0 = <&uart10_bus>; 1381 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_8>, 1382 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_8>; 1383 clock-names = "uart", "clk_uart_baud0"; 1384 samsung,uart-fifosize = <64>; 1385 status = "disabled"; 1386 }; 1387 1388 spi_10: spi@10980000 { 1389 compatible = "samsung,exynosautov9-spi"; 1390 reg = <0x10980000 0x30>; 1391 interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>; 1392 pinctrl-names = "default"; 1393 pinctrl-0 = <&spi10_bus &spi10_cs_func>; 1394 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_8>, 1395 <&cmu_peric1 CLK_DOUT_PERIC1_USI10_USI>, 1396 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_8>; 1397 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 1398 samsung,spi-src-clk = <0>; 1399 dmas = <&pdma0 21>, <&pdma0 20>; 1400 dma-names = "tx", "rx"; 1401 num-cs = <1>; 1402 #address-cells = <1>; 1403 #size-cells = <0>; 1404 fifo-depth = <64>; 1405 status = "disabled"; 1406 }; 1407 1408 hsi2c_20: i2c@10980000 { 1409 compatible = "samsung,exynosautov9-hsi2c"; 1410 reg = <0x10980000 0xc0>; 1411 interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>; 1412 pinctrl-names = "default"; 1413 pinctrl-0 = <&hsi2c20_bus>; 1414 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_8>, 1415 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_8>; 1416 clock-names = "hsi2c", "hsi2c_pclk"; 1417 #address-cells = <1>; 1418 #size-cells = <0>; 1419 status = "disabled"; 1420 }; 1421 }; 1422 1423 usi_i2c_10: usi@109900c0 { 1424 compatible = "samsung,exynosautov9-usi", 1425 "samsung,exynos850-usi"; 1426 reg = <0x109900c0 0x20>; 1427 samsung,sysreg = <&syscon_peric1 0x1024>; 1428 samsung,mode = <USI_MODE_I2C>; 1429 #address-cells = <1>; 1430 #size-cells = <1>; 1431 ranges; 1432 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_9>, 1433 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_9>; 1434 clock-names = "pclk", "ipclk"; 1435 status = "disabled"; 1436 1437 hsi2c_21: i2c@10990000 { 1438 compatible = "samsung,exynosautov9-hsi2c"; 1439 reg = <0x10990000 0xc0>; 1440 interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>; 1441 pinctrl-names = "default"; 1442 pinctrl-0 = <&hsi2c21_bus>; 1443 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_9>, 1444 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_9>; 1445 clock-names = "hsi2c", "hsi2c_pclk"; 1446 #address-cells = <1>; 1447 #size-cells = <0>; 1448 status = "disabled"; 1449 }; 1450 }; 1451 1452 usi_11: usi@109a00c0 { 1453 compatible = "samsung,exynosautov9-usi", 1454 "samsung,exynos850-usi"; 1455 reg = <0x109a00c0 0x20>; 1456 samsung,sysreg = <&syscon_peric1 0x1028>; 1457 samsung,mode = <USI_MODE_UART>; 1458 #address-cells = <1>; 1459 #size-cells = <1>; 1460 ranges; 1461 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_10>, 1462 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_10>; 1463 clock-names = "pclk", "ipclk"; 1464 status = "disabled"; 1465 1466 serial_11: serial@109a0000 { 1467 compatible = "samsung,exynosautov9-uart", 1468 "samsung,exynos850-uart"; 1469 reg = <0x109a0000 0xc0>; 1470 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1471 pinctrl-names = "default"; 1472 pinctrl-0 = <&uart11_bus>; 1473 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_10>, 1474 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_10>; 1475 clock-names = "uart", "clk_uart_baud0"; 1476 samsung,uart-fifosize = <64>; 1477 status = "disabled"; 1478 }; 1479 1480 spi_11: spi@109a0000 { 1481 compatible = "samsung,exynosautov9-spi"; 1482 reg = <0x109a0000 0x30>; 1483 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1484 pinctrl-names = "default"; 1485 pinctrl-0 = <&spi11_bus &spi11_cs_func>; 1486 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_10>, 1487 <&cmu_peric1 CLK_DOUT_PERIC1_USI11_USI>, 1488 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_10>; 1489 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 1490 samsung,spi-src-clk = <0>; 1491 num-cs = <1>; 1492 #address-cells = <1>; 1493 #size-cells = <0>; 1494 fifo-depth = <64>; 1495 status = "disabled"; 1496 }; 1497 1498 hsi2c_22: i2c@109a0000 { 1499 compatible = "samsung,exynosautov9-hsi2c"; 1500 reg = <0x109a0000 0xc0>; 1501 pinctrl-names = "default"; 1502 pinctrl-0 = <&hsi2c22_bus>; 1503 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1504 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_10>, 1505 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_10>; 1506 clock-names = "hsi2c", "hsi2c_pclk"; 1507 #address-cells = <1>; 1508 #size-cells = <0>; 1509 status = "disabled"; 1510 }; 1511 }; 1512 1513 usi_i2c_11: usi@109b00c0 { 1514 compatible = "samsung,exynosautov9-usi", 1515 "samsung,exynos850-usi"; 1516 reg = <0x109b00c0 0x20>; 1517 samsung,sysreg = <&syscon_peric1 0x102c>; 1518 samsung,mode = <USI_MODE_I2C>; 1519 #address-cells = <1>; 1520 #size-cells = <1>; 1521 ranges; 1522 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_11>, 1523 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_11>; 1524 clock-names = "pclk", "ipclk"; 1525 status = "disabled"; 1526 1527 hsi2c_23: i2c@109b0000 { 1528 compatible = "samsung,exynosautov9-hsi2c"; 1529 reg = <0x109b0000 0xc0>; 1530 interrupts = <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>; 1531 pinctrl-names = "default"; 1532 pinctrl-0 = <&hsi2c23_bus>; 1533 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_11>, 1534 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_11>; 1535 clock-names = "hsi2c", "hsi2c_pclk"; 1536 #address-cells = <1>; 1537 #size-cells = <0>; 1538 status = "disabled"; 1539 }; 1540 }; 1541 1542 ufs_0_phy: phy@17e04000 { 1543 compatible = "samsung,exynosautov9-ufs-phy"; 1544 reg = <0x17e04000 0xc00>; 1545 reg-names = "phy-pma"; 1546 samsung,pmu-syscon = <&pmu_system_controller>; 1547 #phy-cells = <0>; 1548 clocks = <&xtcxo>; 1549 clock-names = "ref_clk"; 1550 status = "disabled"; 1551 }; 1552 1553 ufs_0: ufs@17e00000 { 1554 compatible = "samsung,exynosautov9-ufs"; 1555 1556 reg = <0x17e00000 0x100>, 1557 <0x17e01100 0x410>, 1558 <0x17e80000 0x8000>, 1559 <0x17dc0000 0x2200>; 1560 reg-names = "hci", "vs_hci", "unipro", "ufsp"; 1561 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 1562 clocks = <&cmu_fsys2 CLK_GOUT_FSYS2_UFS_EMBD0_ACLK>, 1563 <&cmu_fsys2 CLK_GOUT_FSYS2_UFS_EMBD0_UNIPRO>; 1564 clock-names = "core_clk", "sclk_unipro_main"; 1565 freq-table-hz = <0 0>, <0 0>; 1566 pinctrl-names = "default"; 1567 pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>; 1568 phys = <&ufs_0_phy>; 1569 phy-names = "ufs-phy"; 1570 samsung,sysreg = <&syscon_fsys2 0x710>; 1571 status = "disabled"; 1572 }; 1573 1574 ufs_1_phy: phy@17f04000 { 1575 compatible = "samsung,exynosautov9-ufs-phy"; 1576 reg = <0x17f04000 0xc00>; 1577 reg-names = "phy-pma"; 1578 samsung,pmu-syscon = <&pmu_system_controller 0x72c>; 1579 #phy-cells = <0>; 1580 clocks = <&xtcxo>; 1581 clock-names = "ref_clk"; 1582 status = "disabled"; 1583 }; 1584 1585 ufs_1: ufs@17f00000 { 1586 compatible = "samsung,exynosautov9-ufs"; 1587 1588 reg = <0x17f00000 0x100>, 1589 <0x17f01100 0x410>, 1590 <0x17f80000 0x8000>, 1591 <0x17de0000 0x2200>; 1592 reg-names = "hci", "vs_hci", "unipro", "ufsp"; 1593 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 1594 clocks = <&cmu_fsys2 CLK_GOUT_FSYS2_UFS_EMBD1_ACLK>, 1595 <&cmu_fsys2 CLK_GOUT_FSYS2_UFS_EMBD1_UNIPRO>; 1596 clock-names = "core_clk", "sclk_unipro_main"; 1597 freq-table-hz = <0 0>, <0 0>; 1598 pinctrl-names = "default"; 1599 pinctrl-0 = <&ufs_rst_n_1 &ufs_refclk_out_1>; 1600 phys = <&ufs_1_phy>; 1601 phy-names = "ufs-phy"; 1602 samsung,sysreg = <&syscon_fsys2 0x714>; 1603 status = "disabled"; 1604 }; 1605 1606 watchdog_cl0: watchdog@10050000 { 1607 compatible = "samsung,exynosautov9-wdt"; 1608 reg = <0x10050000 0x100>; 1609 interrupts = <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>; 1610 clocks = <&cmu_peris CLK_GOUT_WDT_CLUSTER0>, <&xtcxo>; 1611 clock-names = "watchdog", "watchdog_src"; 1612 samsung,syscon-phandle = <&pmu_system_controller>; 1613 samsung,cluster-index = <0>; 1614 }; 1615 1616 watchdog_cl1: watchdog@10060000 { 1617 compatible = "samsung,exynosautov9-wdt"; 1618 reg = <0x10060000 0x100>; 1619 interrupts = <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>; 1620 clocks = <&cmu_peris CLK_GOUT_WDT_CLUSTER1>, <&xtcxo>; 1621 clock-names = "watchdog", "watchdog_src"; 1622 samsung,syscon-phandle = <&pmu_system_controller>; 1623 samsung,cluster-index = <1>; 1624 }; 1625 1626 pwm: pwm@103f0000 { 1627 compatible = "samsung,exynosautov9-pwm", 1628 "samsung,exynos4210-pwm"; 1629 reg = <0x103f0000 0x100>; 1630 samsung,pwm-outputs = <0>, <1>, <2>, <3>; 1631 #pwm-cells = <3>; 1632 clocks = <&xtcxo>; 1633 clock-names = "timers"; 1634 status = "disabled"; 1635 }; 1636 }; 1637}; 1638 1639#include "exynosautov9-pinctrl.dtsi"
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