exynos5433.dtsi

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Samsung's Exynos5433 SoC device tree source
   4 *
   5 * Copyright (c) 2016 Samsung Electronics Co., Ltd.
   6 *
   7 * Samsung's Exynos5433 SoC device nodes are listed in this file.
   8 * Exynos5433 based board files can include this file and provide
   9 * values for board specific bindings.
  10 *
  11 * Note: This file does not include device nodes for all the controllers in
  12 * Exynos5433 SoC. As device tree coverage for Exynos5433 increases,
  13 * additional nodes can be added to this file.
  14 */
  15
  16#include <dt-bindings/clock/exynos5433.h>
  17#include <dt-bindings/interrupt-controller/arm-gic.h>
  18
  19/ {
  20	compatible = "samsung,exynos5433";
  21	#address-cells = <2>;
  22	#size-cells = <2>;
  23
  24	interrupt-parent = <&gic>;
  25
  26	arm-a53-pmu {
  27		compatible = "arm,cortex-a53-pmu";
  28		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
  29			     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
  30			     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
  31			     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
  32		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  33	};
  34
  35	arm-a57-pmu {
  36		compatible = "arm,cortex-a57-pmu";
  37		interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
  38			     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
  39			     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
  40			     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
  41		interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
  42	};
  43
  44	xxti: clock {
  45		/* XXTI */
  46		compatible = "fixed-clock";
  47		clock-output-names = "oscclk";
  48		#clock-cells = <0>;
  49	};
  50
  51	cpus {
  52		#address-cells = <1>;
  53		#size-cells = <0>;
  54
  55		cpu-map {
  56			cluster0 {
  57				core0 {
  58					cpu = <&cpu0>;
  59				};
  60				core1 {
  61					cpu = <&cpu1>;
  62				};
  63				core2 {
  64					cpu = <&cpu2>;
  65				};
  66				core3 {
  67					cpu = <&cpu3>;
  68				};
  69			};
  70
  71			cluster1 {
  72				core0 {
  73					cpu = <&cpu4>;
  74				};
  75				core1 {
  76					cpu = <&cpu5>;
  77				};
  78				core2 {
  79					cpu = <&cpu6>;
  80				};
  81				core3 {
  82					cpu = <&cpu7>;
  83				};
  84			};
  85		};
  86
  87		cpu0: cpu@100 {
  88			device_type = "cpu";
  89			compatible = "arm,cortex-a53";
  90			enable-method = "psci";
  91			reg = <0x100>;
  92			clocks = <&cmu_apollo CLK_SCLK_APOLLO>;
  93			clock-names = "apolloclk";
  94			operating-points-v2 = <&cluster_a53_opp_table>;
  95			#cooling-cells = <2>;
  96			i-cache-size = <0x8000>;
  97			i-cache-line-size = <64>;
  98			i-cache-sets = <256>;
  99			d-cache-size = <0x8000>;
 100			d-cache-line-size = <64>;
 101			d-cache-sets = <128>;
 102			next-level-cache = <&cluster_a53_l2>;
 103		};
 104
 105		cpu1: cpu@101 {
 106			device_type = "cpu";
 107			compatible = "arm,cortex-a53";
 108			enable-method = "psci";
 109			reg = <0x101>;
 110			operating-points-v2 = <&cluster_a53_opp_table>;
 111			#cooling-cells = <2>;
 112			i-cache-size = <0x8000>;
 113			i-cache-line-size = <64>;
 114			i-cache-sets = <256>;
 115			d-cache-size = <0x8000>;
 116			d-cache-line-size = <64>;
 117			d-cache-sets = <128>;
 118			next-level-cache = <&cluster_a53_l2>;
 119		};
 120
 121		cpu2: cpu@102 {
 122			device_type = "cpu";
 123			compatible = "arm,cortex-a53";
 124			enable-method = "psci";
 125			reg = <0x102>;
 126			operating-points-v2 = <&cluster_a53_opp_table>;
 127			#cooling-cells = <2>;
 128			i-cache-size = <0x8000>;
 129			i-cache-line-size = <64>;
 130			i-cache-sets = <256>;
 131			d-cache-size = <0x8000>;
 132			d-cache-line-size = <64>;
 133			d-cache-sets = <128>;
 134			next-level-cache = <&cluster_a53_l2>;
 135		};
 136
 137		cpu3: cpu@103 {
 138			device_type = "cpu";
 139			compatible = "arm,cortex-a53";
 140			enable-method = "psci";
 141			reg = <0x103>;
 142			operating-points-v2 = <&cluster_a53_opp_table>;
 143			#cooling-cells = <2>;
 144			i-cache-size = <0x8000>;
 145			i-cache-line-size = <64>;
 146			i-cache-sets = <256>;
 147			d-cache-size = <0x8000>;
 148			d-cache-line-size = <64>;
 149			d-cache-sets = <128>;
 150			next-level-cache = <&cluster_a53_l2>;
 151		};
 152
 153		cpu4: cpu@0 {
 154			device_type = "cpu";
 155			compatible = "arm,cortex-a57";
 156			enable-method = "psci";
 157			reg = <0x0>;
 158			clocks = <&cmu_atlas CLK_SCLK_ATLAS>;
 159			clock-names = "atlasclk";
 160			operating-points-v2 = <&cluster_a57_opp_table>;
 161			#cooling-cells = <2>;
 162			i-cache-size = <0xc000>;
 163			i-cache-line-size = <64>;
 164			i-cache-sets = <256>;
 165			d-cache-size = <0x8000>;
 166			d-cache-line-size = <64>;
 167			d-cache-sets = <256>;
 168			next-level-cache = <&cluster_a57_l2>;
 169		};
 170
 171		cpu5: cpu@1 {
 172			device_type = "cpu";
 173			compatible = "arm,cortex-a57";
 174			enable-method = "psci";
 175			reg = <0x1>;
 176			operating-points-v2 = <&cluster_a57_opp_table>;
 177			#cooling-cells = <2>;
 178			i-cache-size = <0xc000>;
 179			i-cache-line-size = <64>;
 180			i-cache-sets = <256>;
 181			d-cache-size = <0x8000>;
 182			d-cache-line-size = <64>;
 183			d-cache-sets = <256>;
 184			next-level-cache = <&cluster_a57_l2>;
 185		};
 186
 187		cpu6: cpu@2 {
 188			device_type = "cpu";
 189			compatible = "arm,cortex-a57";
 190			enable-method = "psci";
 191			reg = <0x2>;
 192			operating-points-v2 = <&cluster_a57_opp_table>;
 193			#cooling-cells = <2>;
 194			i-cache-size = <0xc000>;
 195			i-cache-line-size = <64>;
 196			i-cache-sets = <256>;
 197			d-cache-size = <0x8000>;
 198			d-cache-line-size = <64>;
 199			d-cache-sets = <256>;
 200			next-level-cache = <&cluster_a57_l2>;
 201		};
 202
 203		cpu7: cpu@3 {
 204			device_type = "cpu";
 205			compatible = "arm,cortex-a57";
 206			enable-method = "psci";
 207			reg = <0x3>;
 208			operating-points-v2 = <&cluster_a57_opp_table>;
 209			#cooling-cells = <2>;
 210			i-cache-size = <0xc000>;
 211			i-cache-line-size = <64>;
 212			i-cache-sets = <256>;
 213			d-cache-size = <0x8000>;
 214			d-cache-line-size = <64>;
 215			d-cache-sets = <256>;
 216			next-level-cache = <&cluster_a57_l2>;
 217		};
 218
 219		cluster_a57_l2: l2-cache0 {
 220			compatible = "cache";
 221			cache-level = <2>;
 222			cache-unified;
 223			cache-size = <0x200000>;
 224			cache-line-size = <64>;
 225			cache-sets = <2048>;
 226		};
 227
 228		cluster_a53_l2: l2-cache1 {
 229			compatible = "cache";
 230			cache-level = <2>;
 231			cache-unified;
 232			cache-size = <0x40000>;
 233			cache-line-size = <64>;
 234			cache-sets = <256>;
 235		};
 236	};
 237
 238	cluster_a53_opp_table: opp-table-0 {
 239		compatible = "operating-points-v2";
 240		opp-shared;
 241
 242		opp-400000000 {
 243			opp-hz = /bits/ 64 <400000000>;
 244			opp-microvolt = <900000>;
 245		};
 246		opp-500000000 {
 247			opp-hz = /bits/ 64 <500000000>;
 248			opp-microvolt = <925000>;
 249		};
 250		opp-600000000 {
 251			opp-hz = /bits/ 64 <600000000>;
 252			opp-microvolt = <950000>;
 253		};
 254		opp-700000000 {
 255			opp-hz = /bits/ 64 <700000000>;
 256			opp-microvolt = <975000>;
 257		};
 258		opp-800000000 {
 259			opp-hz = /bits/ 64 <800000000>;
 260			opp-microvolt = <1000000>;
 261		};
 262		opp-900000000 {
 263			opp-hz = /bits/ 64 <900000000>;
 264			opp-microvolt = <1050000>;
 265		};
 266		opp-1000000000 {
 267			opp-hz = /bits/ 64 <1000000000>;
 268			opp-microvolt = <1075000>;
 269		};
 270		opp-1100000000 {
 271			opp-hz = /bits/ 64 <1100000000>;
 272			opp-microvolt = <1112500>;
 273		};
 274		opp-1200000000 {
 275			opp-hz = /bits/ 64 <1200000000>;
 276			opp-microvolt = <1112500>;
 277		};
 278		opp-1300000000 {
 279			opp-hz = /bits/ 64 <1300000000>;
 280			opp-microvolt = <1150000>;
 281		};
 282	};
 283
 284	cluster_a57_opp_table: opp-table-1 {
 285		compatible = "operating-points-v2";
 286		opp-shared;
 287
 288		opp-500000000 {
 289			opp-hz = /bits/ 64 <500000000>;
 290			opp-microvolt = <900000>;
 291		};
 292		opp-600000000 {
 293			opp-hz = /bits/ 64 <600000000>;
 294			opp-microvolt = <900000>;
 295		};
 296		opp-700000000 {
 297			opp-hz = /bits/ 64 <700000000>;
 298			opp-microvolt = <912500>;
 299		};
 300		opp-800000000 {
 301			opp-hz = /bits/ 64 <800000000>;
 302			opp-microvolt = <912500>;
 303		};
 304		opp-900000000 {
 305			opp-hz = /bits/ 64 <900000000>;
 306			opp-microvolt = <937500>;
 307		};
 308		opp-1000000000 {
 309			opp-hz = /bits/ 64 <1000000000>;
 310			opp-microvolt = <975000>;
 311		};
 312		opp-1100000000 {
 313			opp-hz = /bits/ 64 <1100000000>;
 314			opp-microvolt = <1012500>;
 315		};
 316		opp-1200000000 {
 317			opp-hz = /bits/ 64 <1200000000>;
 318			opp-microvolt = <1037500>;
 319		};
 320		opp-1300000000 {
 321			opp-hz = /bits/ 64 <1300000000>;
 322			opp-microvolt = <1062500>;
 323		};
 324		opp-1400000000 {
 325			opp-hz = /bits/ 64 <1400000000>;
 326			opp-microvolt = <1087500>;
 327		};
 328		opp-1500000000 {
 329			opp-hz = /bits/ 64 <1500000000>;
 330			opp-microvolt = <1125000>;
 331		};
 332		opp-1600000000 {
 333			opp-hz = /bits/ 64 <1600000000>;
 334			opp-microvolt = <1137500>;
 335		};
 336		opp-1700000000 {
 337			opp-hz = /bits/ 64 <1700000000>;
 338			opp-microvolt = <1175000>;
 339		};
 340		opp-1800000000 {
 341			opp-hz = /bits/ 64 <1800000000>;
 342			opp-microvolt = <1212500>;
 343		};
 344		opp-1900000000 {
 345			opp-hz = /bits/ 64 <1900000000>;
 346			opp-microvolt = <1262500>;
 347		};
 348	};
 349
 350	psci {
 351		compatible = "arm,psci";
 352		method = "smc";
 353		cpu_off = <0x84000002>;
 354		cpu_on = <0xc4000003>;
 355	};
 356
 357	soc: soc@0 {
 358		compatible = "simple-bus";
 359		#address-cells = <1>;
 360		#size-cells = <1>;
 361		ranges = <0x0 0x0 0x0 0x18000000>;
 362
 363		chipid@10000000 {
 364			compatible = "samsung,exynos5433-chipid",
 365				     "samsung,exynos4210-chipid";
 366			reg = <0x10000000 0x100>;
 367		};
 368
 369		cmu_top: clock-controller@10030000 {
 370			compatible = "samsung,exynos5433-cmu-top";
 371			reg = <0x10030000 0x1000>;
 372			#clock-cells = <1>;
 373
 374			clock-names = "oscclk",
 375				"sclk_mphy_pll",
 376				"sclk_mfc_pll",
 377				"sclk_bus_pll";
 378			clocks = <&xxti>,
 379				<&cmu_cpif CLK_SCLK_MPHY_PLL>,
 380				<&cmu_mif CLK_SCLK_MFC_PLL>,
 381				<&cmu_mif CLK_SCLK_BUS_PLL>;
 382		};
 383
 384		cmu_cpif: clock-controller@10fc0000 {
 385			compatible = "samsung,exynos5433-cmu-cpif";
 386			reg = <0x10fc0000 0x1000>;
 387			#clock-cells = <1>;
 388
 389			clock-names = "oscclk";
 390			clocks = <&xxti>;
 391		};
 392
 393		cmu_mif: clock-controller@105b0000 {
 394			compatible = "samsung,exynos5433-cmu-mif";
 395			reg = <0x105b0000 0x2000>;
 396			#clock-cells = <1>;
 397
 398			clock-names = "oscclk",
 399				"sclk_mphy_pll";
 400			clocks = <&xxti>,
 401				<&cmu_cpif CLK_SCLK_MPHY_PLL>;
 402		};
 403
 404		cmu_peric: clock-controller@14c80000 {
 405			compatible = "samsung,exynos5433-cmu-peric";
 406			reg = <0x14c80000 0x1000>;
 407			#clock-cells = <1>;
 408		};
 409
 410		cmu_peris: clock-controller@10040000 {
 411			compatible = "samsung,exynos5433-cmu-peris";
 412			reg = <0x10040000 0x1000>;
 413			#clock-cells = <1>;
 414		};
 415
 416		cmu_fsys: clock-controller@156e0000 {
 417			compatible = "samsung,exynos5433-cmu-fsys";
 418			reg = <0x156e0000 0x1000>;
 419			#clock-cells = <1>;
 420
 421			clock-names = "oscclk",
 422				"sclk_ufs_mphy",
 423				"aclk_fsys_200",
 424				"sclk_pcie_100_fsys",
 425				"sclk_ufsunipro_fsys",
 426				"sclk_mmc2_fsys",
 427				"sclk_mmc1_fsys",
 428				"sclk_mmc0_fsys",
 429				"sclk_usbhost30_fsys",
 430				"sclk_usbdrd30_fsys";
 431			clocks = <&xxti>,
 432				<&cmu_cpif CLK_SCLK_UFS_MPHY>,
 433				<&cmu_top CLK_ACLK_FSYS_200>,
 434				<&cmu_top CLK_SCLK_PCIE_100_FSYS>,
 435				<&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>,
 436				<&cmu_top CLK_SCLK_MMC2_FSYS>,
 437				<&cmu_top CLK_SCLK_MMC1_FSYS>,
 438				<&cmu_top CLK_SCLK_MMC0_FSYS>,
 439				<&cmu_top CLK_SCLK_USBHOST30_FSYS>,
 440				<&cmu_top CLK_SCLK_USBDRD30_FSYS>;
 441		};
 442
 443		cmu_g2d: clock-controller@12460000 {
 444			compatible = "samsung,exynos5433-cmu-g2d";
 445			reg = <0x12460000 0x1000>;
 446			#clock-cells = <1>;
 447
 448			clock-names = "oscclk",
 449				"aclk_g2d_266",
 450				"aclk_g2d_400";
 451			clocks = <&xxti>,
 452				<&cmu_top CLK_ACLK_G2D_266>,
 453				<&cmu_top CLK_ACLK_G2D_400>;
 454			power-domains = <&pd_g2d>;
 455		};
 456
 457		cmu_disp: clock-controller@13b90000 {
 458			compatible = "samsung,exynos5433-cmu-disp";
 459			reg = <0x13b90000 0x1000>;
 460			#clock-cells = <1>;
 461
 462			clock-names = "oscclk",
 463				"sclk_dsim1_disp",
 464				"sclk_dsim0_disp",
 465				"sclk_dsd_disp",
 466				"sclk_decon_tv_eclk_disp",
 467				"sclk_decon_vclk_disp",
 468				"sclk_decon_eclk_disp",
 469				"sclk_decon_tv_vclk_disp",
 470				"aclk_disp_333";
 471			clocks = <&xxti>,
 472				<&cmu_mif CLK_SCLK_DSIM1_DISP>,
 473				<&cmu_mif CLK_SCLK_DSIM0_DISP>,
 474				<&cmu_mif CLK_SCLK_DSD_DISP>,
 475				<&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
 476				<&cmu_mif CLK_SCLK_DECON_VCLK_DISP>,
 477				<&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
 478				<&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>,
 479				<&cmu_mif CLK_ACLK_DISP_333>;
 480			power-domains = <&pd_disp>;
 481		};
 482
 483		cmu_aud: clock-controller@114c0000 {
 484			compatible = "samsung,exynos5433-cmu-aud";
 485			reg = <0x114c0000 0x1000>;
 486			#clock-cells = <1>;
 487			clock-names = "oscclk", "fout_aud_pll";
 488			clocks = <&xxti>, <&cmu_top CLK_FOUT_AUD_PLL>;
 489			power-domains = <&pd_aud>;
 490		};
 491
 492		cmu_bus0: clock-controller@13600000 {
 493			compatible = "samsung,exynos5433-cmu-bus0";
 494			reg = <0x13600000 0x1000>;
 495			#clock-cells = <1>;
 496
 497			clock-names = "aclk_bus0_400";
 498			clocks = <&cmu_top CLK_ACLK_BUS0_400>;
 499		};
 500
 501		cmu_bus1: clock-controller@14800000 {
 502			compatible = "samsung,exynos5433-cmu-bus1";
 503			reg = <0x14800000 0x1000>;
 504			#clock-cells = <1>;
 505
 506			clock-names = "aclk_bus1_400";
 507			clocks = <&cmu_top CLK_ACLK_BUS1_400>;
 508		};
 509
 510		cmu_bus2: clock-controller@13400000 {
 511			compatible = "samsung,exynos5433-cmu-bus2";
 512			reg = <0x13400000 0x1000>;
 513			#clock-cells = <1>;
 514
 515			clock-names = "oscclk", "aclk_bus2_400";
 516			clocks = <&xxti>, <&cmu_mif CLK_ACLK_BUS2_400>;
 517		};
 518
 519		cmu_g3d: clock-controller@14aa0000 {
 520			compatible = "samsung,exynos5433-cmu-g3d";
 521			reg = <0x14aa0000 0x2000>;
 522			#clock-cells = <1>;
 523
 524			clock-names = "oscclk", "aclk_g3d_400";
 525			clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>;
 526			power-domains = <&pd_g3d>;
 527		};
 528
 529		cmu_gscl: clock-controller@13cf0000 {
 530			compatible = "samsung,exynos5433-cmu-gscl";
 531			reg = <0x13cf0000 0x1000>;
 532			#clock-cells = <1>;
 533
 534			clock-names = "oscclk",
 535				"aclk_gscl_111",
 536				"aclk_gscl_333";
 537			clocks = <&xxti>,
 538				<&cmu_top CLK_ACLK_GSCL_111>,
 539				<&cmu_top CLK_ACLK_GSCL_333>;
 540			power-domains = <&pd_gscl>;
 541		};
 542
 543		cmu_apollo: clock-controller@11900000 {
 544			compatible = "samsung,exynos5433-cmu-apollo";
 545			reg = <0x11900000 0x2000>;
 546			#clock-cells = <1>;
 547
 548			clock-names = "oscclk", "sclk_bus_pll_apollo";
 549			clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_APOLLO>;
 550		};
 551
 552		cmu_atlas: clock-controller@11800000 {
 553			compatible = "samsung,exynos5433-cmu-atlas";
 554			reg = <0x11800000 0x2000>;
 555			#clock-cells = <1>;
 556
 557			clock-names = "oscclk", "sclk_bus_pll_atlas";
 558			clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_ATLAS>;
 559		};
 560
 561		cmu_mscl: clock-controller@150d0000 {
 562			compatible = "samsung,exynos5433-cmu-mscl";
 563			reg = <0x150d0000 0x1000>;
 564			#clock-cells = <1>;
 565
 566			clock-names = "oscclk",
 567				"sclk_jpeg_mscl",
 568				"aclk_mscl_400";
 569			clocks = <&xxti>,
 570				<&cmu_top CLK_SCLK_JPEG_MSCL>,
 571				<&cmu_top CLK_ACLK_MSCL_400>;
 572			power-domains = <&pd_mscl>;
 573		};
 574
 575		cmu_mfc: clock-controller@15280000 {
 576			compatible = "samsung,exynos5433-cmu-mfc";
 577			reg = <0x15280000 0x1000>;
 578			#clock-cells = <1>;
 579
 580			clock-names = "oscclk", "aclk_mfc_400";
 581			clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>;
 582			power-domains = <&pd_mfc>;
 583		};
 584
 585		cmu_hevc: clock-controller@14f80000 {
 586			compatible = "samsung,exynos5433-cmu-hevc";
 587			reg = <0x14f80000 0x1000>;
 588			#clock-cells = <1>;
 589
 590			clock-names = "oscclk", "aclk_hevc_400";
 591			clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>;
 592			power-domains = <&pd_hevc>;
 593		};
 594
 595		cmu_isp: clock-controller@146d0000 {
 596			compatible = "samsung,exynos5433-cmu-isp";
 597			reg = <0x146d0000 0x1000>;
 598			#clock-cells = <1>;
 599
 600			clock-names = "oscclk",
 601				"aclk_isp_dis_400",
 602				"aclk_isp_400";
 603			clocks = <&xxti>,
 604				<&cmu_top CLK_ACLK_ISP_DIS_400>,
 605				<&cmu_top CLK_ACLK_ISP_400>;
 606			power-domains = <&pd_isp>;
 607		};
 608
 609		cmu_cam0: clock-controller@120d0000 {
 610			compatible = "samsung,exynos5433-cmu-cam0";
 611			reg = <0x120d0000 0x1000>;
 612			#clock-cells = <1>;
 613
 614			clock-names = "oscclk",
 615				"aclk_cam0_333",
 616				"aclk_cam0_400",
 617				"aclk_cam0_552";
 618			clocks = <&xxti>,
 619				<&cmu_top CLK_ACLK_CAM0_333>,
 620				<&cmu_top CLK_ACLK_CAM0_400>,
 621				<&cmu_top CLK_ACLK_CAM0_552>;
 622			power-domains = <&pd_cam0>;
 623		};
 624
 625		cmu_cam1: clock-controller@145d0000 {
 626			compatible = "samsung,exynos5433-cmu-cam1";
 627			reg = <0x145d0000 0x1000>;
 628			#clock-cells = <1>;
 629
 630			clock-names = "oscclk",
 631				"sclk_isp_uart_cam1",
 632				"sclk_isp_spi1_cam1",
 633				"sclk_isp_spi0_cam1",
 634				"aclk_cam1_333",
 635				"aclk_cam1_400",
 636				"aclk_cam1_552";
 637			clocks = <&xxti>,
 638				<&cmu_top CLK_SCLK_ISP_UART_CAM1>,
 639				<&cmu_top CLK_SCLK_ISP_SPI1_CAM1>,
 640				<&cmu_top CLK_SCLK_ISP_SPI0_CAM1>,
 641				<&cmu_top CLK_ACLK_CAM1_333>,
 642				<&cmu_top CLK_ACLK_CAM1_400>,
 643				<&cmu_top CLK_ACLK_CAM1_552>;
 644			power-domains = <&pd_cam1>;
 645		};
 646
 647		cmu_imem: clock-controller@11060000 {
 648			compatible = "samsung,exynos5433-cmu-imem";
 649			reg = <0x11060000 0x1000>;
 650			#clock-cells = <1>;
 651
 652			clock-names = "oscclk",
 653				"aclk_imem_sssx_266",
 654				"aclk_imem_266",
 655				"aclk_imem_200";
 656			clocks = <&xxti>,
 657				<&cmu_top CLK_DIV_ACLK_IMEM_SSSX_266>,
 658				<&cmu_top CLK_DIV_ACLK_IMEM_266>,
 659				<&cmu_top CLK_DIV_ACLK_IMEM_200>;
 660		};
 661
 662		slim_sss: slim-sss@11140000 {
 663			compatible = "samsung,exynos5433-slim-sss";
 664			reg = <0x11140000 0x1000>;
 665			interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
 666			clock-names = "pclk", "aclk";
 667			clocks = <&cmu_imem CLK_PCLK_SLIMSSS>,
 668				 <&cmu_imem CLK_ACLK_SLIMSSS>;
 669		};
 670
 671		pd_gscl: power-domain@105c4000 {
 672			compatible = "samsung,exynos5433-pd";
 673			reg = <0x105c4000 0x20>;
 674			#power-domain-cells = <0>;
 675			label = "GSCL";
 676		};
 677
 678		pd_cam0: power-domain@105c4020 {
 679			compatible = "samsung,exynos5433-pd";
 680			reg = <0x105c4020 0x20>;
 681			#power-domain-cells = <0>;
 682			power-domains = <&pd_cam1>;
 683			label = "CAM0";
 684		};
 685
 686		pd_mscl: power-domain@105c4040 {
 687			compatible = "samsung,exynos5433-pd";
 688			reg = <0x105c4040 0x20>;
 689			#power-domain-cells = <0>;
 690			label = "MSCL";
 691		};
 692
 693		pd_g3d: power-domain@105c4060 {
 694			compatible = "samsung,exynos5433-pd";
 695			reg = <0x105c4060 0x20>;
 696			#power-domain-cells = <0>;
 697			label = "G3D";
 698		};
 699
 700		pd_disp: power-domain@105c4080 {
 701			compatible = "samsung,exynos5433-pd";
 702			reg = <0x105c4080 0x20>;
 703			#power-domain-cells = <0>;
 704			label = "DISP";
 705		};
 706
 707		pd_cam1: power-domain@105c40a0 {
 708			compatible = "samsung,exynos5433-pd";
 709			reg = <0x105c40a0 0x20>;
 710			#power-domain-cells = <0>;
 711			label = "CAM1";
 712		};
 713
 714		pd_aud: power-domain@105c40c0 {
 715			compatible = "samsung,exynos5433-pd";
 716			reg = <0x105c40c0 0x20>;
 717			#power-domain-cells = <0>;
 718			label = "AUD";
 719		};
 720
 721		pd_g2d: power-domain@105c4120 {
 722			compatible = "samsung,exynos5433-pd";
 723			reg = <0x105c4120 0x20>;
 724			#power-domain-cells = <0>;
 725			label = "G2D";
 726		};
 727
 728		pd_isp: power-domain@105c4140 {
 729			compatible = "samsung,exynos5433-pd";
 730			reg = <0x105c4140 0x20>;
 731			#power-domain-cells = <0>;
 732			power-domains = <&pd_cam0>;
 733			label = "ISP";
 734		};
 735
 736		pd_mfc: power-domain@105c4180 {
 737			compatible = "samsung,exynos5433-pd";
 738			reg = <0x105c4180 0x20>;
 739			#power-domain-cells = <0>;
 740			label = "MFC";
 741		};
 742
 743		pd_hevc: power-domain@105c41c0 {
 744			compatible = "samsung,exynos5433-pd";
 745			reg = <0x105c41c0 0x20>;
 746			#power-domain-cells = <0>;
 747			label = "HEVC";
 748		};
 749
 750		tmu_atlas0: tmu@10060000 {
 751			compatible = "samsung,exynos5433-tmu";
 752			reg = <0x10060000 0x200>;
 753			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 754			clocks = <&cmu_peris CLK_PCLK_TMU0_APBIF>,
 755				<&cmu_peris CLK_SCLK_TMU0>;
 756			clock-names = "tmu_apbif", "tmu_sclk";
 757			#thermal-sensor-cells = <0>;
 758			status = "disabled";
 759		};
 760
 761		tmu_atlas1: tmu@10068000 {
 762			compatible = "samsung,exynos5433-tmu";
 763			reg = <0x10068000 0x200>;
 764			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 765			clocks = <&cmu_peris CLK_PCLK_TMU0_APBIF>,
 766				<&cmu_peris CLK_SCLK_TMU0>;
 767			clock-names = "tmu_apbif", "tmu_sclk";
 768			#thermal-sensor-cells = <0>;
 769			status = "disabled";
 770		};
 771
 772		tmu_g3d: tmu@10070000 {
 773			compatible = "samsung,exynos5433-tmu";
 774			reg = <0x10070000 0x200>;
 775			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 776			clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>,
 777				<&cmu_peris CLK_SCLK_TMU1>;
 778			clock-names = "tmu_apbif", "tmu_sclk";
 779			#thermal-sensor-cells = <0>;
 780			status = "disabled";
 781		};
 782
 783		tmu_apollo: tmu@10078000 {
 784			compatible = "samsung,exynos5433-tmu";
 785			reg = <0x10078000 0x200>;
 786			interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 787			clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>,
 788				<&cmu_peris CLK_SCLK_TMU1>;
 789			clock-names = "tmu_apbif", "tmu_sclk";
 790			#thermal-sensor-cells = <0>;
 791			status = "disabled";
 792		};
 793
 794		tmu_isp: tmu@1007c000 {
 795			compatible = "samsung,exynos5433-tmu";
 796			reg = <0x1007c000 0x200>;
 797			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 798			clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>,
 799				<&cmu_peris CLK_SCLK_TMU1>;
 800			clock-names = "tmu_apbif", "tmu_sclk";
 801			#thermal-sensor-cells = <0>;
 802			status = "disabled";
 803		};
 804
 805		timer@101c0000 {
 806			compatible = "samsung,exynos5433-mct",
 807				     "samsung,exynos4210-mct";
 808			reg = <0x101c0000 0x800>;
 809			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 810				<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
 811				<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 812				<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 813				<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 814				<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 815				<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 816				<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 817				<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 818				<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 819				<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 820				<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 821			clocks = <&xxti>, <&cmu_peris CLK_PCLK_MCT>;
 822			clock-names = "fin_pll", "mct";
 823		};
 824
 825		ppmu_d0_cpu: ppmu@10480000 {
 826			compatible = "samsung,exynos-ppmu-v2";
 827			reg = <0x10480000 0x2000>;
 828			status = "disabled";
 829		};
 830
 831		ppmu_d0_general: ppmu@10490000 {
 832			compatible = "samsung,exynos-ppmu-v2";
 833			reg = <0x10490000 0x2000>;
 834			status = "disabled";
 835		};
 836
 837		ppmu_d1_cpu: ppmu@104b0000 {
 838			compatible = "samsung,exynos-ppmu-v2";
 839			reg = <0x104b0000 0x2000>;
 840			status = "disabled";
 841		};
 842
 843		ppmu_d1_general: ppmu@104c0000 {
 844			compatible = "samsung,exynos-ppmu-v2";
 845			reg = <0x104c0000 0x2000>;
 846			status = "disabled";
 847		};
 848
 849		pinctrl_alive: pinctrl@10580000 {
 850			compatible = "samsung,exynos5433-pinctrl";
 851			reg = <0x10580000 0x1a20>, <0x11090000 0x100>;
 852
 853			wakeup-interrupt-controller {
 854				compatible = "samsung,exynos5433-wakeup-eint",
 855					     "samsung,exynos7-wakeup-eint";
 856				interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 857			};
 858		};
 859
 860		pinctrl_aud: pinctrl@114b0000 {
 861			compatible = "samsung,exynos5433-pinctrl";
 862			reg = <0x114b0000 0x1000>;
 863			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 864			power-domains = <&pd_aud>;
 865		};
 866
 867		pinctrl_cpif: pinctrl@10fe0000 {
 868			compatible = "samsung,exynos5433-pinctrl";
 869			reg = <0x10fe0000 0x1000>;
 870			interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
 871		};
 872
 873		pinctrl_ese: pinctrl@14ca0000 {
 874			compatible = "samsung,exynos5433-pinctrl";
 875			reg = <0x14ca0000 0x1000>;
 876			interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
 877		};
 878
 879		pinctrl_finger: pinctrl@14cb0000 {
 880			compatible = "samsung,exynos5433-pinctrl";
 881			reg = <0x14cb0000 0x1000>;
 882			interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>;
 883		};
 884
 885		pinctrl_fsys: pinctrl@15690000 {
 886			compatible = "samsung,exynos5433-pinctrl";
 887			reg = <0x15690000 0x1000>;
 888			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
 889		};
 890
 891		pinctrl_imem: pinctrl@11090000 {
 892			compatible = "samsung,exynos5433-pinctrl";
 893			reg = <0x11090000 0x1000>;
 894			interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>;
 895		};
 896
 897		pinctrl_nfc: pinctrl@14cd0000 {
 898			compatible = "samsung,exynos5433-pinctrl";
 899			reg = <0x14cd0000 0x1000>;
 900			interrupts = <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>;
 901		};
 902
 903		pinctrl_peric: pinctrl@14cc0000 {
 904			compatible = "samsung,exynos5433-pinctrl";
 905			reg = <0x14cc0000 0x1100>;
 906			interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>;
 907		};
 908
 909		pinctrl_touch: pinctrl@14ce0000 {
 910			compatible = "samsung,exynos5433-pinctrl";
 911			reg = <0x14ce0000 0x1100>;
 912			interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
 913		};
 914
 915		pmu_system_controller: system-controller@105c0000 {
 916			compatible = "samsung,exynos5433-pmu", "simple-mfd", "syscon";
 917			reg = <0x105c0000 0x5008>;
 918			#clock-cells = <1>;
 919			clock-names = "clkout16";
 920			clocks = <&xxti>;
 921
 922			mipi_phy: mipi-phy {
 923				compatible = "samsung,exynos5433-mipi-video-phy";
 924				#phy-cells = <1>;
 925				samsung,cam0-sysreg = <&syscon_cam0>;
 926				samsung,cam1-sysreg = <&syscon_cam1>;
 927				samsung,disp-sysreg = <&syscon_disp>;
 928			};
 929
 930			reboot: syscon-reboot {
 931				compatible = "syscon-reboot";
 932				regmap = <&pmu_system_controller>;
 933				offset = <0x400>; /* SWRESET */
 934				mask = <0x1>;
 935			};
 936		};
 937
 938		gic: interrupt-controller@11001000 {
 939			compatible = "arm,gic-400";
 940			#address-cells = <0>;
 941			#interrupt-cells = <3>;
 942			interrupt-controller;
 943			reg = <0x11001000 0x1000>,
 944				<0x11002000 0x2000>,
 945				<0x11004000 0x2000>,
 946				<0x11006000 0x2000>;
 947			interrupts = <GIC_PPI 9 0xf04>;
 948		};
 949
 950		decon: decon@13800000 {
 951			compatible = "samsung,exynos5433-decon";
 952			reg = <0x13800000 0x2104>;
 953			clocks = <&cmu_disp CLK_PCLK_DECON>,
 954				<&cmu_disp CLK_ACLK_DECON>,
 955				<&cmu_disp CLK_ACLK_SMMU_DECON0X>,
 956				<&cmu_disp CLK_ACLK_XIU_DECON0X>,
 957				<&cmu_disp CLK_PCLK_SMMU_DECON0X>,
 958				<&cmu_disp CLK_ACLK_SMMU_DECON1X>,
 959				<&cmu_disp CLK_ACLK_XIU_DECON1X>,
 960				<&cmu_disp CLK_PCLK_SMMU_DECON1X>,
 961				<&cmu_disp CLK_SCLK_DECON_VCLK>,
 962				<&cmu_disp CLK_SCLK_DECON_ECLK>,
 963				<&cmu_disp CLK_SCLK_DSD>;
 964			clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x",
 965				"aclk_xiu_decon0x", "pclk_smmu_decon0x",
 966				"aclk_smmu_decon1x", "aclk_xiu_decon1x",
 967				"pclk_smmu_decon1x", "sclk_decon_vclk",
 968				"sclk_decon_eclk", "dsd";
 969			power-domains = <&pd_disp>;
 970			interrupt-names = "fifo", "vsync", "lcd_sys";
 971			interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
 972				     <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
 973				     <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
 974			samsung,disp-sysreg = <&syscon_disp>;
 975			status = "disabled";
 976			iommus = <&sysmmu_decon0x>, <&sysmmu_decon1x>;
 977			iommu-names = "m0", "m1";
 978
 979			ports {
 980				#address-cells = <1>;
 981				#size-cells = <0>;
 982
 983				port@0 {
 984					reg = <0>;
 985					decon_to_mic: endpoint {
 986						remote-endpoint =
 987							<&mic_to_decon>;
 988					};
 989				};
 990			};
 991		};
 992
 993		decon_tv: decon@13880000 {
 994			compatible = "samsung,exynos5433-decon-tv";
 995			reg = <0x13880000 0x20b8>;
 996			clocks = <&cmu_disp CLK_PCLK_DECON_TV>,
 997				 <&cmu_disp CLK_ACLK_DECON_TV>,
 998				 <&cmu_disp CLK_ACLK_SMMU_TV0X>,
 999				 <&cmu_disp CLK_ACLK_XIU_TV0X>,
1000				 <&cmu_disp CLK_PCLK_SMMU_TV0X>,
1001				 <&cmu_disp CLK_ACLK_SMMU_TV1X>,
1002				 <&cmu_disp CLK_ACLK_XIU_TV1X>,
1003				 <&cmu_disp CLK_PCLK_SMMU_TV1X>,
1004				 <&cmu_disp CLK_SCLK_DECON_TV_VCLK>,
1005				 <&cmu_disp CLK_SCLK_DECON_TV_ECLK>,
1006				 <&cmu_disp CLK_SCLK_DSD>;
1007			clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x",
1008				      "aclk_xiu_decon0x", "pclk_smmu_decon0x",
1009				      "aclk_smmu_decon1x", "aclk_xiu_decon1x",
1010				      "pclk_smmu_decon1x", "sclk_decon_vclk",
1011				      "sclk_decon_eclk", "dsd";
1012			samsung,disp-sysreg = <&syscon_disp>;
1013			power-domains = <&pd_disp>;
1014			interrupt-names = "fifo", "vsync", "lcd_sys";
1015			interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
1016				     <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
1017				     <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
1018			status = "disabled";
1019			iommus = <&sysmmu_tv0x>, <&sysmmu_tv1x>;
1020			iommu-names = "m0", "m1";
1021		};
1022
1023		dsi: dsi@13900000 {
1024			compatible = "samsung,exynos5433-mipi-dsi";
1025			reg = <0x13900000 0xc0>;
1026			interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
1027			phys = <&mipi_phy 1>;
1028			phy-names = "dsim";
1029			clocks = <&cmu_disp CLK_PCLK_DSIM0>,
1030				<&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8>,
1031				<&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0>,
1032				<&cmu_disp CLK_SCLK_RGB_VCLK_TO_DSIM0>,
1033				<&cmu_disp CLK_SCLK_DSIM0>;
1034			clock-names = "bus_clk",
1035					"phyclk_mipidphy0_bitclkdiv8",
1036					"phyclk_mipidphy0_rxclkesc0",
1037					"sclk_rgb_vclk_to_dsim0",
1038					"sclk_mipi";
1039			power-domains = <&pd_disp>;
1040			status = "disabled";
1041			#address-cells = <1>;
1042			#size-cells = <0>;
1043
1044			ports {
1045				#address-cells = <1>;
1046				#size-cells = <0>;
1047
1048				port@0 {
1049					reg = <0>;
1050					dsi_to_mic: endpoint {
1051						remote-endpoint = <&mic_to_dsi>;
1052					};
1053				};
1054			};
1055		};
1056
1057		mic: mic@13930000 {
1058			compatible = "samsung,exynos5433-mic";
1059			reg = <0x13930000 0x48>;
1060			clocks = <&cmu_disp CLK_PCLK_MIC0>,
1061				<&cmu_disp CLK_SCLK_RGB_VCLK_TO_MIC0>;
1062			clock-names = "pclk_mic0", "sclk_rgb_vclk_to_mic0";
1063			power-domains = <&pd_disp>;
1064			samsung,disp-syscon = <&syscon_disp>;
1065			status = "disabled";
1066
1067			ports {
1068				#address-cells = <1>;
1069				#size-cells = <0>;
1070
1071				port@0 {
1072					reg = <0>;
1073					mic_to_decon: endpoint {
1074						remote-endpoint =
1075							<&decon_to_mic>;
1076					};
1077				};
1078
1079				port@1 {
1080					reg = <1>;
1081					mic_to_dsi: endpoint {
1082						remote-endpoint = <&dsi_to_mic>;
1083					};
1084				};
1085			};
1086		};
1087
1088		hdmi: hdmi@13970000 {
1089			compatible = "samsung,exynos5433-hdmi";
1090			reg = <0x13970000 0x70000>;
1091			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1092			clocks = <&cmu_disp CLK_PCLK_HDMI>,
1093				<&cmu_disp CLK_PCLK_HDMIPHY>,
1094				<&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO>,
1095				<&cmu_disp CLK_PHYCLK_HDMI_PIXEL>,
1096				<&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY>,
1097				<&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER>,
1098				<&cmu_disp CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY>,
1099				<&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER>,
1100				<&xxti>, <&cmu_disp CLK_SCLK_HDMI_SPDIF>;
1101			clock-names = "hdmi_pclk", "hdmi_i_pclk",
1102				"i_tmds_clk", "i_pixel_clk",
1103				"tmds_clko", "tmds_clko_user",
1104				"pixel_clko", "pixel_clko_user",
1105				"oscclk", "i_spdif_clk";
1106			phy = <&hdmiphy>;
1107			ddc = <&hsi2c_11>;
1108			samsung,syscon-phandle = <&pmu_system_controller>;
1109			samsung,sysreg-phandle = <&syscon_disp>;
1110			#sound-dai-cells = <0>;
1111			status = "disabled";
1112		};
1113
1114		hdmiphy: hdmiphy@13af0000 {
1115			reg = <0x13af0000 0x80>;
1116		};
1117
1118		syscon_disp: syscon@13b80000 {
1119			compatible = "samsung,exynos5433-disp-sysreg",
1120				     "samsung,exynos5433-sysreg", "syscon";
1121			reg = <0x13b80000 0x1010>;
1122		};
1123
1124		syscon_cam0: syscon@120f0000 {
1125			compatible = "samsung,exynos5433-cam0-sysreg",
1126				     "samsung,exynos5433-sysreg", "syscon";
1127			reg = <0x120f0000 0x1020>;
1128		};
1129
1130		syscon_cam1: syscon@145f0000 {
1131			compatible = "samsung,exynos5433-cam1-sysreg",
1132				     "samsung,exynos5433-sysreg", "syscon";
1133			reg = <0x145f0000 0x1038>;
1134		};
1135
1136		syscon_fsys: syscon@156f0000 {
1137			compatible = "samsung,exynos5433-fsys-sysreg",
1138				     "samsung,exynos5433-sysreg", "syscon";
1139			reg = <0x156f0000 0x1044>;
1140		};
1141
1142		gsc_0: video-scaler@13c00000 {
1143			compatible = "samsung,exynos5433-gsc";
1144			reg = <0x13c00000 0x1000>;
1145			interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
1146			clock-names = "pclk", "aclk", "aclk_xiu",
1147				      "aclk_gsclbend", "gsd";
1148			clocks = <&cmu_gscl CLK_PCLK_GSCL0>,
1149				 <&cmu_gscl CLK_ACLK_GSCL0>,
1150				 <&cmu_gscl CLK_ACLK_XIU_GSCLX>,
1151				 <&cmu_gscl CLK_ACLK_GSCLBEND_333>,
1152				 <&cmu_gscl CLK_ACLK_GSD>;
1153			iommus = <&sysmmu_gscl0>;
1154			power-domains = <&pd_gscl>;
1155		};
1156
1157		gsc_1: video-scaler@13c10000 {
1158			compatible = "samsung,exynos5433-gsc";
1159			reg = <0x13c10000 0x1000>;
1160			interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
1161			clock-names = "pclk", "aclk", "aclk_xiu",
1162				      "aclk_gsclbend", "gsd";
1163			clocks = <&cmu_gscl CLK_PCLK_GSCL1>,
1164				 <&cmu_gscl CLK_ACLK_GSCL1>,
1165				 <&cmu_gscl CLK_ACLK_XIU_GSCLX>,
1166				 <&cmu_gscl CLK_ACLK_GSCLBEND_333>,
1167				 <&cmu_gscl CLK_ACLK_GSD>;
1168			iommus = <&sysmmu_gscl1>;
1169			power-domains = <&pd_gscl>;
1170		};
1171
1172		gsc_2: video-scaler@13c20000 {
1173			compatible = "samsung,exynos5433-gsc";
1174			reg = <0x13c20000 0x1000>;
1175			interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
1176			clock-names = "pclk", "aclk", "aclk_xiu",
1177				      "aclk_gsclbend", "gsd";
1178			clocks = <&cmu_gscl CLK_PCLK_GSCL2>,
1179				 <&cmu_gscl CLK_ACLK_GSCL2>,
1180				 <&cmu_gscl CLK_ACLK_XIU_GSCLX>,
1181				 <&cmu_gscl CLK_ACLK_GSCLBEND_333>,
1182				 <&cmu_gscl CLK_ACLK_GSD>;
1183			iommus = <&sysmmu_gscl2>;
1184			power-domains = <&pd_gscl>;
1185		};
1186
1187		gpu: gpu@14ac0000 {
1188			compatible = "samsung,exynos5433-mali", "arm,mali-t760";
1189			reg = <0x14ac0000 0x5000>;
1190			interrupts = <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1191				     <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1192				     <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>;
1193			interrupt-names = "job", "mmu", "gpu";
1194			clocks = <&cmu_g3d CLK_ACLK_G3D>;
1195			clock-names = "core";
1196			power-domains = <&pd_g3d>;
1197			operating-points-v2 = <&gpu_opp_table>;
1198			status = "disabled";
1199
1200			gpu_opp_table: opp-table {
1201				compatible = "operating-points-v2";
1202
1203				opp-160000000 {
1204					opp-hz = /bits/ 64 <160000000>;
1205					opp-microvolt = <1000000>;
1206				};
1207				opp-267000000 {
1208					opp-hz = /bits/ 64 <267000000>;
1209					opp-microvolt = <1000000>;
1210				};
1211				opp-350000000 {
1212					opp-hz = /bits/ 64 <350000000>;
1213					opp-microvolt = <1025000>;
1214				};
1215				opp-420000000 {
1216					opp-hz = /bits/ 64 <420000000>;
1217					opp-microvolt = <1025000>;
1218				};
1219				opp-500000000 {
1220					opp-hz = /bits/ 64 <500000000>;
1221					opp-microvolt = <1075000>;
1222				};
1223				opp-550000000 {
1224					opp-hz = /bits/ 64 <550000000>;
1225					opp-microvolt = <1125000>;
1226				};
1227				opp-600000000 {
1228					opp-hz = /bits/ 64 <600000000>;
1229					opp-microvolt = <1150000>;
1230				};
1231				opp-700000000 {
1232					opp-hz = /bits/ 64 <700000000>;
1233					opp-microvolt = <1150000>;
1234				};
1235			};
1236		};
1237
1238		scaler_0: scaler@15000000 {
1239			compatible = "samsung,exynos5433-scaler";
1240			reg = <0x15000000 0x1294>;
1241			interrupts = <0 402 IRQ_TYPE_LEVEL_HIGH>;
1242			clock-names = "pclk", "aclk", "aclk_xiu";
1243			clocks = <&cmu_mscl CLK_PCLK_M2MSCALER0>,
1244				 <&cmu_mscl CLK_ACLK_M2MSCALER0>,
1245				 <&cmu_mscl CLK_ACLK_XIU_MSCLX>;
1246			iommus = <&sysmmu_scaler_0>;
1247			power-domains = <&pd_mscl>;
1248		};
1249
1250		scaler_1: scaler@15010000 {
1251			compatible = "samsung,exynos5433-scaler";
1252			reg = <0x15010000 0x1294>;
1253			interrupts = <0 403 IRQ_TYPE_LEVEL_HIGH>;
1254			clock-names = "pclk", "aclk", "aclk_xiu";
1255			clocks = <&cmu_mscl CLK_PCLK_M2MSCALER1>,
1256				 <&cmu_mscl CLK_ACLK_M2MSCALER1>,
1257				 <&cmu_mscl CLK_ACLK_XIU_MSCLX>;
1258			iommus = <&sysmmu_scaler_1>;
1259			power-domains = <&pd_mscl>;
1260		};
1261
1262		jpeg: codec@15020000 {
1263			compatible = "samsung,exynos5433-jpeg";
1264			reg = <0x15020000 0x10000>;
1265			interrupts = <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>;
1266			clock-names = "pclk", "aclk", "aclk_xiu", "sclk";
1267			clocks = <&cmu_mscl CLK_PCLK_JPEG>,
1268				 <&cmu_mscl CLK_ACLK_JPEG>,
1269				 <&cmu_mscl CLK_ACLK_XIU_MSCLX>,
1270				 <&cmu_mscl CLK_SCLK_JPEG>;
1271			iommus = <&sysmmu_jpeg>;
1272			power-domains = <&pd_mscl>;
1273		};
1274
1275		mfc: codec@152e0000 {
1276			compatible = "samsung,exynos5433-mfc";
1277			reg = <0x152e0000 0x10000>;
1278			interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1279			clock-names = "pclk", "aclk", "aclk_xiu";
1280			clocks = <&cmu_mfc CLK_PCLK_MFC>,
1281				 <&cmu_mfc CLK_ACLK_MFC>,
1282				 <&cmu_mfc CLK_ACLK_XIU_MFCX>;
1283			iommus = <&sysmmu_mfc_0>, <&sysmmu_mfc_1>;
1284			iommu-names = "left", "right";
1285			power-domains = <&pd_mfc>;
1286		};
1287
1288		sysmmu_decon0x: sysmmu@13a00000 {
1289			compatible = "samsung,exynos-sysmmu";
1290			reg = <0x13a00000 0x1000>;
1291			interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
1292			clock-names = "aclk", "pclk";
1293			clocks = <&cmu_disp CLK_ACLK_SMMU_DECON0X>,
1294				<&cmu_disp CLK_PCLK_SMMU_DECON0X>;
1295			power-domains = <&pd_disp>;
1296			#iommu-cells = <0>;
1297		};
1298
1299		sysmmu_decon1x: sysmmu@13a10000 {
1300			compatible = "samsung,exynos-sysmmu";
1301			reg = <0x13a10000 0x1000>;
1302			interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
1303			clock-names = "aclk", "pclk";
1304			clocks = <&cmu_disp CLK_ACLK_SMMU_DECON1X>,
1305				<&cmu_disp CLK_PCLK_SMMU_DECON1X>;
1306			#iommu-cells = <0>;
1307			power-domains = <&pd_disp>;
1308		};
1309
1310		sysmmu_tv0x: sysmmu@13a20000 {
1311			compatible = "samsung,exynos-sysmmu";
1312			reg = <0x13a20000 0x1000>;
1313			interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
1314			clock-names = "aclk", "pclk";
1315			clocks = <&cmu_disp CLK_ACLK_SMMU_TV0X>,
1316				<&cmu_disp CLK_PCLK_SMMU_TV0X>;
1317			#iommu-cells = <0>;
1318			power-domains = <&pd_disp>;
1319		};
1320
1321		sysmmu_tv1x: sysmmu@13a30000 {
1322			compatible = "samsung,exynos-sysmmu";
1323			reg = <0x13a30000 0x1000>;
1324			interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
1325			clock-names = "aclk", "pclk";
1326			clocks = <&cmu_disp CLK_ACLK_SMMU_TV1X>,
1327				<&cmu_disp CLK_PCLK_SMMU_TV1X>;
1328			#iommu-cells = <0>;
1329			power-domains = <&pd_disp>;
1330		};
1331
1332		sysmmu_gscl0: sysmmu@13c80000 {
1333			compatible = "samsung,exynos-sysmmu";
1334			reg = <0x13c80000 0x1000>;
1335			interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
1336			clock-names = "aclk", "pclk";
1337			clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL0>,
1338				 <&cmu_gscl CLK_PCLK_SMMU_GSCL0>;
1339			#iommu-cells = <0>;
1340			power-domains = <&pd_gscl>;
1341		};
1342
1343		sysmmu_gscl1: sysmmu@13c90000 {
1344			compatible = "samsung,exynos-sysmmu";
1345			reg = <0x13c90000 0x1000>;
1346			interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
1347			clock-names = "aclk", "pclk";
1348			clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL1>,
1349				 <&cmu_gscl CLK_PCLK_SMMU_GSCL1>;
1350			#iommu-cells = <0>;
1351			power-domains = <&pd_gscl>;
1352		};
1353
1354		sysmmu_gscl2: sysmmu@13ca0000 {
1355			compatible = "samsung,exynos-sysmmu";
1356			reg = <0x13ca0000 0x1000>;
1357			interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
1358			clock-names = "aclk", "pclk";
1359			clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL2>,
1360				 <&cmu_gscl CLK_PCLK_SMMU_GSCL2>;
1361			#iommu-cells = <0>;
1362			power-domains = <&pd_gscl>;
1363		};
1364
1365		sysmmu_scaler_0: sysmmu@15040000 {
1366			compatible = "samsung,exynos-sysmmu";
1367			reg = <0x15040000 0x1000>;
1368			interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
1369			clock-names = "aclk", "pclk";
1370			clocks = <&cmu_mscl CLK_ACLK_SMMU_M2MSCALER0>,
1371				<&cmu_mscl CLK_PCLK_SMMU_M2MSCALER0>;
1372			#iommu-cells = <0>;
1373			power-domains = <&pd_mscl>;
1374		};
1375
1376		sysmmu_scaler_1: sysmmu@15050000 {
1377			compatible = "samsung,exynos-sysmmu";
1378			reg = <0x15050000 0x1000>;
1379			interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>;
1380			clock-names = "aclk", "pclk";
1381			clocks = <&cmu_mscl CLK_ACLK_SMMU_M2MSCALER1>,
1382				<&cmu_mscl CLK_PCLK_SMMU_M2MSCALER1>;
1383			#iommu-cells = <0>;
1384			power-domains = <&pd_mscl>;
1385		};
1386
1387		sysmmu_jpeg: sysmmu@15060000 {
1388			compatible = "samsung,exynos-sysmmu";
1389			reg = <0x15060000 0x1000>;
1390			interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
1391			clock-names = "aclk", "pclk";
1392			clocks = <&cmu_mscl CLK_ACLK_SMMU_JPEG>,
1393				<&cmu_mscl CLK_PCLK_SMMU_JPEG>;
1394			#iommu-cells = <0>;
1395			power-domains = <&pd_mscl>;
1396		};
1397
1398		sysmmu_mfc_0: sysmmu@15200000 {
1399			compatible = "samsung,exynos-sysmmu";
1400			reg = <0x15200000 0x1000>;
1401			interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1402			clock-names = "aclk", "pclk";
1403			clocks = <&cmu_mfc CLK_ACLK_SMMU_MFC_0>,
1404				<&cmu_mfc CLK_PCLK_SMMU_MFC_0>;
1405			#iommu-cells = <0>;
1406			power-domains = <&pd_mfc>;
1407		};
1408
1409		sysmmu_mfc_1: sysmmu@15210000 {
1410			compatible = "samsung,exynos-sysmmu";
1411			reg = <0x15210000 0x1000>;
1412			interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1413			clock-names = "aclk", "pclk";
1414			clocks = <&cmu_mfc CLK_ACLK_SMMU_MFC_1>,
1415				<&cmu_mfc CLK_PCLK_SMMU_MFC_1>;
1416			#iommu-cells = <0>;
1417			power-domains = <&pd_mfc>;
1418		};
1419
1420		serial_0: serial@14c10000 {
1421			compatible = "samsung,exynos5433-uart";
1422			reg = <0x14c10000 0x100>;
1423			interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
1424			clocks = <&cmu_peric CLK_PCLK_UART0>,
1425				<&cmu_peric CLK_SCLK_UART0>;
1426			clock-names = "uart", "clk_uart_baud0";
1427			pinctrl-names = "default";
1428			pinctrl-0 = <&uart0_bus>;
1429			status = "disabled";
1430		};
1431
1432		serial_1: serial@14c20000 {
1433			compatible = "samsung,exynos5433-uart";
1434			reg = <0x14c20000 0x100>;
1435			interrupts = <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
1436			clocks = <&cmu_peric CLK_PCLK_UART1>,
1437				<&cmu_peric CLK_SCLK_UART1>;
1438			clock-names = "uart", "clk_uart_baud0";
1439			pinctrl-names = "default";
1440			pinctrl-0 = <&uart1_bus>;
1441			status = "disabled";
1442		};
1443
1444		serial_2: serial@14c30000 {
1445			compatible = "samsung,exynos5433-uart";
1446			reg = <0x14c30000 0x100>;
1447			interrupts = <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>;
1448			clocks = <&cmu_peric CLK_PCLK_UART2>,
1449				<&cmu_peric CLK_SCLK_UART2>;
1450			clock-names = "uart", "clk_uart_baud0";
1451			pinctrl-names = "default";
1452			pinctrl-0 = <&uart2_bus>;
1453			status = "disabled";
1454		};
1455
1456		spi_0: spi@14d20000 {
1457			compatible = "samsung,exynos5433-spi";
1458			reg = <0x14d20000 0x100>;
1459			interrupts = <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>;
1460			dmas = <&pdma0 9>, <&pdma0 8>;
1461			dma-names = "tx", "rx";
1462			#address-cells = <1>;
1463			#size-cells = <0>;
1464			clocks = <&cmu_peric CLK_PCLK_SPI0>,
1465				<&cmu_peric CLK_SCLK_SPI0>,
1466				<&cmu_peric CLK_SCLK_IOCLK_SPI0>;
1467			clock-names = "spi", "spi_busclk0", "spi_ioclk";
1468			samsung,spi-src-clk = <0>;
1469			pinctrl-names = "default";
1470			pinctrl-0 = <&spi0_bus>;
1471			num-cs = <1>;
1472			fifo-depth = <256>;
1473			status = "disabled";
1474		};
1475
1476		spi_1: spi@14d30000 {
1477			compatible = "samsung,exynos5433-spi";
1478			reg = <0x14d30000 0x100>;
1479			interrupts = <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>;
1480			dmas = <&pdma0 11>, <&pdma0 10>;
1481			dma-names = "tx", "rx";
1482			#address-cells = <1>;
1483			#size-cells = <0>;
1484			clocks = <&cmu_peric CLK_PCLK_SPI1>,
1485				<&cmu_peric CLK_SCLK_SPI1>,
1486				<&cmu_peric CLK_SCLK_IOCLK_SPI1>;
1487			clock-names = "spi", "spi_busclk0", "spi_ioclk";
1488			samsung,spi-src-clk = <0>;
1489			pinctrl-names = "default";
1490			pinctrl-0 = <&spi1_bus>;
1491			num-cs = <1>;
1492			fifo-depth = <64>;
1493			status = "disabled";
1494		};
1495
1496		spi_2: spi@14d40000 {
1497			compatible = "samsung,exynos5433-spi";
1498			reg = <0x14d40000 0x100>;
1499			interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>;
1500			dmas = <&pdma0 13>, <&pdma0 12>;
1501			dma-names = "tx", "rx";
1502			#address-cells = <1>;
1503			#size-cells = <0>;
1504			clocks = <&cmu_peric CLK_PCLK_SPI2>,
1505				<&cmu_peric CLK_SCLK_SPI2>,
1506				<&cmu_peric CLK_SCLK_IOCLK_SPI2>;
1507			clock-names = "spi", "spi_busclk0", "spi_ioclk";
1508			samsung,spi-src-clk = <0>;
1509			pinctrl-names = "default";
1510			pinctrl-0 = <&spi2_bus>;
1511			num-cs = <1>;
1512			fifo-depth = <64>;
1513			status = "disabled";
1514		};
1515
1516		spi_3: spi@14d50000 {
1517			compatible = "samsung,exynos5433-spi";
1518			reg = <0x14d50000 0x100>;
1519			interrupts = <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>;
1520			dmas = <&pdma0 23>, <&pdma0 22>;
1521			dma-names = "tx", "rx";
1522			#address-cells = <1>;
1523			#size-cells = <0>;
1524			clocks = <&cmu_peric CLK_PCLK_SPI3>,
1525				<&cmu_peric CLK_SCLK_SPI3>,
1526				<&cmu_peric CLK_SCLK_IOCLK_SPI3>;
1527			clock-names = "spi", "spi_busclk0", "spi_ioclk";
1528			samsung,spi-src-clk = <0>;
1529			pinctrl-names = "default";
1530			pinctrl-0 = <&spi3_bus>;
1531			num-cs = <1>;
1532			fifo-depth = <64>;
1533			status = "disabled";
1534		};
1535
1536		spi_4: spi@14d00000 {
1537			compatible = "samsung,exynos5433-spi";
1538			reg = <0x14d00000 0x100>;
1539			interrupts = <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
1540			dmas = <&pdma0 25>, <&pdma0 24>;
1541			dma-names = "tx", "rx";
1542			#address-cells = <1>;
1543			#size-cells = <0>;
1544			clocks = <&cmu_peric CLK_PCLK_SPI4>,
1545				<&cmu_peric CLK_SCLK_SPI4>,
1546				<&cmu_peric CLK_SCLK_IOCLK_SPI4>;
1547			clock-names = "spi", "spi_busclk0", "spi_ioclk";
1548			samsung,spi-src-clk = <0>;
1549			pinctrl-names = "default";
1550			pinctrl-0 = <&spi4_bus>;
1551			num-cs = <1>;
1552			fifo-depth = <64>;
1553			status = "disabled";
1554		};
1555
1556		adc: adc@14d10000 {
1557			compatible = "samsung,exynos5433-adc", "samsung,exynos7-adc";
1558			reg = <0x14d10000 0x100>;
1559			interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>;
1560			clock-names = "adc";
1561			clocks = <&cmu_peric CLK_PCLK_ADCIF>;
1562			#io-channel-cells = <1>;
1563			status = "disabled";
1564		};
1565
1566		i2s1: i2s@14d60000 {
1567			compatible = "samsung,exynos5433-i2s", "samsung,exynos7-i2s";
1568			reg = <0x14d60000 0x100>;
1569			dmas = <&pdma0 31>, <&pdma0 30>;
1570			dma-names = "tx", "rx";
1571			interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>;
1572			clocks = <&cmu_peric CLK_PCLK_I2S1>,
1573				 <&cmu_peric CLK_PCLK_I2S1>,
1574				 <&cmu_peric CLK_SCLK_I2S1>;
1575			clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
1576			#clock-cells = <1>;
1577			#sound-dai-cells = <1>;
1578			status = "disabled";
1579		};
1580
1581		pwm: pwm@14dd0000 {
1582			compatible = "samsung,exynos5433-pwm", "samsung,exynos4210-pwm";
1583			reg = <0x14dd0000 0x100>;
1584			interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
1585				     <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
1586				     <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
1587				     <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
1588				     <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
1589			samsung,pwm-outputs = <0>, <1>, <2>, <3>;
1590			clocks = <&cmu_peric CLK_PCLK_PWM>;
1591			clock-names = "timers";
1592			#pwm-cells = <3>;
1593			status = "disabled";
1594		};
1595
1596		hsi2c_0: i2c@14e40000 {
1597			compatible = "samsung,exynos5433-hsi2c",
1598				     "samsung,exynos7-hsi2c";
1599			reg = <0x14e40000 0x1000>;
1600			interrupts = <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>;
1601			#address-cells = <1>;
1602			#size-cells = <0>;
1603			pinctrl-names = "default";
1604			pinctrl-0 = <&hs_i2c0_bus>;
1605			clocks = <&cmu_peric CLK_PCLK_HSI2C0>;
1606			clock-names = "hsi2c";
1607			status = "disabled";
1608		};
1609
1610		hsi2c_1: i2c@14e50000 {
1611			compatible = "samsung,exynos5433-hsi2c",
1612				     "samsung,exynos7-hsi2c";
1613			reg = <0x14e50000 0x1000>;
1614			interrupts = <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
1615			#address-cells = <1>;
1616			#size-cells = <0>;
1617			pinctrl-names = "default";
1618			pinctrl-0 = <&hs_i2c1_bus>;
1619			clocks = <&cmu_peric CLK_PCLK_HSI2C1>;
1620			clock-names = "hsi2c";
1621			status = "disabled";
1622		};
1623
1624		hsi2c_2: i2c@14e60000 {
1625			compatible = "samsung,exynos5433-hsi2c",
1626				     "samsung,exynos7-hsi2c";
1627			reg = <0x14e60000 0x1000>;
1628			interrupts = <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
1629			#address-cells = <1>;
1630			#size-cells = <0>;
1631			pinctrl-names = "default";
1632			pinctrl-0 = <&hs_i2c2_bus>;
1633			clocks = <&cmu_peric CLK_PCLK_HSI2C2>;
1634			clock-names = "hsi2c";
1635			status = "disabled";
1636		};
1637
1638		hsi2c_3: i2c@14e70000 {
1639			compatible = "samsung,exynos5433-hsi2c",
1640				     "samsung,exynos7-hsi2c";
1641			reg = <0x14e70000 0x1000>;
1642			interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>;
1643			#address-cells = <1>;
1644			#size-cells = <0>;
1645			pinctrl-names = "default";
1646			pinctrl-0 = <&hs_i2c3_bus>;
1647			clocks = <&cmu_peric CLK_PCLK_HSI2C3>;
1648			clock-names = "hsi2c";
1649			status = "disabled";
1650		};
1651
1652		hsi2c_4: i2c@14ec0000 {
1653			compatible = "samsung,exynos5433-hsi2c",
1654				     "samsung,exynos7-hsi2c";
1655			reg = <0x14ec0000 0x1000>;
1656			interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
1657			#address-cells = <1>;
1658			#size-cells = <0>;
1659			pinctrl-names = "default";
1660			pinctrl-0 = <&hs_i2c4_bus>;
1661			clocks = <&cmu_peric CLK_PCLK_HSI2C4>;
1662			clock-names = "hsi2c";
1663			status = "disabled";
1664		};
1665
1666		hsi2c_5: i2c@14ed0000 {
1667			compatible = "samsung,exynos5433-hsi2c",
1668				     "samsung,exynos7-hsi2c";
1669			reg = <0x14ed0000 0x1000>;
1670			interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
1671			#address-cells = <1>;
1672			#size-cells = <0>;
1673			pinctrl-names = "default";
1674			pinctrl-0 = <&hs_i2c5_bus>;
1675			clocks = <&cmu_peric CLK_PCLK_HSI2C5>;
1676			clock-names = "hsi2c";
1677			status = "disabled";
1678		};
1679
1680		hsi2c_6: i2c@14ee0000 {
1681			compatible = "samsung,exynos5433-hsi2c",
1682				     "samsung,exynos7-hsi2c";
1683			reg = <0x14ee0000 0x1000>;
1684			interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>;
1685			#address-cells = <1>;
1686			#size-cells = <0>;
1687			pinctrl-names = "default";
1688			pinctrl-0 = <&hs_i2c6_bus>;
1689			clocks = <&cmu_peric CLK_PCLK_HSI2C6>;
1690			clock-names = "hsi2c";
1691			status = "disabled";
1692		};
1693
1694		hsi2c_7: i2c@14ef0000 {
1695			compatible = "samsung,exynos5433-hsi2c",
1696				     "samsung,exynos7-hsi2c";
1697			reg = <0x14ef0000 0x1000>;
1698			interrupts = <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>;
1699			#address-cells = <1>;
1700			#size-cells = <0>;
1701			pinctrl-names = "default";
1702			pinctrl-0 = <&hs_i2c7_bus>;
1703			clocks = <&cmu_peric CLK_PCLK_HSI2C7>;
1704			clock-names = "hsi2c";
1705			status = "disabled";
1706		};
1707
1708		hsi2c_8: i2c@14d90000 {
1709			compatible = "samsung,exynos5433-hsi2c",
1710				     "samsung,exynos7-hsi2c";
1711			reg = <0x14d90000 0x1000>;
1712			interrupts = <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>;
1713			#address-cells = <1>;
1714			#size-cells = <0>;
1715			pinctrl-names = "default";
1716			pinctrl-0 = <&hs_i2c8_bus>;
1717			clocks = <&cmu_peric CLK_PCLK_HSI2C8>;
1718			clock-names = "hsi2c";
1719			status = "disabled";
1720		};
1721
1722		hsi2c_9: i2c@14da0000 {
1723			compatible = "samsung,exynos5433-hsi2c",
1724				     "samsung,exynos7-hsi2c";
1725			reg = <0x14da0000 0x1000>;
1726			interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
1727			#address-cells = <1>;
1728			#size-cells = <0>;
1729			pinctrl-names = "default";
1730			pinctrl-0 = <&hs_i2c9_bus>;
1731			clocks = <&cmu_peric CLK_PCLK_HSI2C9>;
1732			clock-names = "hsi2c";
1733			status = "disabled";
1734		};
1735
1736		hsi2c_10: i2c@14de0000 {
1737			compatible = "samsung,exynos5433-hsi2c",
1738				     "samsung,exynos7-hsi2c";
1739			reg = <0x14de0000 0x1000>;
1740			interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
1741			#address-cells = <1>;
1742			#size-cells = <0>;
1743			pinctrl-names = "default";
1744			pinctrl-0 = <&hs_i2c10_bus>;
1745			clocks = <&cmu_peric CLK_PCLK_HSI2C10>;
1746			clock-names = "hsi2c";
1747			status = "disabled";
1748		};
1749
1750		hsi2c_11: i2c@14df0000 {
1751			compatible = "samsung,exynos5433-hsi2c",
1752				     "samsung,exynos7-hsi2c";
1753			reg = <0x14df0000 0x1000>;
1754			interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>;
1755			#address-cells = <1>;
1756			#size-cells = <0>;
1757			pinctrl-names = "default";
1758			pinctrl-0 = <&hs_i2c11_bus>;
1759			clocks = <&cmu_peric CLK_PCLK_HSI2C11>;
1760			clock-names = "hsi2c";
1761			status = "disabled";
1762		};
1763
1764		usbdrd30: usb@15400000 {
1765			compatible = "samsung,exynos5433-dwusb3";
1766			clocks = <&cmu_fsys CLK_ACLK_USBDRD30>,
1767				<&cmu_fsys CLK_SCLK_USBDRD30>,
1768				<&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK>,
1769				<&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK>;
1770			clock-names = "aclk", "susp_clk", "phyclk", "pipe_pclk";
1771			#address-cells = <1>;
1772			#size-cells = <1>;
1773			ranges = <0x0 0x15400000 0x10000>;
1774			status = "disabled";
1775
1776			usbdrd_dwc3: usb@0 {
1777				compatible = "snps,dwc3";
1778				clocks = <&cmu_fsys CLK_SCLK_USBDRD30>,
1779					<&cmu_fsys CLK_ACLK_USBDRD30>,
1780					<&cmu_fsys CLK_SCLK_USBDRD30>;
1781				clock-names = "ref", "bus_early", "suspend";
1782				reg = <0x0 0x10000>;
1783				interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
1784				phys = <&usbdrd30_phy 0>, <&usbdrd30_phy 1>;
1785				phy-names = "usb2-phy", "usb3-phy";
1786			};
1787		};
1788
1789		usbdrd30_phy: phy@15500000 {
1790			compatible = "samsung,exynos5433-usbdrd-phy";
1791			reg = <0x15500000 0x100>;
1792			clocks = <&cmu_fsys CLK_ACLK_USBDRD30>, <&xxti>,
1793				<&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK>,
1794				<&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK>,
1795				<&cmu_fsys CLK_SCLK_USBDRD30>;
1796			clock-names = "phy", "ref", "phy_utmi", "phy_pipe",
1797					"itp";
1798			#phy-cells = <1>;
1799			samsung,pmu-syscon = <&pmu_system_controller>;
1800			status = "disabled";
1801		};
1802
1803		usbhost30_phy: phy@15580000 {
1804			compatible = "samsung,exynos5433-usbdrd-phy";
1805			reg = <0x15580000 0x100>;
1806			clocks = <&cmu_fsys CLK_ACLK_USBHOST30>, <&xxti>,
1807				<&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK>,
1808				<&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK>,
1809				<&cmu_fsys CLK_SCLK_USBHOST30>;
1810			clock-names = "phy", "ref", "phy_utmi", "phy_pipe",
1811					"itp";
1812			#phy-cells = <1>;
1813			samsung,pmu-syscon = <&pmu_system_controller>;
1814			status = "disabled";
1815		};
1816
1817		usbhost30: usb@15a00000 {
1818			compatible = "samsung,exynos5433-dwusb3";
1819			clocks = <&cmu_fsys CLK_ACLK_USBHOST30>,
1820				<&cmu_fsys CLK_SCLK_USBHOST30>,
1821				<&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK>,
1822				<&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK>;
1823			clock-names = "aclk", "susp_clk", "phyclk", "pipe_pclk";
1824			#address-cells = <1>;
1825			#size-cells = <1>;
1826			ranges = <0x0 0x15a00000 0x10000>;
1827			status = "disabled";
1828
1829			usbhost_dwc3: usb@0 {
1830				compatible = "snps,dwc3";
1831				clocks = <&cmu_fsys CLK_SCLK_USBHOST30>,
1832					<&cmu_fsys CLK_ACLK_USBHOST30>,
1833					<&cmu_fsys CLK_SCLK_USBHOST30>;
1834				clock-names = "ref", "bus_early", "suspend";
1835				reg = <0x0 0x10000>;
1836				interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
1837				phys = <&usbhost30_phy 0>, <&usbhost30_phy 1>;
1838				phy-names = "usb2-phy", "usb3-phy";
1839			};
1840		};
1841
1842		mshc_0: mmc@15540000 {
1843			compatible = "samsung,exynos5433-dw-mshc-smu",
1844				     "samsung,exynos7-dw-mshc-smu";
1845			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1846			#address-cells = <1>;
1847			#size-cells = <0>;
1848			reg = <0x15540000 0x2000>;
1849			clocks = <&cmu_fsys CLK_ACLK_MMC0>,
1850				<&cmu_fsys CLK_SCLK_MMC0>;
1851			clock-names = "biu", "ciu";
1852			fifo-depth = <0x40>;
1853			status = "disabled";
1854		};
1855
1856		mshc_1: mmc@15550000 {
1857			compatible = "samsung,exynos5433-dw-mshc-smu",
1858				     "samsung,exynos7-dw-mshc-smu";
1859			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1860			#address-cells = <1>;
1861			#size-cells = <0>;
1862			reg = <0x15550000 0x2000>;
1863			clocks = <&cmu_fsys CLK_ACLK_MMC1>,
1864				<&cmu_fsys CLK_SCLK_MMC1>;
1865			clock-names = "biu", "ciu";
1866			fifo-depth = <0x40>;
1867			status = "disabled";
1868		};
1869
1870		mshc_2: mmc@15560000 {
1871			compatible = "samsung,exynos5433-dw-mshc-smu",
1872				     "samsung,exynos7-dw-mshc-smu";
1873			interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
1874			#address-cells = <1>;
1875			#size-cells = <0>;
1876			reg = <0x15560000 0x2000>;
1877			clocks = <&cmu_fsys CLK_ACLK_MMC2>,
1878				<&cmu_fsys CLK_SCLK_MMC2>;
1879			clock-names = "biu", "ciu";
1880			fifo-depth = <0x40>;
1881			status = "disabled";
1882		};
1883
1884		pdma0: dma-controller@15610000 {
1885			compatible = "arm,pl330", "arm,primecell";
1886			reg = <0x15610000 0x1000>;
1887			interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
1888			clocks = <&cmu_fsys CLK_PDMA0>;
1889			clock-names = "apb_pclk";
1890			#dma-cells = <1>;
1891		};
1892
1893		pdma1: dma-controller@15600000 {
1894			compatible = "arm,pl330", "arm,primecell";
1895			reg = <0x15600000 0x1000>;
1896			interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
1897			clocks = <&cmu_fsys CLK_PDMA1>;
1898			clock-names = "apb_pclk";
1899			#dma-cells = <1>;
1900		};
1901
1902		audio-subsystem@11400000 {
1903			compatible = "samsung,exynos5433-lpass";
1904			reg = <0x11400000 0x100>, <0x11500000 0x08>;
1905			clocks = <&cmu_aud CLK_PCLK_SFR0_CTRL>;
1906			clock-names = "sfr0_ctrl";
1907			power-domains = <&pd_aud>;
1908			#address-cells = <1>;
1909			#size-cells = <1>;
1910			ranges;
1911
1912			adma: dma-controller@11420000 {
1913				compatible = "arm,pl330", "arm,primecell";
1914				reg = <0x11420000 0x1000>;
1915				interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1916				clocks = <&cmu_aud CLK_ACLK_DMAC>;
1917				clock-names = "apb_pclk";
1918				#dma-cells = <1>;
1919				power-domains = <&pd_aud>;
1920			};
1921
1922			i2s0: i2s@11440000 {
1923				compatible = "samsung,exynos5433-i2s",
1924					     "samsung,exynos7-i2s";
1925				reg = <0x11440000 0x100>;
1926				dmas = <&adma 0>, <&adma 2>;
1927				dma-names = "tx", "rx";
1928				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1929				#address-cells = <1>;
1930				#size-cells = <0>;
1931				clocks = <&cmu_aud CLK_PCLK_AUD_I2S>,
1932					<&cmu_aud CLK_SCLK_AUD_I2S>,
1933					<&cmu_aud CLK_SCLK_I2S_BCLK>;
1934				clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
1935				#clock-cells = <1>;
1936				pinctrl-names = "default";
1937				pinctrl-0 = <&i2s0_bus>;
1938				power-domains = <&pd_aud>;
1939				#sound-dai-cells = <1>;
1940				status = "disabled";
1941			};
1942
1943			serial_3: serial@11460000 {
1944				compatible = "samsung,exynos5433-uart";
1945				reg = <0x11460000 0x100>;
1946				interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
1947				clocks = <&cmu_aud CLK_PCLK_AUD_UART>,
1948					<&cmu_aud CLK_SCLK_AUD_UART>;
1949				clock-names = "uart", "clk_uart_baud0";
1950				pinctrl-names = "default";
1951				pinctrl-0 = <&uart_aud_bus>;
1952				power-domains = <&pd_aud>;
1953				status = "disabled";
1954			};
1955		};
1956
1957		pcie_phy: pcie-phy@15680000 {
1958			compatible = "samsung,exynos5433-pcie-phy";
1959			reg = <0x15680000 0x1000>;
1960			samsung,pmu-syscon = <&pmu_system_controller>;
1961			samsung,fsys-sysreg = <&syscon_fsys>;
1962			#phy-cells = <0>;
1963			status = "disabled";
1964		};
1965
1966		pcie: pcie@15700000 {
1967			compatible = "samsung,exynos5433-pcie";
1968			reg = <0x15700000 0x1000>, <0x156b0000 0x1000>,
1969			      <0x0c000000 0x1000>;
1970			reg-names = "dbi", "elbi", "config";
1971			#address-cells = <3>;
1972			#size-cells = <2>;
1973			#interrupt-cells = <1>;
1974			device_type = "pci";
1975			interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
1976			clocks = <&cmu_fsys CLK_PCIE>,
1977				 <&cmu_fsys CLK_PCLK_PCIE_PHY>;
1978			clock-names = "pcie", "pcie_bus";
1979			num-lanes = <1>;
1980			num-viewport = <3>;
1981			bus-range = <0x00 0xff>;
1982			phys = <&pcie_phy>;
1983			ranges = <0x81000000 0 0	  0x0c001000 0 0x00010000>,
1984				 <0x82000000 0 0x0c011000 0x0c011000 0 0x03feefff>;
1985			status = "disabled";
1986		};
1987	};
1988
1989	timer: timer {
1990		compatible = "arm,armv8-timer";
1991		interrupts = <GIC_PPI 13
1992				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
1993			<GIC_PPI 14
1994				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
1995			<GIC_PPI 11
1996				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
1997			<GIC_PPI 10
1998				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1999	};
2000};
2001
2002#include "exynos5433-bus.dtsi"
2003#include "exynos5433-pinctrl.dtsi"
2004#include "exynos5433-tmu.dtsi"