artpec8-pinctrl.dtsi

  1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2/*
  3 * Axis ARTPEC-8 SoC pin-mux and pin-config device tree source
  4 *
  5 * Copyright (c) 2025 Samsung Electronics Co., Ltd.
  6 *             https://www.samsung.com
  7 * Copyright (c) 2025  Axis Communications AB.
  8 *             https://www.axis.com
  9 */
 10
 11#include "artpec-pinctrl.h"
 12
 13&pinctrl_fsys {
 14	gpe0: gpe0-gpio-bank {
 15		gpio-controller;
 16		#gpio-cells = <2>;
 17		interrupt-controller;
 18		#interrupt-cells = <2>;
 19	};
 20
 21	gpe1: gpe1-gpio-bank {
 22		gpio-controller;
 23		#gpio-cells = <2>;
 24		interrupt-controller;
 25		#interrupt-cells = <2>;
 26	};
 27
 28	gpe2: gpe2-gpio-bank {
 29		gpio-controller;
 30		#gpio-cells = <2>;
 31		interrupt-controller;
 32		#interrupt-cells = <2>;
 33	};
 34
 35	gpf0: gpf0-gpio-bank {
 36		gpio-controller;
 37		#gpio-cells = <2>;
 38		interrupt-controller;
 39		#interrupt-cells = <2>;
 40	};
 41
 42	gpf1: gpf1-gpio-bank {
 43		gpio-controller;
 44		#gpio-cells = <2>;
 45		interrupt-controller;
 46		#interrupt-cells = <2>;
 47	};
 48
 49	gpf2: gpf2-gpio-bank {
 50		gpio-controller;
 51		#gpio-cells = <2>;
 52		interrupt-controller;
 53		#interrupt-cells = <2>;
 54	};
 55
 56	gpf3: gpf3-gpio-bank {
 57		gpio-controller;
 58		#gpio-cells = <2>;
 59		interrupt-controller;
 60		#interrupt-cells = <2>;
 61	};
 62
 63	gpf4: gpf4-gpio-bank {
 64		gpio-controller;
 65		#gpio-cells = <2>;
 66		interrupt-controller;
 67		#interrupt-cells = <2>;
 68	};
 69
 70	gps0: gps0-gpio-bank {
 71		gpio-controller;
 72		#gpio-cells = <2>;
 73		interrupt-controller;
 74		#interrupt-cells = <2>;
 75	};
 76
 77	gps1: gps1-gpio-bank {
 78		gpio-controller;
 79		#gpio-cells = <2>;
 80		interrupt-controller;
 81		#interrupt-cells = <2>;
 82	};
 83
 84	serial0_bus: serial0-bus-pins {
 85		samsung,pins = "gpf4-4", "gpf4-5";
 86		samsung,pin-function = <ARTPEC_PIN_FUNC_2>;
 87		samsung,pin-pud = <ARTPEC_PIN_PULL_UP>;
 88		samsung,pin-drv = <ARTPEC_PIN_DRV_SR3>;
 89	};
 90};
 91
 92&pinctrl_peric {
 93	gpa0: gpa0-gpio-bank {
 94		gpio-controller;
 95		#gpio-cells = <2>;
 96		interrupt-controller;
 97		#interrupt-cells = <2>;
 98	};
 99
100	gpa1: gpa1-gpio-bank {
101		gpio-controller;
102		#gpio-cells = <2>;
103		interrupt-controller;
104		#interrupt-cells = <2>;
105	};
106
107	gpa2: gpa2-gpio-bank {
108		gpio-controller;
109		#gpio-cells = <2>;
110		interrupt-controller;
111		#interrupt-cells = <2>;
112	};
113
114	gpk0: gpk0-gpio-bank {
115		gpio-controller;
116		#gpio-cells = <2>;
117		interrupt-controller;
118		#interrupt-cells = <2>;
119	};
120};