ns2-clock.dtsi

  1/*
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  4 *  Copyright (c) 2016 Broadcom.  All rights reserved.
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 11 *      notice, this list of conditions and the following disclaimer.
 12 *    * Redistributions in binary form must reproduce the above copyright
 13 *      notice, this list of conditions and the following disclaimer in
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 18 *      from this software without specific prior written permission.
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 31 */
 32
 33#include <dt-bindings/clock/bcm-ns2.h>
 34
 35	osc: oscillator {
 36		#clock-cells = <0>;
 37		compatible = "fixed-clock";
 38		clock-frequency = <25000000>;
 39	};
 40
 41	lcpll_ddr: lcpll_ddr@6501d058 {
 42		#clock-cells = <1>;
 43		compatible = "brcm,ns2-lcpll-ddr";
 44		reg = <0x6501d058 0x20>,
 45		      <0x6501c020 0x4>,
 46		      <0x6501d04c 0x4>;
 47		clocks = <&osc>;
 48		clock-output-names = "lcpll_ddr", "pcie_sata_usb",
 49				     "ddr", "ddr_ch2_unused",
 50				     "ddr_ch3_unused", "ddr_ch4_unused",
 51				     "ddr_ch5_unused";
 52	};
 53
 54	lcpll_ports: lcpll_ports@6501d078 {
 55		#clock-cells = <1>;
 56		compatible = "brcm,ns2-lcpll-ports";
 57		reg = <0x6501d078 0x20>,
 58		      <0x6501c020 0x4>,
 59		      <0x6501d054 0x4>;
 60		clocks = <&osc>;
 61		clock-output-names = "lcpll_ports", "wan", "rgmii",
 62				     "ports_ch2_unused",
 63				     "ports_ch3_unused",
 64				     "ports_ch4_unused",
 65				     "ports_ch5_unused";
 66	};
 67
 68	genpll_scr: genpll_scr@6501d098 {
 69		#clock-cells = <1>;
 70		compatible = "brcm,ns2-genpll-scr";
 71		reg = <0x6501d098 0x32>,
 72		      <0x6501c020 0x4>,
 73		      <0x6501d044 0x4>;
 74		clocks = <&osc>;
 75		clock-output-names = "genpll_scr", "scr", "fs",
 76				     "audio_ref", "scr_ch3_unused",
 77				     "scr_ch4_unused", "scr_ch5_unused";
 78	};
 79
 80	iprocmed: iprocmed {
 81		#clock-cells = <0>;
 82		compatible = "fixed-factor-clock";
 83		clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>;
 84		clock-div = <2>;
 85		clock-mult = <1>;
 86	};
 87
 88	iprocslow: iprocslow {
 89		#clock-cells = <0>;
 90		compatible = "fixed-factor-clock";
 91		clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>;
 92		clock-div = <4>;
 93		clock-mult = <1>;
 94	};
 95
 96	genpll_sw: genpll_sw@6501d0c4 {
 97		#clock-cells = <1>;
 98		compatible = "brcm,ns2-genpll-sw";
 99		reg = <0x6501d0c4 0x32>,
100		      <0x6501c020 0x4>,
101		      <0x6501d044 0x4>;
102		clocks = <&osc>;
103		clock-output-names = "genpll_sw", "rpe", "250", "nic",
104				     "chimp", "port", "sdio";
105	};