bcm6858.dtsi

  1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2/*
  3 * Copyright 2022 Broadcom Ltd.
  4 */
  5
  6#include <dt-bindings/interrupt-controller/irq.h>
  7#include <dt-bindings/interrupt-controller/arm-gic.h>
  8
  9/ {
 10	compatible = "brcm,bcm6858", "brcm,bcmbca";
 11	#address-cells = <2>;
 12	#size-cells = <2>;
 13
 14	interrupt-parent = <&gic>;
 15
 16	cpus {
 17		#address-cells = <2>;
 18		#size-cells = <0>;
 19
 20		B53_0: cpu@0 {
 21			compatible = "brcm,brahma-b53";
 22			device_type = "cpu";
 23			reg = <0x0 0x0>;
 24			next-level-cache = <&L2_0>;
 25			enable-method = "psci";
 26		};
 27
 28		B53_1: cpu@1 {
 29			compatible = "brcm,brahma-b53";
 30			device_type = "cpu";
 31			reg = <0x0 0x1>;
 32			next-level-cache = <&L2_0>;
 33			enable-method = "psci";
 34		};
 35
 36		B53_2: cpu@2 {
 37			compatible = "brcm,brahma-b53";
 38			device_type = "cpu";
 39			reg = <0x0 0x2>;
 40			next-level-cache = <&L2_0>;
 41			enable-method = "psci";
 42		};
 43
 44		B53_3: cpu@3 {
 45			compatible = "brcm,brahma-b53";
 46			device_type = "cpu";
 47			reg = <0x0 0x3>;
 48			next-level-cache = <&L2_0>;
 49			enable-method = "psci";
 50		};
 51		L2_0: l2-cache0 {
 52			compatible = "cache";
 53			cache-level = <2>;
 54			cache-unified;
 55		};
 56	};
 57
 58	timer {
 59		compatible = "arm,armv8-timer";
 60		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 61			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 62			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 63			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 64	};
 65
 66	pmu: pmu {
 67		compatible = "arm,armv8-pmuv3";
 68		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 69			<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
 70			<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 71			<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 72		interrupt-affinity = <&B53_0>, <&B53_1>,
 73			<&B53_2>, <&B53_3>;
 74	};
 75
 76	clocks: clocks {
 77		periph_clk:periph-clk {
 78			compatible = "fixed-clock";
 79			#clock-cells = <0>;
 80			clock-frequency = <200000000>;
 81		};
 82
 83		hsspi_pll: hsspi-pll {
 84			compatible = "fixed-clock";
 85			#clock-cells = <0>;
 86			clock-frequency = <400000000>;
 87		};
 88	};
 89
 90	psci {
 91		compatible = "arm,psci-0.2";
 92		method = "smc";
 93	};
 94
 95	axi@81000000 {
 96		compatible = "simple-bus";
 97		#address-cells = <1>;
 98		#size-cells = <1>;
 99		ranges = <0x0 0x0 0x81000000 0x8000>;
100
101		gic: interrupt-controller@1000 {
102			compatible = "arm,gic-400";
103			#interrupt-cells = <3>;
104			interrupt-controller;
105			reg = <0x1000 0x1000>, /* GICD */
106				<0x2000 0x2000>, /* GICC */
107				<0x4000 0x2000>, /* GICH */
108				<0x6000 0x2000>; /* GICV */
109			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
110					IRQ_TYPE_LEVEL_HIGH)>;
111		};
112	};
113
114	/* PERF Peripherals */
115	bus@ff800000 {
116		compatible = "simple-bus";
117		#address-cells = <1>;
118		#size-cells = <1>;
119		ranges = <0x0 0x0 0xff800000 0x400000>;
120
121		twd: timer-mfd@400 {
122			compatible = "brcm,bcm4908-twd", "simple-mfd", "syscon";
123			reg = <0x400 0x4c>;
124			ranges = <0x0 0x400 0x4c>;
125
126			#address-cells = <1>;
127			#size-cells = <1>;
128
129			timer@0 {
130				compatible = "brcm,bcm63138-timer";
131				reg = <0x0 0x28>;
132			};
133
134			watchdog@28 {
135				compatible = "brcm,bcm6345-wdt";
136				reg = <0x28 0x8>;
137			};
138		};
139
140		/* GPIOs 0 .. 31 */
141		gpio0: gpio@500 {
142			compatible = "brcm,bcm6345-gpio";
143			reg = <0x500 0x04>, <0x520 0x04>;
144			reg-names = "dirout", "dat";
145			gpio-controller;
146			#gpio-cells = <2>;
147			status = "disabled";
148		};
149
150		/* GPIOs 32 .. 63 */
151		gpio1: gpio@504 {
152			compatible = "brcm,bcm6345-gpio";
153			reg = <0x504 0x04>, <0x524 0x04>;
154			reg-names = "dirout", "dat";
155			gpio-controller;
156			#gpio-cells = <2>;
157			status = "disabled";
158		};
159
160		/* GPIOs 64 .. 95 */
161		gpio2: gpio@508 {
162			compatible = "brcm,bcm6345-gpio";
163			reg = <0x508 0x04>, <0x528 0x04>;
164			reg-names = "dirout", "dat";
165			gpio-controller;
166			#gpio-cells = <2>;
167			status = "disabled";
168		};
169
170		/* GPIOs 96 .. 127 */
171		gpio3: gpio@50c {
172			compatible = "brcm,bcm6345-gpio";
173			reg = <0x50c 0x04>, <0x52c 0x04>;
174			reg-names = "dirout", "dat";
175			gpio-controller;
176			#gpio-cells = <2>;
177			status = "disabled";
178		};
179
180		/* GPIOs 128 .. 159 */
181		gpio4: gpio@510 {
182			compatible = "brcm,bcm6345-gpio";
183			reg = <0x510 0x04>, <0x530 0x04>;
184			reg-names = "dirout", "dat";
185			gpio-controller;
186			#gpio-cells = <2>;
187			status = "disabled";
188		};
189
190		/* GPIOs 160 .. 191 */
191		gpio5: gpio@514 {
192			compatible = "brcm,bcm6345-gpio";
193			reg = <0x514 0x04>, <0x534 0x04>;
194			reg-names = "dirout", "dat";
195			gpio-controller;
196			#gpio-cells = <2>;
197			status = "disabled";
198		};
199
200		/* GPIOs 192 .. 223 */
201		gpio6: gpio@518 {
202			compatible = "brcm,bcm6345-gpio";
203			reg = <0x518 0x04>, <0x538 0x04>;
204			reg-names = "dirout", "dat";
205			gpio-controller;
206			#gpio-cells = <2>;
207			status = "disabled";
208		};
209
210		/* GPIOs 224 .. 255 */
211		gpio7: gpio@51c {
212			compatible = "brcm,bcm6345-gpio";
213			reg = <0x51c 0x04>, <0x53c 0x04>;
214			reg-names = "dirout", "dat";
215			gpio-controller;
216			#gpio-cells = <2>;
217			status = "disabled";
218		};
219
220		uart0: serial@640 {
221			compatible = "brcm,bcm6345-uart";
222			reg = <0x640 0x18>;
223			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
224			clocks = <&periph_clk>;
225			clock-names = "refclk";
226			status = "disabled";
227		};
228
229		uart1: serial@660 {
230			compatible = "brcm,bcm6345-uart";
231			reg = <0x660 0x18>;
232			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
233			clocks = <&periph_clk>;
234			clock-names = "refclk";
235			status = "disabled";
236		};
237
238		leds: led-controller@800 {
239			#address-cells = <1>;
240			#size-cells = <0>;
241			compatible = "brcm,bcm63138-leds";
242			reg = <0x800 0xdc>;
243			status = "disabled";
244		};
245
246		rng@b80 {
247			compatible = "brcm,iproc-rng200";
248			reg = <0xb80 0x28>;
249			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
250		};
251
252		hsspi: spi@1000 {
253			#address-cells = <1>;
254			#size-cells = <0>;
255			compatible = "brcm,bcm6858-hsspi", "brcm,bcmbca-hsspi-v1.0";
256			reg = <0x1000 0x600>;
257			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
258			clocks = <&hsspi_pll &hsspi_pll>;
259			clock-names = "hsspi", "pll";
260			num-cs = <8>;
261			status = "disabled";
262		};
263
264		nand_controller: nand-controller@1800 {
265			#address-cells = <1>;
266			#size-cells = <0>;
267			compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand";
268			reg = <0x1800 0x600>, <0x2000 0x10>;
269			reg-names = "nand", "nand-int-base";
270			status = "disabled";
271
272			nandcs: nand@0 {
273				compatible = "brcm,nandcs";
274				reg = <0>;
275			};
276		};
277
278		pl081_dma: dma-controller@59000 {
279			compatible = "arm,pl081", "arm,primecell";
280			// The magic B105F00D info is missing
281			arm,primecell-periphid = <0x00041081>;
282			reg = <0x59000 0x1000>;
283			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
284			memcpy-burst-size = <256>;
285			memcpy-bus-width = <32>;
286			clocks = <&periph_clk>;
287			clock-names = "apb_pclk";
288			#dma-cells = <2>;
289		};
290	};
291};