bcm6856.dtsi

  1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2/*
  3 * Copyright 2022 Broadcom Ltd.
  4 */
  5
  6#include <dt-bindings/interrupt-controller/irq.h>
  7#include <dt-bindings/interrupt-controller/arm-gic.h>
  8
  9/ {
 10	compatible = "brcm,bcm6856", "brcm,bcmbca";
 11	#address-cells = <2>;
 12	#size-cells = <2>;
 13
 14	interrupt-parent = <&gic>;
 15
 16	cpus {
 17		#address-cells = <2>;
 18		#size-cells = <0>;
 19
 20		B53_0: cpu@0 {
 21			compatible = "brcm,brahma-b53";
 22			device_type = "cpu";
 23			reg = <0x0 0x0>;
 24			next-level-cache = <&L2_0>;
 25			enable-method = "psci";
 26		};
 27
 28		B53_1: cpu@1 {
 29			compatible = "brcm,brahma-b53";
 30			device_type = "cpu";
 31			reg = <0x0 0x1>;
 32			next-level-cache = <&L2_0>;
 33			enable-method = "psci";
 34		};
 35
 36		L2_0: l2-cache0 {
 37			compatible = "cache";
 38			cache-level = <2>;
 39			cache-unified;
 40		};
 41	};
 42
 43	timer {
 44		compatible = "arm,armv8-timer";
 45		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 46			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 47			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 48			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
 49	};
 50
 51	pmu: pmu {
 52		compatible = "arm,cortex-a53-pmu";
 53		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 54			<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 55		interrupt-affinity = <&B53_0>, <&B53_1>;
 56	};
 57
 58	clocks: clocks {
 59		periph_clk:periph-clk {
 60			compatible = "fixed-clock";
 61			#clock-cells = <0>;
 62			clock-frequency = <200000000>;
 63		};
 64
 65		hsspi_pll: hsspi-pll {
 66			compatible = "fixed-clock";
 67			#clock-cells = <0>;
 68			clock-frequency = <400000000>;
 69		};
 70	};
 71
 72	psci {
 73		compatible = "arm,psci-0.2";
 74		method = "smc";
 75	};
 76
 77	axi@81000000 {
 78		compatible = "simple-bus";
 79		#address-cells = <1>;
 80		#size-cells = <1>;
 81		ranges = <0x0 0x0 0x81000000 0x8000>;
 82
 83		gic: interrupt-controller@1000 {
 84			compatible = "arm,gic-400";
 85			#interrupt-cells = <3>;
 86			interrupt-controller;
 87			reg = <0x1000 0x1000>, /* GICD */
 88				<0x2000 0x2000>, /* GICC */
 89				<0x4000 0x2000>, /* GICH */
 90				<0x6000 0x2000>; /* GICV */
 91			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
 92					IRQ_TYPE_LEVEL_HIGH)>;
 93		};
 94	};
 95
 96	/* PERF Peripherals */
 97	bus@ff800000 {
 98		compatible = "simple-bus";
 99		#address-cells = <1>;
100		#size-cells = <1>;
101		ranges = <0x0 0x0 0xff800000 0x400000>;
102
103		watchdog@480 {
104			compatible = "brcm,bcm6345-wdt";
105			reg = <0x480 0x10>;
106		};
107
108		watchdog@4c0 {
109			compatible = "brcm,bcm6345-wdt";
110			reg = <0x4c0 0x10>;
111			status = "disabled";
112		};
113
114		/* GPIOs 0 .. 31 */
115		gpio0: gpio@500 {
116			compatible = "brcm,bcm6345-gpio";
117			reg = <0x500 0x04>, <0x520 0x04>;
118			reg-names = "dirout", "dat";
119			gpio-controller;
120			#gpio-cells = <2>;
121			status = "disabled";
122		};
123
124		/* GPIOs 32 .. 63 */
125		gpio1: gpio@504 {
126			compatible = "brcm,bcm6345-gpio";
127			reg = <0x504 0x04>, <0x524 0x04>;
128			reg-names = "dirout", "dat";
129			gpio-controller;
130			#gpio-cells = <2>;
131			status = "disabled";
132		};
133
134		/* GPIOs 64 .. 95 */
135		gpio2: gpio@508 {
136			compatible = "brcm,bcm6345-gpio";
137			reg = <0x508 0x04>, <0x528 0x04>;
138			reg-names = "dirout", "dat";
139			gpio-controller;
140			#gpio-cells = <2>;
141			status = "disabled";
142		};
143
144		/* GPIOs 96 .. 127 */
145		gpio3: gpio@50c {
146			compatible = "brcm,bcm6345-gpio";
147			reg = <0x50c 0x04>, <0x52c 0x04>;
148			reg-names = "dirout", "dat";
149			gpio-controller;
150			#gpio-cells = <2>;
151			status = "disabled";
152		};
153
154		/* GPIOs 128 .. 159 */
155		gpio4: gpio@510 {
156			compatible = "brcm,bcm6345-gpio";
157			reg = <0x510 0x04>, <0x530 0x04>;
158			reg-names = "dirout", "dat";
159			gpio-controller;
160			#gpio-cells = <2>;
161			status = "disabled";
162		};
163
164		/* GPIOs 160 .. 191 */
165		gpio5: gpio@514 {
166			compatible = "brcm,bcm6345-gpio";
167			reg = <0x514 0x04>, <0x534 0x04>;
168			reg-names = "dirout", "dat";
169			gpio-controller;
170			#gpio-cells = <2>;
171			status = "disabled";
172		};
173
174		/* GPIOs 192 .. 223 */
175		gpio6: gpio@518 {
176			compatible = "brcm,bcm6345-gpio";
177			reg = <0x518 0x04>, <0x538 0x04>;
178			reg-names = "dirout", "dat";
179			gpio-controller;
180			#gpio-cells = <2>;
181			status = "disabled";
182		};
183
184		/* GPIOs 224 .. 255 */
185		gpio7: gpio@51c {
186			compatible = "brcm,bcm6345-gpio";
187			reg = <0x51c 0x04>, <0x53c 0x04>;
188			reg-names = "dirout", "dat";
189			gpio-controller;
190			#gpio-cells = <2>;
191			status = "disabled";
192		};
193
194		uart0: serial@640 {
195			compatible = "brcm,bcm6345-uart";
196			reg = <0x640 0x18>;
197			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
198			clocks = <&periph_clk>;
199			clock-names = "refclk";
200			status = "disabled";
201		};
202
203		uart1: serial@660 {
204			compatible = "brcm,bcm6345-uart";
205			reg = <0x660 0x18>;
206			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
207			clocks = <&periph_clk>;
208			clock-names = "refclk";
209			status = "disabled";
210		};
211
212		leds: led-controller@800 {
213			#address-cells = <1>;
214			#size-cells = <0>;
215			compatible = "brcm,bcm63138-leds";
216			reg = <0x800 0xdc>;
217			status = "disabled";
218		};
219
220		rng@b80 {
221			compatible = "brcm,iproc-rng200";
222			reg = <0xb80 0x28>;
223			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
224		};
225
226		hsspi: spi@1000 {
227			#address-cells = <1>;
228			#size-cells = <0>;
229			compatible = "brcm,bcm6856-hsspi", "brcm,bcmbca-hsspi-v1.0";
230			reg = <0x1000 0x600>;
231			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
232			clocks = <&hsspi_pll &hsspi_pll>;
233			clock-names = "hsspi", "pll";
234			num-cs = <8>;
235			status = "disabled";
236		};
237
238		nand_controller: nand-controller@1800 {
239			#address-cells = <1>;
240			#size-cells = <0>;
241			compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand";
242			reg = <0x1800 0x600>, <0x2000 0x10>;
243			reg-names = "nand", "nand-int-base";
244			status = "disabled";
245
246			nandcs: nand@0 {
247				compatible = "brcm,nandcs";
248				reg = <0>;
249			};
250		};
251
252		pl081_dma: dma-controller@59000 {
253			compatible = "arm,pl081", "arm,primecell";
254			// The magic B105F00D info is missing
255			arm,primecell-periphid = <0x00041081>;
256			reg = <0x59000 0x1000>;
257			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
258			memcpy-burst-size = <256>;
259			memcpy-bus-width = <32>;
260			clocks = <&periph_clk>;
261			clock-names = "apb_pclk";
262			#dma-cells = <2>;
263		};
264	};
265};