blaize-blzp1600.dtsi

  1// SPDX-License-Identifier: GPL-2.0+
  2/*
  3 * Copyright (c) 2024 Blaize, Inc. All rights reserved.
  4 */
  5
  6/dts-v1/;
  7
  8#include <dt-bindings/gpio/gpio.h>
  9#include <dt-bindings/interrupt-controller/arm-gic.h>
 10
 11/ {
 12	interrupt-parent = <&gic>;
 13	#address-cells = <2>;
 14	#size-cells = <2>;
 15
 16	cpus {
 17		#address-cells = <2>;
 18		#size-cells = <0>;
 19
 20		cpu0: cpu@0 {
 21			compatible = "arm,cortex-a53";
 22			reg = <0x0 0x0>;
 23			device_type = "cpu";
 24			enable-method = "psci";
 25			next-level-cache = <&l2>;
 26		};
 27
 28		cpu1: cpu@1 {
 29			compatible = "arm,cortex-a53";
 30			reg = <0x0 0x1>;
 31			device_type = "cpu";
 32			enable-method = "psci";
 33			next-level-cache = <&l2>;
 34		};
 35
 36		l2: l2-cache0 {
 37			compatible = "cache";
 38			cache-level = <2>;
 39			cache-unified;
 40		};
 41	};
 42
 43	firmware {
 44		scmi {
 45			compatible = "arm,scmi-smc";
 46			arm,smc-id = <0x82002000>;
 47			#address-cells = <1>;
 48			#size-cells = <0>;
 49
 50			shmem = <&scmi0_shm>;
 51
 52			scmi_clk: protocol@14 {
 53				reg = <0x14>;
 54				#clock-cells = <1>;
 55			};
 56
 57			scmi_rst: protocol@16 {
 58				reg = <0x16>;
 59				#reset-cells = <1>;
 60			};
 61		};
 62	};
 63
 64	pmu {
 65		compatible = "arm,cortex-a53-pmu";
 66		interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 67			     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 68		interrupt-affinity = <&cpu0>, <&cpu1>;
 69	};
 70
 71	psci {
 72		compatible = "arm,psci-1.0", "arm,psci-0.2";
 73		method = "smc";
 74	};
 75
 76	reserved-memory {
 77		#address-cells = <2>;
 78		#size-cells = <2>;
 79		ranges;
 80
 81		/* SCMI reserved buffer space on DDR space */
 82		scmi0_shm: scmi-shmem@800 {
 83			compatible = "arm,scmi-shmem";
 84			reg = <0x0 0x800 0x0 0x80>;
 85		};
 86	};
 87
 88	timer {
 89		compatible = "arm,armv8-timer";
 90		interrupts = /* Physical Secure PPI */
 91			     <GIC_PPI 13 (GIC_CPU_MASK_RAW(0x3) |
 92					  IRQ_TYPE_LEVEL_LOW)>,
 93			     /* Physical Non-Secure PPI */
 94			     <GIC_PPI 14 (GIC_CPU_MASK_RAW(0x3) |
 95					  IRQ_TYPE_LEVEL_LOW)>,
 96			     /* Hypervisor PPI */
 97			     <GIC_PPI 10 (GIC_CPU_MASK_RAW(0x3) |
 98					  IRQ_TYPE_LEVEL_LOW)>,
 99			     /* Virtual PPI */
100			     <GIC_PPI 11 (GIC_CPU_MASK_RAW(0x3) |
101					  IRQ_TYPE_LEVEL_LOW)>;
102	};
103
104	soc@200000000 {
105		compatible = "simple-bus";
106		#address-cells = <1>;
107		#size-cells = <1>;
108		ranges = <0x0 0x2 0x0 0x850000>;
109
110		gic: interrupt-controller@410000 {
111			compatible = "arm,gic-400";
112			reg = <0x410000 0x20000>,
113			      <0x420000 0x20000>,
114			      <0x440000 0x20000>,
115			      <0x460000 0x20000>;
116			#interrupt-cells = <3>;
117			#address-cells = <0>;
118			interrupt-controller;
119			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0x3) |
120						 IRQ_TYPE_LEVEL_LOW)>;
121		};
122
123		gpio0: gpio@4c0000 {
124			compatible = "blaize,blzp1600-gpio";
125			reg = <0x4c0000 0x1000>;
126			gpio-controller;
127			#gpio-cells = <2>;
128			ngpios = <32>;
129			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
130			interrupt-controller;
131			#interrupt-cells = <2>;
132			status = "disabled";
133		};
134
135		uart0: serial@4d0000 {
136			compatible = "ns16550a";
137			reg = <0x4d0000 0x1000>;
138			clocks = <&scmi_clk 59>;
139			resets = <&scmi_rst 59>;
140			reg-shift = <2>;
141			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
142			status = "disabled";
143		};
144
145		uart1: serial@4e0000 {
146			compatible = "ns16550a";
147			reg = <0x4e0000 0x1000>;
148			clocks = <&scmi_clk 60>;
149			resets = <&scmi_rst 60>;
150			reg-shift = <2>;
151			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
152			status = "disabled";
153		};
154
155		i2c0: i2c@4f0000 {
156			compatible = "snps,designware-i2c";
157			reg = <0x4f0000 0x1000>;
158			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
159			clocks = <&scmi_clk 54>;
160			resets = <&scmi_rst 54>;
161			#address-cells = <1>;
162			#size-cells = <0>;
163			status = "disabled";
164		};
165
166		i2c1: i2c@500000 {
167			compatible = "snps,designware-i2c";
168			reg = <0x500000 0x1000>;
169			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
170			clocks = <&scmi_clk 55>;
171			resets = <&scmi_rst 55>;
172			#address-cells = <1>;
173			#size-cells = <0>;
174			status = "disabled";
175		};
176
177		i2c2: i2c@510000 {
178			compatible = "snps,designware-i2c";
179			reg = <0x510000 0x1000>;
180			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
181			clocks = <&scmi_clk 56>;
182			resets = <&scmi_rst 56>;
183			#address-cells = <1>;
184			#size-cells = <0>;
185			status = "disabled";
186		};
187
188		i2c3: i2c@520000 {
189			compatible = "snps,designware-i2c";
190			reg = <0x520000 0x1000>;
191			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
192			clocks = <&scmi_clk 57>;
193			resets = <&scmi_rst 57>;
194			#address-cells = <1>;
195			#size-cells = <0>;
196			status = "disabled";
197		};
198
199		i2c4: i2c@530000 {
200			compatible = "snps,designware-i2c";
201			reg = <0x530000 0x1000>;
202			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
203			clocks = <&scmi_clk 58>;
204			resets = <&scmi_rst 58>;
205			#address-cells = <1>;
206			#size-cells = <0>;
207			status = "disabled";
208		};
209
210		arm_cc712: crypto@550000 {
211			compatible = "arm,cryptocell-712-ree";
212			reg = <0x550000 0x1000>;
213			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
214			clocks = <&scmi_clk 7>;
215		};
216	};
217};