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t8103.dtsi
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linux-6.19.14/arch/arm64/boot/dts/apple/t8103.dtsi
1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Apple T8103 "M1" SoC 4 * 5 * Other names: H13G, "Tonga" 6 * 7 * Copyright The Asahi Linux Contributors 8 */ 9 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/interrupt-controller/apple-aic.h> 12#include <dt-bindings/interrupt-controller/irq.h> 13#include <dt-bindings/pinctrl/apple.h> 14#include <dt-bindings/spmi/spmi.h> 15 16/ { 17 compatible = "apple,t8103", "apple,arm-platform"; 18 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 gpu = &gpu; 24 }; 25 26 cpus { 27 #address-cells = <2>; 28 #size-cells = <0>; 29 30 cpu-map { 31 cluster0 { 32 core0 { 33 cpu = <&cpu_e0>; 34 }; 35 core1 { 36 cpu = <&cpu_e1>; 37 }; 38 core2 { 39 cpu = <&cpu_e2>; 40 }; 41 core3 { 42 cpu = <&cpu_e3>; 43 }; 44 }; 45 46 cluster1 { 47 core0 { 48 cpu = <&cpu_p0>; 49 }; 50 core1 { 51 cpu = <&cpu_p1>; 52 }; 53 core2 { 54 cpu = <&cpu_p2>; 55 }; 56 core3 { 57 cpu = <&cpu_p3>; 58 }; 59 }; 60 }; 61 62 cpu_e0: cpu@0 { 63 compatible = "apple,icestorm"; 64 device_type = "cpu"; 65 reg = <0x0 0x0>; 66 enable-method = "spin-table"; 67 cpu-release-addr = <0 0>; /* To be filled by loader */ 68 operating-points-v2 = <&ecluster_opp>; 69 capacity-dmips-mhz = <714>; 70 performance-domains = <&cpufreq_e>; 71 next-level-cache = <&l2_cache_0>; 72 i-cache-size = <0x20000>; 73 d-cache-size = <0x10000>; 74 }; 75 76 cpu_e1: cpu@1 { 77 compatible = "apple,icestorm"; 78 device_type = "cpu"; 79 reg = <0x0 0x1>; 80 enable-method = "spin-table"; 81 cpu-release-addr = <0 0>; /* To be filled by loader */ 82 operating-points-v2 = <&ecluster_opp>; 83 capacity-dmips-mhz = <714>; 84 performance-domains = <&cpufreq_e>; 85 next-level-cache = <&l2_cache_0>; 86 i-cache-size = <0x20000>; 87 d-cache-size = <0x10000>; 88 }; 89 90 cpu_e2: cpu@2 { 91 compatible = "apple,icestorm"; 92 device_type = "cpu"; 93 reg = <0x0 0x2>; 94 enable-method = "spin-table"; 95 cpu-release-addr = <0 0>; /* To be filled by loader */ 96 operating-points-v2 = <&ecluster_opp>; 97 capacity-dmips-mhz = <714>; 98 performance-domains = <&cpufreq_e>; 99 next-level-cache = <&l2_cache_0>; 100 i-cache-size = <0x20000>; 101 d-cache-size = <0x10000>; 102 }; 103 104 cpu_e3: cpu@3 { 105 compatible = "apple,icestorm"; 106 device_type = "cpu"; 107 reg = <0x0 0x3>; 108 enable-method = "spin-table"; 109 cpu-release-addr = <0 0>; /* To be filled by loader */ 110 operating-points-v2 = <&ecluster_opp>; 111 capacity-dmips-mhz = <714>; 112 performance-domains = <&cpufreq_e>; 113 next-level-cache = <&l2_cache_0>; 114 i-cache-size = <0x20000>; 115 d-cache-size = <0x10000>; 116 }; 117 118 cpu_p0: cpu@10100 { 119 compatible = "apple,firestorm"; 120 device_type = "cpu"; 121 reg = <0x0 0x10100>; 122 enable-method = "spin-table"; 123 cpu-release-addr = <0 0>; /* To be filled by loader */ 124 operating-points-v2 = <&pcluster_opp>; 125 capacity-dmips-mhz = <1024>; 126 performance-domains = <&cpufreq_p>; 127 next-level-cache = <&l2_cache_1>; 128 i-cache-size = <0x30000>; 129 d-cache-size = <0x20000>; 130 }; 131 132 cpu_p1: cpu@10101 { 133 compatible = "apple,firestorm"; 134 device_type = "cpu"; 135 reg = <0x0 0x10101>; 136 enable-method = "spin-table"; 137 cpu-release-addr = <0 0>; /* To be filled by loader */ 138 operating-points-v2 = <&pcluster_opp>; 139 capacity-dmips-mhz = <1024>; 140 performance-domains = <&cpufreq_p>; 141 next-level-cache = <&l2_cache_1>; 142 i-cache-size = <0x30000>; 143 d-cache-size = <0x20000>; 144 }; 145 146 cpu_p2: cpu@10102 { 147 compatible = "apple,firestorm"; 148 device_type = "cpu"; 149 reg = <0x0 0x10102>; 150 enable-method = "spin-table"; 151 cpu-release-addr = <0 0>; /* To be filled by loader */ 152 operating-points-v2 = <&pcluster_opp>; 153 capacity-dmips-mhz = <1024>; 154 performance-domains = <&cpufreq_p>; 155 next-level-cache = <&l2_cache_1>; 156 i-cache-size = <0x30000>; 157 d-cache-size = <0x20000>; 158 }; 159 160 cpu_p3: cpu@10103 { 161 compatible = "apple,firestorm"; 162 device_type = "cpu"; 163 reg = <0x0 0x10103>; 164 enable-method = "spin-table"; 165 cpu-release-addr = <0 0>; /* To be filled by loader */ 166 operating-points-v2 = <&pcluster_opp>; 167 capacity-dmips-mhz = <1024>; 168 performance-domains = <&cpufreq_p>; 169 next-level-cache = <&l2_cache_1>; 170 i-cache-size = <0x30000>; 171 d-cache-size = <0x20000>; 172 }; 173 174 l2_cache_0: l2-cache-0 { 175 compatible = "cache"; 176 cache-level = <2>; 177 cache-unified; 178 cache-size = <0x400000>; 179 }; 180 181 l2_cache_1: l2-cache-1 { 182 compatible = "cache"; 183 cache-level = <2>; 184 cache-unified; 185 cache-size = <0xc00000>; 186 }; 187 }; 188 189 ecluster_opp: opp-table-0 { 190 compatible = "operating-points-v2"; 191 192 opp01 { 193 opp-hz = /bits/ 64 <600000000>; 194 opp-level = <1>; 195 clock-latency-ns = <7500>; 196 }; 197 opp02 { 198 opp-hz = /bits/ 64 <972000000>; 199 opp-level = <2>; 200 clock-latency-ns = <22000>; 201 }; 202 opp03 { 203 opp-hz = /bits/ 64 <1332000000>; 204 opp-level = <3>; 205 clock-latency-ns = <27000>; 206 }; 207 opp04 { 208 opp-hz = /bits/ 64 <1704000000>; 209 opp-level = <4>; 210 clock-latency-ns = <33000>; 211 }; 212 opp05 { 213 opp-hz = /bits/ 64 <2064000000>; 214 opp-level = <5>; 215 clock-latency-ns = <50000>; 216 }; 217 }; 218 219 pcluster_opp: opp-table-1 { 220 compatible = "operating-points-v2"; 221 222 opp01 { 223 opp-hz = /bits/ 64 <600000000>; 224 opp-level = <1>; 225 clock-latency-ns = <8000>; 226 }; 227 opp02 { 228 opp-hz = /bits/ 64 <828000000>; 229 opp-level = <2>; 230 clock-latency-ns = <19000>; 231 }; 232 opp03 { 233 opp-hz = /bits/ 64 <1056000000>; 234 opp-level = <3>; 235 clock-latency-ns = <21000>; 236 }; 237 opp04 { 238 opp-hz = /bits/ 64 <1284000000>; 239 opp-level = <4>; 240 clock-latency-ns = <23000>; 241 }; 242 opp05 { 243 opp-hz = /bits/ 64 <1500000000>; 244 opp-level = <5>; 245 clock-latency-ns = <24000>; 246 }; 247 opp06 { 248 opp-hz = /bits/ 64 <1728000000>; 249 opp-level = <6>; 250 clock-latency-ns = <29000>; 251 }; 252 opp07 { 253 opp-hz = /bits/ 64 <1956000000>; 254 opp-level = <7>; 255 clock-latency-ns = <31000>; 256 }; 257 opp08 { 258 opp-hz = /bits/ 64 <2184000000>; 259 opp-level = <8>; 260 clock-latency-ns = <34000>; 261 }; 262 opp09 { 263 opp-hz = /bits/ 64 <2388000000>; 264 opp-level = <9>; 265 clock-latency-ns = <36000>; 266 }; 267 opp10 { 268 opp-hz = /bits/ 64 <2592000000>; 269 opp-level = <10>; 270 clock-latency-ns = <51000>; 271 }; 272 opp11 { 273 opp-hz = /bits/ 64 <2772000000>; 274 opp-level = <11>; 275 clock-latency-ns = <54000>; 276 }; 277 opp12 { 278 opp-hz = /bits/ 64 <2988000000>; 279 opp-level = <12>; 280 clock-latency-ns = <55000>; 281 }; 282#if 0 283 /* Not available until CPU deep sleep is implemented */ 284 opp13 { 285 opp-hz = /bits/ 64 <3096000000>; 286 opp-level = <13>; 287 clock-latency-ns = <55000>; 288 turbo-mode; 289 }; 290 opp14 { 291 opp-hz = /bits/ 64 <3144000000>; 292 opp-level = <14>; 293 clock-latency-ns = <56000>; 294 turbo-mode; 295 }; 296 opp15 { 297 opp-hz = /bits/ 64 <3204000000>; 298 opp-level = <15>; 299 clock-latency-ns = <56000>; 300 turbo-mode; 301 }; 302#endif 303 }; 304 305 timer { 306 compatible = "arm,armv8-timer"; 307 interrupt-parent = <&aic>; 308 interrupt-names = "phys", "virt", "hyp-phys", "hyp-virt"; 309 interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>, 310 <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>, 311 <AIC_FIQ AIC_TMR_HV_PHYS IRQ_TYPE_LEVEL_HIGH>, 312 <AIC_FIQ AIC_TMR_HV_VIRT IRQ_TYPE_LEVEL_HIGH>; 313 }; 314 315 pmu-e { 316 compatible = "apple,icestorm-pmu"; 317 interrupt-parent = <&aic>; 318 interrupts = <AIC_FIQ AIC_CPU_PMU_E IRQ_TYPE_LEVEL_HIGH>; 319 }; 320 321 pmu-p { 322 compatible = "apple,firestorm-pmu"; 323 interrupt-parent = <&aic>; 324 interrupts = <AIC_FIQ AIC_CPU_PMU_P IRQ_TYPE_LEVEL_HIGH>; 325 }; 326 327 clkref: clock-ref { 328 compatible = "fixed-clock"; 329 #clock-cells = <0>; 330 clock-frequency = <24000000>; 331 clock-output-names = "clkref"; 332 }; 333 334 clk_120m: clock-120m { 335 compatible = "fixed-clock"; 336 #clock-cells = <0>; 337 clock-frequency = <120000000>; 338 clock-output-names = "clk_120m"; 339 }; 340 341 clk_200m: clock-200m { 342 compatible = "fixed-clock"; 343 #clock-cells = <0>; 344 clock-frequency = <200000000>; 345 clock-output-names = "clk_200m"; 346 }; 347 348 /* 349 * This is a fabulated representation of the input clock 350 * to NCO since we don't know the true clock tree. 351 */ 352 nco_clkref: clock-ref-nco { 353 compatible = "fixed-clock"; 354 #clock-cells = <0>; 355 clock-output-names = "nco_ref"; 356 }; 357 358 reserved-memory { 359 #address-cells = <2>; 360 #size-cells = <2>; 361 ranges; 362 363 gpu_globals: globals { 364 status = "disabled"; 365 }; 366 367 gpu_hw_cal_a: hw-cal-a { 368 status = "disabled"; 369 }; 370 371 gpu_hw_cal_b: hw-cal-b { 372 status = "disabled"; 373 }; 374 375 uat_handoff: uat-handoff { 376 status = "disabled"; 377 }; 378 379 uat_pagetables: uat-pagetables { 380 status = "disabled"; 381 }; 382 383 uat_ttbs: uat-ttbs { 384 status = "disabled"; 385 }; 386 }; 387 388 soc { 389 compatible = "simple-bus"; 390 #address-cells = <2>; 391 #size-cells = <2>; 392 393 ranges; 394 nonposted-mmio; 395 396 gpu: gpu@206400000 { 397 compatible = "apple,agx-g13g"; 398 reg = <0x2 0x6400000 0 0x40000>, 399 <0x2 0x4000000 0 0x1000000>; 400 reg-names = "asc", "sgx"; 401 mboxes = <&agx_mbox>; 402 power-domains = <&ps_gfx>; 403 memory-region = <&uat_ttbs>, <&uat_pagetables>, <&uat_handoff>, 404 <&gpu_hw_cal_a>, <&gpu_hw_cal_b>, <&gpu_globals>; 405 memory-region-names = "ttbs", "pagetables", "handoff", 406 "hw-cal-a", "hw-cal-b", "globals"; 407 408 apple,firmware-abi = <0 0 0>; 409 }; 410 411 agx_mbox: mbox@206408000 { 412 compatible = "apple,t8103-asc-mailbox", "apple,asc-mailbox-v4"; 413 reg = <0x2 0x6408000 0x0 0x4000>; 414 interrupt-parent = <&aic>; 415 interrupts = <AIC_IRQ 575 IRQ_TYPE_LEVEL_HIGH>, 416 <AIC_IRQ 576 IRQ_TYPE_LEVEL_HIGH>, 417 <AIC_IRQ 577 IRQ_TYPE_LEVEL_HIGH>, 418 <AIC_IRQ 578 IRQ_TYPE_LEVEL_HIGH>; 419 interrupt-names = "send-empty", "send-not-empty", 420 "recv-empty", "recv-not-empty"; 421 #mbox-cells = <0>; 422 }; 423 424 cpufreq_e: performance-controller@210e20000 { 425 compatible = "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq"; 426 reg = <0x2 0x10e20000 0 0x1000>; 427 #performance-domain-cells = <0>; 428 }; 429 430 cpufreq_p: performance-controller@211e20000 { 431 compatible = "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq"; 432 reg = <0x2 0x11e20000 0 0x1000>; 433 #performance-domain-cells = <0>; 434 }; 435 436 display_dfr: display-pipe@228200000 { 437 compatible = "apple,t8103-display-pipe", "apple,h7-display-pipe"; 438 reg = <0x2 0x28200000 0x0 0xc000>, 439 <0x2 0x28400000 0x0 0x4000>; 440 reg-names = "be", "fe"; 441 power-domains = <&ps_dispdfr_fe>, <&ps_dispdfr_be>; 442 interrupt-parent = <&aic>; 443 interrupts = <AIC_IRQ 502 IRQ_TYPE_LEVEL_HIGH>, 444 <AIC_IRQ 506 IRQ_TYPE_LEVEL_HIGH>; 445 interrupt-names = "be", "fe"; 446 iommus = <&displaydfr_dart 0>; 447 status = "disabled"; 448 449 port { 450 dfr_adp_out_mipi: endpoint { 451 remote-endpoint = <&dfr_mipi_in_adp>; 452 }; 453 }; 454 }; 455 456 displaydfr_dart: iommu@228304000 { 457 compatible = "apple,t8103-dart"; 458 reg = <0x2 0x28304000 0x0 0x4000>; 459 interrupt-parent = <&aic>; 460 interrupts = <AIC_IRQ 504 IRQ_TYPE_LEVEL_HIGH>; 461 #iommu-cells = <1>; 462 power-domains = <&ps_dispdfr_fe>; 463 status = "disabled"; 464 }; 465 466 displaydfr_mipi: dsi@228600000 { 467 compatible = "apple,t8103-display-pipe-mipi", "apple,h7-display-pipe-mipi"; 468 reg = <0x2 0x28600000 0x0 0x100000>; 469 power-domains = <&ps_mipi_dsi>; 470 status = "disabled"; 471 472 ports { 473 #address-cells = <1>; 474 #size-cells = <0>; 475 476 dfr_mipi_in: port@0 { 477 reg = <0>; 478 #address-cells = <1>; 479 #size-cells = <0>; 480 481 dfr_mipi_in_adp: endpoint@0 { 482 reg = <0>; 483 remote-endpoint = <&dfr_adp_out_mipi>; 484 }; 485 }; 486 487 dfr_mipi_out: port@1 { 488 reg = <1>; 489 #address-cells = <1>; 490 #size-cells = <0>; 491 }; 492 }; 493 }; 494 495 sio_dart: iommu@235004000 { 496 compatible = "apple,t8103-dart"; 497 reg = <0x2 0x35004000 0x0 0x4000>; 498 interrupt-parent = <&aic>; 499 interrupts = <AIC_IRQ 635 IRQ_TYPE_LEVEL_HIGH>; 500 #iommu-cells = <1>; 501 power-domains = <&ps_sio_cpu>; 502 }; 503 504 i2c0: i2c@235010000 { 505 compatible = "apple,t8103-i2c", "apple,i2c"; 506 reg = <0x2 0x35010000 0x0 0x4000>; 507 clocks = <&clkref>; 508 interrupt-parent = <&aic>; 509 interrupts = <AIC_IRQ 627 IRQ_TYPE_LEVEL_HIGH>; 510 pinctrl-0 = <&i2c0_pins>; 511 pinctrl-names = "default"; 512 #address-cells = <0x1>; 513 #size-cells = <0x0>; 514 power-domains = <&ps_i2c0>; 515 }; 516 517 i2c1: i2c@235014000 { 518 compatible = "apple,t8103-i2c", "apple,i2c"; 519 reg = <0x2 0x35014000 0x0 0x4000>; 520 clocks = <&clkref>; 521 interrupt-parent = <&aic>; 522 interrupts = <AIC_IRQ 628 IRQ_TYPE_LEVEL_HIGH>; 523 pinctrl-0 = <&i2c1_pins>; 524 pinctrl-names = "default"; 525 #address-cells = <0x1>; 526 #size-cells = <0x0>; 527 power-domains = <&ps_i2c1>; 528 }; 529 530 i2c2: i2c@235018000 { 531 compatible = "apple,t8103-i2c", "apple,i2c"; 532 reg = <0x2 0x35018000 0x0 0x4000>; 533 clocks = <&clkref>; 534 interrupt-parent = <&aic>; 535 interrupts = <AIC_IRQ 629 IRQ_TYPE_LEVEL_HIGH>; 536 pinctrl-0 = <&i2c2_pins>; 537 pinctrl-names = "default"; 538 #address-cells = <0x1>; 539 #size-cells = <0x0>; 540 status = "disabled"; /* not used in all devices */ 541 power-domains = <&ps_i2c2>; 542 }; 543 544 i2c3: i2c@23501c000 { 545 compatible = "apple,t8103-i2c", "apple,i2c"; 546 reg = <0x2 0x3501c000 0x0 0x4000>; 547 clocks = <&clkref>; 548 interrupt-parent = <&aic>; 549 interrupts = <AIC_IRQ 630 IRQ_TYPE_LEVEL_HIGH>; 550 pinctrl-0 = <&i2c3_pins>; 551 pinctrl-names = "default"; 552 #address-cells = <0x1>; 553 #size-cells = <0x0>; 554 power-domains = <&ps_i2c3>; 555 }; 556 557 i2c4: i2c@235020000 { 558 compatible = "apple,t8103-i2c", "apple,i2c"; 559 reg = <0x2 0x35020000 0x0 0x4000>; 560 clocks = <&clkref>; 561 interrupt-parent = <&aic>; 562 interrupts = <AIC_IRQ 631 IRQ_TYPE_LEVEL_HIGH>; 563 pinctrl-0 = <&i2c4_pins>; 564 pinctrl-names = "default"; 565 #address-cells = <0x1>; 566 #size-cells = <0x0>; 567 power-domains = <&ps_i2c4>; 568 status = "disabled"; /* only used in J293 */ 569 }; 570 571 fpwm1: pwm@235044000 { 572 compatible = "apple,t8103-fpwm", "apple,s5l-fpwm"; 573 reg = <0x2 0x35044000 0x0 0x4000>; 574 power-domains = <&ps_fpwm1>; 575 clocks = <&clkref>; 576 #pwm-cells = <2>; 577 status = "disabled"; 578 }; 579 580 spi0: spi@235100000 { 581 compatible = "apple,t8103-spi", "apple,spi"; 582 reg = <0x2 0x35100000 0x0 0x4000>; 583 interrupt-parent = <&aic>; 584 interrupts = <AIC_IRQ 614 IRQ_TYPE_LEVEL_HIGH>; 585 clocks = <&clk_200m>; 586 pinctrl-0 = <&spi0_pins>; 587 pinctrl-names = "default"; 588 power-domains = <&ps_spi0>; 589 #address-cells = <1>; 590 #size-cells = <0>; 591 status = "disabled"; 592 }; 593 594 spi1: spi@235104000 { 595 compatible = "apple,t8103-spi", "apple,spi"; 596 reg = <0x2 0x35104000 0x0 0x4000>; 597 interrupt-parent = <&aic>; 598 interrupts = <AIC_IRQ 615 IRQ_TYPE_LEVEL_HIGH>; 599 clocks = <&clk_200m>; 600 pinctrl-0 = <&spi1_pins>; 601 pinctrl-names = "default"; 602 power-domains = <&ps_spi1>; 603 #address-cells = <1>; 604 #size-cells = <0>; 605 status = "disabled"; 606 }; 607 608 spi3: spi@23510c000 { 609 compatible = "apple,t8103-spi", "apple,spi"; 610 reg = <0x2 0x3510c000 0x0 0x4000>; 611 interrupt-parent = <&aic>; 612 interrupts = <AIC_IRQ 617 IRQ_TYPE_LEVEL_HIGH>; 613 clocks = <&clk_120m>; 614 pinctrl-0 = <&spi3_pins>; 615 pinctrl-names = "default"; 616 power-domains = <&ps_spi3>; 617 #address-cells = <1>; 618 #size-cells = <0>; 619 status = "disabled"; 620 }; 621 622 serial0: serial@235200000 { 623 compatible = "apple,s5l-uart"; 624 reg = <0x2 0x35200000 0x0 0x1000>; 625 reg-io-width = <4>; 626 interrupt-parent = <&aic>; 627 interrupts = <AIC_IRQ 605 IRQ_TYPE_LEVEL_HIGH>; 628 /* 629 * TODO: figure out the clocking properly, there may 630 * be a third selectable clock. 631 */ 632 clocks = <&clkref>, <&clkref>; 633 clock-names = "uart", "clk_uart_baud0"; 634 power-domains = <&ps_uart0>; 635 status = "disabled"; 636 }; 637 638 serial2: serial@235208000 { 639 compatible = "apple,s5l-uart"; 640 reg = <0x2 0x35208000 0x0 0x1000>; 641 reg-io-width = <4>; 642 interrupt-parent = <&aic>; 643 interrupts = <AIC_IRQ 607 IRQ_TYPE_LEVEL_HIGH>; 644 clocks = <&clkref>, <&clkref>; 645 clock-names = "uart", "clk_uart_baud0"; 646 power-domains = <&ps_uart2>; 647 status = "disabled"; 648 }; 649 650 admac: dma-controller@238200000 { 651 compatible = "apple,t8103-admac", "apple,admac"; 652 reg = <0x2 0x38200000 0x0 0x34000>; 653 dma-channels = <24>; 654 interrupts-extended = <0>, 655 <&aic AIC_IRQ 626 IRQ_TYPE_LEVEL_HIGH>, 656 <0>, 657 <0>; 658 #dma-cells = <1>; 659 iommus = <&sio_dart 2>; 660 power-domains = <&ps_sio_adma>; 661 resets = <&ps_audio_p>; 662 }; 663 664 mca: i2s@238400000 { 665 compatible = "apple,t8103-mca", "apple,mca"; 666 reg = <0x2 0x38400000 0x0 0x18000>, 667 <0x2 0x38300000 0x0 0x30000>; 668 669 interrupt-parent = <&aic>; 670 interrupts = <AIC_IRQ 619 IRQ_TYPE_LEVEL_HIGH>, 671 <AIC_IRQ 620 IRQ_TYPE_LEVEL_HIGH>, 672 <AIC_IRQ 621 IRQ_TYPE_LEVEL_HIGH>, 673 <AIC_IRQ 622 IRQ_TYPE_LEVEL_HIGH>, 674 <AIC_IRQ 623 IRQ_TYPE_LEVEL_HIGH>, 675 <AIC_IRQ 624 IRQ_TYPE_LEVEL_HIGH>; 676 677 resets = <&ps_audio_p>; 678 clocks = <&nco 0>, <&nco 1>, <&nco 2>, 679 <&nco 3>, <&nco 4>, <&nco 4>; 680 power-domains = <&ps_audio_p>, <&ps_mca0>, <&ps_mca1>, 681 <&ps_mca2>, <&ps_mca3>, <&ps_mca4>, <&ps_mca5>; 682 dmas = <&admac 0>, <&admac 1>, <&admac 2>, <&admac 3>, 683 <&admac 4>, <&admac 5>, <&admac 6>, <&admac 7>, 684 <&admac 8>, <&admac 9>, <&admac 10>, <&admac 11>, 685 <&admac 12>, <&admac 13>, <&admac 14>, <&admac 15>, 686 <&admac 16>, <&admac 17>, <&admac 18>, <&admac 19>, 687 <&admac 20>, <&admac 21>, <&admac 22>, <&admac 23>; 688 dma-names = "tx0a", "rx0a", "tx0b", "rx0b", 689 "tx1a", "rx1a", "tx1b", "rx1b", 690 "tx2a", "rx2a", "tx2b", "rx2b", 691 "tx3a", "rx3a", "tx3b", "rx3b", 692 "tx4a", "rx4a", "tx4b", "rx4b", 693 "tx5a", "rx5a", "tx5b", "rx5b"; 694 695 #sound-dai-cells = <1>; 696 }; 697 698 nco: clock-controller@23b044000 { 699 compatible = "apple,t8103-nco", "apple,nco"; 700 reg = <0x2 0x3b044000 0x0 0x14000>; 701 clocks = <&nco_clkref>; 702 #clock-cells = <1>; 703 }; 704 705 aic: interrupt-controller@23b100000 { 706 compatible = "apple,t8103-aic", "apple,aic"; 707 #interrupt-cells = <3>; 708 interrupt-controller; 709 reg = <0x2 0x3b100000 0x0 0x8000>; 710 power-domains = <&ps_aic>; 711 712 affinities { 713 e-core-pmu-affinity { 714 apple,fiq-index = <AIC_CPU_PMU_E>; 715 cpus = <&cpu_e0 &cpu_e1 &cpu_e2 &cpu_e3>; 716 }; 717 718 p-core-pmu-affinity { 719 apple,fiq-index = <AIC_CPU_PMU_P>; 720 cpus = <&cpu_p0 &cpu_p1 &cpu_p2 &cpu_p3>; 721 }; 722 }; 723 }; 724 725 pmgr: power-management@23b700000 { 726 compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd"; 727 #address-cells = <1>; 728 #size-cells = <1>; 729 reg = <0x2 0x3b700000 0 0x14000>; 730 }; 731 732 pinctrl_ap: pinctrl@23c100000 { 733 compatible = "apple,t8103-pinctrl", "apple,pinctrl"; 734 reg = <0x2 0x3c100000 0x0 0x100000>; 735 power-domains = <&ps_gpio>; 736 737 gpio-controller; 738 #gpio-cells = <2>; 739 gpio-ranges = <&pinctrl_ap 0 0 212>; 740 apple,npins = <212>; 741 742 interrupt-controller; 743 #interrupt-cells = <2>; 744 interrupt-parent = <&aic>; 745 interrupts = <AIC_IRQ 190 IRQ_TYPE_LEVEL_HIGH>, 746 <AIC_IRQ 191 IRQ_TYPE_LEVEL_HIGH>, 747 <AIC_IRQ 192 IRQ_TYPE_LEVEL_HIGH>, 748 <AIC_IRQ 193 IRQ_TYPE_LEVEL_HIGH>, 749 <AIC_IRQ 194 IRQ_TYPE_LEVEL_HIGH>, 750 <AIC_IRQ 195 IRQ_TYPE_LEVEL_HIGH>, 751 <AIC_IRQ 196 IRQ_TYPE_LEVEL_HIGH>; 752 753 i2c0_pins: i2c0-pins { 754 pinmux = <APPLE_PINMUX(192, 1)>, 755 <APPLE_PINMUX(188, 1)>; 756 }; 757 758 i2c1_pins: i2c1-pins { 759 pinmux = <APPLE_PINMUX(201, 1)>, 760 <APPLE_PINMUX(199, 1)>; 761 }; 762 763 i2c2_pins: i2c2-pins { 764 pinmux = <APPLE_PINMUX(163, 1)>, 765 <APPLE_PINMUX(162, 1)>; 766 }; 767 768 i2c3_pins: i2c3-pins { 769 pinmux = <APPLE_PINMUX(73, 1)>, 770 <APPLE_PINMUX(72, 1)>; 771 }; 772 773 i2c4_pins: i2c4-pins { 774 pinmux = <APPLE_PINMUX(135, 1)>, 775 <APPLE_PINMUX(134, 1)>; 776 }; 777 778 spi0_pins: spi0-pins { 779 pinmux = <APPLE_PINMUX(67, 1)>, /* CLK */ 780 <APPLE_PINMUX(68, 1)>, /* MOSI */ 781 <APPLE_PINMUX(69, 1)>; /* MISO */ 782 }; 783 784 spi1_pins: spi1-pins { 785 pinmux = <APPLE_PINMUX(42, 1)>, 786 <APPLE_PINMUX(43, 1)>, 787 <APPLE_PINMUX(44, 1)>, 788 <APPLE_PINMUX(45, 1)>; 789 }; 790 791 spi3_pins: spi3-pins { 792 pinmux = <APPLE_PINMUX(46, 1)>, 793 <APPLE_PINMUX(47, 1)>, 794 <APPLE_PINMUX(48, 1)>, 795 <APPLE_PINMUX(49, 1)>; 796 }; 797 798 pcie_pins: pcie-pins { 799 pinmux = <APPLE_PINMUX(150, 1)>, 800 <APPLE_PINMUX(151, 1)>, 801 <APPLE_PINMUX(32, 1)>; 802 }; 803 }; 804 805 nub_spmi: spmi@23d0d9300 { 806 compatible = "apple,t8103-spmi", "apple,spmi"; 807 reg = <0x2 0x3d0d9300 0x0 0x100>; 808 #address-cells = <2>; 809 #size-cells = <0>; 810 811 pmic1: pmic@f { 812 compatible = "apple,sera-pmic", "apple,spmi-nvmem"; 813 reg = <0xf SPMI_USID>; 814 815 nvmem-layout { 816 compatible = "fixed-layout"; 817 #address-cells = <1>; 818 #size-cells = <1>; 819 820 boot_stage: boot-stage@9f01 { 821 reg = <0x9f01 0x1>; 822 }; 823 824 boot_error_count: boot-error-count@9f02,0 { 825 reg = <0x9f02 0x1>; 826 bits = <0 4>; 827 }; 828 829 panic_count: panic-count@9f02,4 { 830 reg = <0x9f02 0x1>; 831 bits = <4 4>; 832 }; 833 834 boot_error_stage: boot-error-stage@9f03 { 835 reg = <0x9f03 0x1>; 836 }; 837 838 shutdown_flag: shutdown-flag@9f0f,3 { 839 reg = <0x9f0f 0x1>; 840 bits = <3 1>; 841 }; 842 843 fault_shadow: fault-shadow@a67b { 844 reg = <0xa67b 0x10>; 845 }; 846 847 socd: socd@ab00 { 848 reg = <0xab00 0x400>; 849 }; 850 851 pm_setting: pm-setting@d001 { 852 reg = <0xd001 0x1>; 853 }; 854 855 rtc_offset: rtc-offset@d100 { 856 reg = <0xd100 0x6>; 857 }; 858 }; 859 }; 860 }; 861 862 pinctrl_nub: pinctrl@23d1f0000 { 863 compatible = "apple,t8103-pinctrl", "apple,pinctrl"; 864 reg = <0x2 0x3d1f0000 0x0 0x4000>; 865 power-domains = <&ps_nub_gpio>; 866 867 gpio-controller; 868 #gpio-cells = <2>; 869 gpio-ranges = <&pinctrl_nub 0 0 23>; 870 apple,npins = <23>; 871 872 interrupt-controller; 873 #interrupt-cells = <2>; 874 interrupt-parent = <&aic>; 875 interrupts = <AIC_IRQ 330 IRQ_TYPE_LEVEL_HIGH>, 876 <AIC_IRQ 331 IRQ_TYPE_LEVEL_HIGH>, 877 <AIC_IRQ 332 IRQ_TYPE_LEVEL_HIGH>, 878 <AIC_IRQ 333 IRQ_TYPE_LEVEL_HIGH>, 879 <AIC_IRQ 334 IRQ_TYPE_LEVEL_HIGH>, 880 <AIC_IRQ 335 IRQ_TYPE_LEVEL_HIGH>, 881 <AIC_IRQ 336 IRQ_TYPE_LEVEL_HIGH>; 882 }; 883 884 pmgr_mini: power-management@23d280000 { 885 compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd"; 886 #address-cells = <1>; 887 #size-cells = <1>; 888 reg = <0x2 0x3d280000 0 0x4000>; 889 }; 890 891 wdt: watchdog@23d2b0000 { 892 compatible = "apple,t8103-wdt", "apple,wdt"; 893 reg = <0x2 0x3d2b0000 0x0 0x4000>; 894 clocks = <&clkref>; 895 interrupt-parent = <&aic>; 896 interrupts = <AIC_IRQ 338 IRQ_TYPE_LEVEL_HIGH>; 897 }; 898 899 smc: smc@23e400000 { 900 compatible = "apple,t8103-smc", "apple,smc"; 901 reg = <0x2 0x3e400000 0x0 0x4000>, 902 <0x2 0x3fe00000 0x0 0x100000>; 903 reg-names = "smc", "sram"; 904 mboxes = <&smc_mbox>; 905 906 smc_gpio: gpio { 907 compatible = "apple,smc-gpio"; 908 gpio-controller; 909 #gpio-cells = <2>; 910 }; 911 912 smc_reboot: reboot { 913 compatible = "apple,smc-reboot"; 914 nvmem-cells = <&shutdown_flag>, <&boot_stage>, 915 <&boot_error_count>, <&panic_count>; 916 nvmem-cell-names = "shutdown_flag", "boot_stage", 917 "boot_error_count", "panic_count"; 918 }; 919 }; 920 921 smc_mbox: mbox@23e408000 { 922 compatible = "apple,t8103-asc-mailbox", "apple,asc-mailbox-v4"; 923 reg = <0x2 0x3e408000 0x0 0x4000>; 924 interrupt-parent = <&aic>; 925 interrupts = <AIC_IRQ 400 IRQ_TYPE_LEVEL_HIGH>, 926 <AIC_IRQ 401 IRQ_TYPE_LEVEL_HIGH>, 927 <AIC_IRQ 402 IRQ_TYPE_LEVEL_HIGH>, 928 <AIC_IRQ 403 IRQ_TYPE_LEVEL_HIGH>; 929 interrupt-names = "send-empty", "send-not-empty", 930 "recv-empty", "recv-not-empty"; 931 #mbox-cells = <0>; 932 }; 933 934 pinctrl_smc: pinctrl@23e820000 { 935 compatible = "apple,t8103-pinctrl", "apple,pinctrl"; 936 reg = <0x2 0x3e820000 0x0 0x4000>; 937 938 gpio-controller; 939 #gpio-cells = <2>; 940 gpio-ranges = <&pinctrl_smc 0 0 16>; 941 apple,npins = <16>; 942 943 interrupt-controller; 944 #interrupt-cells = <2>; 945 interrupt-parent = <&aic>; 946 interrupts = <AIC_IRQ 391 IRQ_TYPE_LEVEL_HIGH>, 947 <AIC_IRQ 392 IRQ_TYPE_LEVEL_HIGH>, 948 <AIC_IRQ 393 IRQ_TYPE_LEVEL_HIGH>, 949 <AIC_IRQ 394 IRQ_TYPE_LEVEL_HIGH>, 950 <AIC_IRQ 395 IRQ_TYPE_LEVEL_HIGH>, 951 <AIC_IRQ 396 IRQ_TYPE_LEVEL_HIGH>, 952 <AIC_IRQ 397 IRQ_TYPE_LEVEL_HIGH>; 953 }; 954 955 pinctrl_aop: pinctrl@24a820000 { 956 compatible = "apple,t8103-pinctrl", "apple,pinctrl"; 957 reg = <0x2 0x4a820000 0x0 0x4000>; 958 959 gpio-controller; 960 #gpio-cells = <2>; 961 gpio-ranges = <&pinctrl_aop 0 0 42>; 962 apple,npins = <42>; 963 964 interrupt-controller; 965 #interrupt-cells = <2>; 966 interrupt-parent = <&aic>; 967 interrupts = <AIC_IRQ 268 IRQ_TYPE_LEVEL_HIGH>, 968 <AIC_IRQ 269 IRQ_TYPE_LEVEL_HIGH>, 969 <AIC_IRQ 270 IRQ_TYPE_LEVEL_HIGH>, 970 <AIC_IRQ 271 IRQ_TYPE_LEVEL_HIGH>, 971 <AIC_IRQ 272 IRQ_TYPE_LEVEL_HIGH>, 972 <AIC_IRQ 273 IRQ_TYPE_LEVEL_HIGH>, 973 <AIC_IRQ 274 IRQ_TYPE_LEVEL_HIGH>; 974 }; 975 976 ans_mbox: mbox@277408000 { 977 compatible = "apple,t8103-asc-mailbox", "apple,asc-mailbox-v4"; 978 reg = <0x2 0x77408000 0x0 0x4000>; 979 interrupt-parent = <&aic>; 980 interrupts = <AIC_IRQ 583 IRQ_TYPE_LEVEL_HIGH>, 981 <AIC_IRQ 584 IRQ_TYPE_LEVEL_HIGH>, 982 <AIC_IRQ 585 IRQ_TYPE_LEVEL_HIGH>, 983 <AIC_IRQ 586 IRQ_TYPE_LEVEL_HIGH>; 984 interrupt-names = "send-empty", "send-not-empty", 985 "recv-empty", "recv-not-empty"; 986 #mbox-cells = <0>; 987 power-domains = <&ps_ans2>; 988 }; 989 990 sart: iommu@27bc50000 { 991 compatible = "apple,t8103-sart"; 992 reg = <0x2 0x7bc50000 0x0 0x10000>; 993 power-domains = <&ps_ans2>; 994 }; 995 996 nvme@27bcc0000 { 997 compatible = "apple,t8103-nvme-ans2", "apple,nvme-ans2"; 998 reg = <0x2 0x7bcc0000 0x0 0x40000>, 999 <0x2 0x77400000 0x0 0x4000>; 1000 reg-names = "nvme", "ans"; 1001 interrupt-parent = <&aic>; 1002 interrupts = <AIC_IRQ 590 IRQ_TYPE_LEVEL_HIGH>; 1003 mboxes = <&ans_mbox>; 1004 apple,sart = <&sart>; 1005 power-domains = <&ps_ans2>, <&ps_apcie_st>; 1006 power-domain-names = "ans", "apcie0"; 1007 resets = <&ps_ans2>; 1008 }; 1009 1010 pcie0_dart_0: iommu@681008000 { 1011 compatible = "apple,t8103-dart"; 1012 reg = <0x6 0x81008000 0x0 0x4000>; 1013 #iommu-cells = <1>; 1014 interrupt-parent = <&aic>; 1015 interrupts = <AIC_IRQ 696 IRQ_TYPE_LEVEL_HIGH>; 1016 power-domains = <&ps_apcie_gp>; 1017 }; 1018 1019 pcie0_dart_1: iommu@682008000 { 1020 compatible = "apple,t8103-dart"; 1021 reg = <0x6 0x82008000 0x0 0x4000>; 1022 #iommu-cells = <1>; 1023 interrupt-parent = <&aic>; 1024 interrupts = <AIC_IRQ 699 IRQ_TYPE_LEVEL_HIGH>; 1025 power-domains = <&ps_apcie_gp>; 1026 status = "disabled"; 1027 }; 1028 1029 pcie0_dart_2: iommu@683008000 { 1030 compatible = "apple,t8103-dart"; 1031 reg = <0x6 0x83008000 0x0 0x4000>; 1032 #iommu-cells = <1>; 1033 interrupt-parent = <&aic>; 1034 interrupts = <AIC_IRQ 702 IRQ_TYPE_LEVEL_HIGH>; 1035 power-domains = <&ps_apcie_gp>; 1036 status = "disabled"; 1037 }; 1038 1039 pcie0: pcie@690000000 { 1040 compatible = "apple,t8103-pcie", "apple,pcie"; 1041 device_type = "pci"; 1042 1043 reg = <0x6 0x90000000 0x0 0x1000000>, 1044 <0x6 0x80000000 0x0 0x100000>, 1045 <0x6 0x81000000 0x0 0x4000>, 1046 <0x6 0x82000000 0x0 0x4000>, 1047 <0x6 0x83000000 0x0 0x4000>; 1048 reg-names = "config", "rc", "port0", "port1", "port2"; 1049 1050 interrupt-parent = <&aic>; 1051 interrupts = <AIC_IRQ 695 IRQ_TYPE_LEVEL_HIGH>, 1052 <AIC_IRQ 698 IRQ_TYPE_LEVEL_HIGH>, 1053 <AIC_IRQ 701 IRQ_TYPE_LEVEL_HIGH>; 1054 1055 msi-controller; 1056 msi-parent = <&pcie0>; 1057 msi-ranges = <&aic AIC_IRQ 704 IRQ_TYPE_EDGE_RISING 32>; 1058 1059 1060 iommu-map = <0x100 &pcie0_dart_0 1 1>, 1061 <0x200 &pcie0_dart_1 1 1>, 1062 <0x300 &pcie0_dart_2 1 1>; 1063 iommu-map-mask = <0xff00>; 1064 1065 bus-range = <0 3>; 1066 #address-cells = <3>; 1067 #size-cells = <2>; 1068 ranges = <0x43000000 0x6 0xa0000000 0x6 0xa0000000 0x0 0x20000000>, 1069 <0x02000000 0x0 0xc0000000 0x6 0xc0000000 0x0 0x40000000>; 1070 1071 power-domains = <&ps_apcie_gp>; 1072 pinctrl-0 = <&pcie_pins>; 1073 pinctrl-names = "default"; 1074 1075 port00: pci@0,0 { 1076 device_type = "pci"; 1077 reg = <0x0 0x0 0x0 0x0 0x0>; 1078 reset-gpios = <&pinctrl_ap 152 GPIO_ACTIVE_LOW>; 1079 1080 #address-cells = <3>; 1081 #size-cells = <2>; 1082 ranges; 1083 1084 interrupt-controller; 1085 #interrupt-cells = <1>; 1086 1087 interrupt-map-mask = <0 0 0 7>; 1088 interrupt-map = <0 0 0 1 &port00 0 0 0 0>, 1089 <0 0 0 2 &port00 0 0 0 1>, 1090 <0 0 0 3 &port00 0 0 0 2>, 1091 <0 0 0 4 &port00 0 0 0 3>; 1092 }; 1093 1094 port01: pci@1,0 { 1095 device_type = "pci"; 1096 reg = <0x800 0x0 0x0 0x0 0x0>; 1097 reset-gpios = <&pinctrl_ap 153 GPIO_ACTIVE_LOW>; 1098 1099 #address-cells = <3>; 1100 #size-cells = <2>; 1101 ranges; 1102 1103 interrupt-controller; 1104 #interrupt-cells = <1>; 1105 1106 interrupt-map-mask = <0 0 0 7>; 1107 interrupt-map = <0 0 0 1 &port01 0 0 0 0>, 1108 <0 0 0 2 &port01 0 0 0 1>, 1109 <0 0 0 3 &port01 0 0 0 2>, 1110 <0 0 0 4 &port01 0 0 0 3>; 1111 status = "disabled"; 1112 }; 1113 1114 port02: pci@2,0 { 1115 device_type = "pci"; 1116 reg = <0x1000 0x0 0x0 0x0 0x0>; 1117 reset-gpios = <&pinctrl_ap 33 GPIO_ACTIVE_LOW>; 1118 1119 #address-cells = <3>; 1120 #size-cells = <2>; 1121 ranges; 1122 1123 interrupt-controller; 1124 #interrupt-cells = <1>; 1125 1126 interrupt-map-mask = <0 0 0 7>; 1127 interrupt-map = <0 0 0 1 &port02 0 0 0 0>, 1128 <0 0 0 2 &port02 0 0 0 1>, 1129 <0 0 0 3 &port02 0 0 0 2>, 1130 <0 0 0 4 &port02 0 0 0 3>; 1131 status = "disabled"; 1132 }; 1133 }; 1134 }; 1135}; 1136 1137#include "t8103-pmgr.dtsi"
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