t6002.dtsi

  1// SPDX-License-Identifier: GPL-2.0+ OR MIT
  2/*
  3 * Apple T6002 "M1 Ultra" SoC
  4 *
  5 * Other names: H13J, "Jade 2C"
  6 *
  7 * Copyright The Asahi Linux Contributors
  8 */
  9
 10#include <dt-bindings/gpio/gpio.h>
 11#include <dt-bindings/interrupt-controller/apple-aic.h>
 12#include <dt-bindings/interrupt-controller/irq.h>
 13#include <dt-bindings/pinctrl/apple.h>
 14#include <dt-bindings/spmi/spmi.h>
 15
 16#include "multi-die-cpp.h"
 17
 18#include "t600x-common.dtsi"
 19
 20/ {
 21	compatible = "apple,t6002", "apple,arm-platform";
 22
 23	#address-cells = <2>;
 24	#size-cells = <2>;
 25
 26	cpus {
 27		cpu-map {
 28			cluster3 {
 29				core0 {
 30					cpu = <&cpu_e10>;
 31				};
 32				core1 {
 33					cpu = <&cpu_e11>;
 34				};
 35			};
 36
 37			cluster4 {
 38				core0 {
 39					cpu = <&cpu_p20>;
 40				};
 41				core1 {
 42					cpu = <&cpu_p21>;
 43				};
 44				core2 {
 45					cpu = <&cpu_p22>;
 46				};
 47				core3 {
 48					cpu = <&cpu_p23>;
 49				};
 50			};
 51
 52			cluster5 {
 53				core0 {
 54					cpu = <&cpu_p30>;
 55				};
 56				core1 {
 57					cpu = <&cpu_p31>;
 58				};
 59				core2 {
 60					cpu = <&cpu_p32>;
 61				};
 62				core3 {
 63					cpu = <&cpu_p33>;
 64				};
 65			};
 66		};
 67
 68		cpu_e10: cpu@800 {
 69			compatible = "apple,icestorm";
 70			device_type = "cpu";
 71			reg = <0x0 0x800>;
 72			enable-method = "spin-table";
 73			cpu-release-addr = <0 0>; /* To be filled by loader */
 74			next-level-cache = <&l2_cache_3>;
 75			i-cache-size = <0x20000>;
 76			d-cache-size = <0x10000>;
 77			operating-points-v2 = <&icestorm_opp>;
 78			capacity-dmips-mhz = <714>;
 79			performance-domains = <&cpufreq_e_die1>;
 80		};
 81
 82		cpu_e11: cpu@801 {
 83			compatible = "apple,icestorm";
 84			device_type = "cpu";
 85			reg = <0x0 0x801>;
 86			enable-method = "spin-table";
 87			cpu-release-addr = <0 0>; /* To be filled by loader */
 88			next-level-cache = <&l2_cache_3>;
 89			i-cache-size = <0x20000>;
 90			d-cache-size = <0x10000>;
 91			operating-points-v2 = <&icestorm_opp>;
 92			capacity-dmips-mhz = <714>;
 93			performance-domains = <&cpufreq_e_die1>;
 94		};
 95
 96		cpu_p20: cpu@10900 {
 97			compatible = "apple,firestorm";
 98			device_type = "cpu";
 99			reg = <0x0 0x10900>;
100			enable-method = "spin-table";
101			cpu-release-addr = <0 0>; /* To be filled by loader */
102			next-level-cache = <&l2_cache_4>;
103			i-cache-size = <0x30000>;
104			d-cache-size = <0x20000>;
105			operating-points-v2 = <&firestorm_opp>;
106			capacity-dmips-mhz = <1024>;
107			performance-domains = <&cpufreq_p0_die1>;
108		};
109
110		cpu_p21: cpu@10901 {
111			compatible = "apple,firestorm";
112			device_type = "cpu";
113			reg = <0x0 0x10901>;
114			enable-method = "spin-table";
115			cpu-release-addr = <0 0>; /* To be filled by loader */
116			next-level-cache = <&l2_cache_4>;
117			i-cache-size = <0x30000>;
118			d-cache-size = <0x20000>;
119			operating-points-v2 = <&firestorm_opp>;
120			capacity-dmips-mhz = <1024>;
121			performance-domains = <&cpufreq_p0_die1>;
122		};
123
124		cpu_p22: cpu@10902 {
125			compatible = "apple,firestorm";
126			device_type = "cpu";
127			reg = <0x0 0x10902>;
128			enable-method = "spin-table";
129			cpu-release-addr = <0 0>; /* To be filled by loader */
130			next-level-cache = <&l2_cache_4>;
131			i-cache-size = <0x30000>;
132			d-cache-size = <0x20000>;
133			operating-points-v2 = <&firestorm_opp>;
134			capacity-dmips-mhz = <1024>;
135			performance-domains = <&cpufreq_p0_die1>;
136		};
137
138		cpu_p23: cpu@10903 {
139			compatible = "apple,firestorm";
140			device_type = "cpu";
141			reg = <0x0 0x10903>;
142			enable-method = "spin-table";
143			cpu-release-addr = <0 0>; /* To be filled by loader */
144			next-level-cache = <&l2_cache_4>;
145			i-cache-size = <0x30000>;
146			d-cache-size = <0x20000>;
147			operating-points-v2 = <&firestorm_opp>;
148			capacity-dmips-mhz = <1024>;
149			performance-domains = <&cpufreq_p0_die1>;
150		};
151
152		cpu_p30: cpu@10a00 {
153			compatible = "apple,firestorm";
154			device_type = "cpu";
155			reg = <0x0 0x10a00>;
156			enable-method = "spin-table";
157			cpu-release-addr = <0 0>; /* To be filled by loader */
158			next-level-cache = <&l2_cache_5>;
159			i-cache-size = <0x30000>;
160			d-cache-size = <0x20000>;
161			operating-points-v2 = <&firestorm_opp>;
162			capacity-dmips-mhz = <1024>;
163			performance-domains = <&cpufreq_p1_die1>;
164		};
165
166		cpu_p31: cpu@10a01 {
167			compatible = "apple,firestorm";
168			device_type = "cpu";
169			reg = <0x0 0x10a01>;
170			enable-method = "spin-table";
171			cpu-release-addr = <0 0>; /* To be filled by loader */
172			next-level-cache = <&l2_cache_5>;
173			i-cache-size = <0x30000>;
174			d-cache-size = <0x20000>;
175			operating-points-v2 = <&firestorm_opp>;
176			capacity-dmips-mhz = <1024>;
177			performance-domains = <&cpufreq_p1_die1>;
178		};
179
180		cpu_p32: cpu@10a02 {
181			compatible = "apple,firestorm";
182			device_type = "cpu";
183			reg = <0x0 0x10a02>;
184			enable-method = "spin-table";
185			cpu-release-addr = <0 0>; /* To be filled by loader */
186			next-level-cache = <&l2_cache_5>;
187			i-cache-size = <0x30000>;
188			d-cache-size = <0x20000>;
189			operating-points-v2 = <&firestorm_opp>;
190			capacity-dmips-mhz = <1024>;
191			performance-domains = <&cpufreq_p1_die1>;
192		};
193
194		cpu_p33: cpu@10a03 {
195			compatible = "apple,firestorm";
196			device_type = "cpu";
197			reg = <0x0 0x10a03>;
198			enable-method = "spin-table";
199			cpu-release-addr = <0 0>; /* To be filled by loader */
200			next-level-cache = <&l2_cache_5>;
201			i-cache-size = <0x30000>;
202			d-cache-size = <0x20000>;
203			operating-points-v2 = <&firestorm_opp>;
204			capacity-dmips-mhz = <1024>;
205			performance-domains = <&cpufreq_p1_die1>;
206		};
207
208		l2_cache_3: l2-cache-3 {
209			compatible = "cache";
210			cache-level = <2>;
211			cache-unified;
212			cache-size = <0x400000>;
213		};
214
215		l2_cache_4: l2-cache-4 {
216			compatible = "cache";
217			cache-level = <2>;
218			cache-unified;
219			cache-size = <0xc00000>;
220		};
221
222		l2_cache_5: l2-cache-5 {
223			compatible = "cache";
224			cache-level = <2>;
225			cache-unified;
226			cache-size = <0xc00000>;
227		};
228	};
229
230	die0: soc@200000000 {
231		compatible = "simple-bus";
232		#address-cells = <2>;
233		#size-cells = <2>;
234		ranges = <0x2 0x0 0x2 0x0 0x4 0x0>,
235			 <0x5 0x80000000 0x5 0x80000000 0x1 0x80000000>,
236			 <0x7 0x0 0x7 0x0 0xf 0x80000000>;
237		nonposted-mmio;
238
239		// filled via templated includes at the end of the file
240	};
241
242	die1: soc@2200000000 {
243		compatible = "simple-bus";
244		#address-cells = <2>;
245		#size-cells = <2>;
246		ranges = <0x2 0x0 0x22 0x0 0x4 0x0>,
247			 <0x7 0x0 0x27 0x0 0xf 0x80000000>;
248		nonposted-mmio;
249
250		// filled via templated includes at the end of the file
251	};
252};
253
254#define DIE
255#define DIE_NO 0
256
257&die0 {
258	#include "t600x-die0.dtsi"
259	#include "t600x-dieX.dtsi"
260};
261
262#include "t600x-pmgr.dtsi"
263#include "t600x-gpio-pins.dtsi"
264
265#undef DIE
266#undef DIE_NO
267
268#define DIE _die1
269#define DIE_NO 1
270
271&die1 {
272	#include "t600x-dieX.dtsi"
273	#include "t600x-nvme.dtsi"
274};
275
276#include "t600x-pmgr.dtsi"
277
278#undef DIE
279#undef DIE_NO
280
281&aic {
282	affinities {
283		e-core-pmu-affinity {
284			apple,fiq-index = <AIC_CPU_PMU_E>;
285			cpus = <&cpu_e00 &cpu_e01
286				&cpu_e10 &cpu_e11>;
287		};
288
289		p-core-pmu-affinity {
290			apple,fiq-index = <AIC_CPU_PMU_P>;
291			cpus = <&cpu_p00 &cpu_p01 &cpu_p02 &cpu_p03
292				&cpu_p10 &cpu_p11 &cpu_p12 &cpu_p13
293				&cpu_p20 &cpu_p21 &cpu_p22 &cpu_p23
294				&cpu_p30 &cpu_p31 &cpu_p32 &cpu_p33>;
295		};
296	};
297};
298
299&ps_gfx {
300	// On t6002, the die0 GPU power domain needs both AFR power domains
301	power-domains = <&ps_afr>, <&ps_afr_die1>;
302};
303
304&gpu {
305	compatible = "apple,agx-g13d", "apple,agx-g13s";
306};