s800-0-3.dtsi

  1// SPDX-License-Identifier: GPL-2.0+ OR MIT
  2/*
  3 * Apple S8000/S8003 "A9" SoC
  4 *
  5 * This file contains parts common to both variants of A9
  6 *
  7 * Copyright (c) 2022, Konrad Dybcio <konradybcio@kernel.org>
  8 */
  9
 10#include <dt-bindings/gpio/gpio.h>
 11#include <dt-bindings/interrupt-controller/apple-aic.h>
 12#include <dt-bindings/interrupt-controller/irq.h>
 13#include <dt-bindings/pinctrl/apple.h>
 14
 15/ {
 16	interrupt-parent = <&aic>;
 17	#address-cells = <2>;
 18	#size-cells = <2>;
 19
 20	clkref: clock-ref {
 21		compatible = "fixed-clock";
 22		#clock-cells = <0>;
 23		clock-frequency = <24000000>;
 24		clock-output-names = "clkref";
 25	};
 26
 27	cpus {
 28		#address-cells = <2>;
 29		#size-cells = <0>;
 30
 31		cpu0: cpu@0 {
 32			compatible = "apple,twister";
 33			reg = <0x0 0x0>;
 34			cpu-release-addr = <0 0>; /* To be filled in by loader */
 35			operating-points-v2 = <&twister_opp>;
 36			performance-domains = <&cpufreq>;
 37			enable-method = "spin-table";
 38			device_type = "cpu";
 39			next-level-cache = <&l2_cache>;
 40			i-cache-size = <0x10000>;
 41			d-cache-size = <0x10000>;
 42		};
 43
 44		cpu1: cpu@1 {
 45			compatible = "apple,twister";
 46			reg = <0x0 0x1>;
 47			cpu-release-addr = <0 0>; /* To be filled in by loader */
 48			operating-points-v2 = <&twister_opp>;
 49			performance-domains = <&cpufreq>;
 50			enable-method = "spin-table";
 51			device_type = "cpu";
 52			next-level-cache = <&l2_cache>;
 53			i-cache-size = <0x10000>;
 54			d-cache-size = <0x10000>;
 55		};
 56
 57		l2_cache: l2-cache {
 58			compatible = "cache";
 59			cache-level = <2>;
 60			cache-unified;
 61			cache-size = <0x300000>;
 62		};
 63	};
 64
 65	soc {
 66		compatible = "simple-bus";
 67		#address-cells = <2>;
 68		#size-cells = <2>;
 69		nonposted-mmio;
 70		ranges;
 71
 72		cpufreq: performance-controller@202220000 {
 73			compatible = "apple,s8000-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
 74			reg = <0x2 0x02220000 0 0x1000>;
 75			#performance-domain-cells = <0>;
 76		};
 77
 78		serial0: serial@20a0c0000 {
 79			compatible = "apple,s5l-uart";
 80			reg = <0x2 0x0a0c0000 0x0 0x4000>;
 81			reg-io-width = <4>;
 82			interrupt-parent = <&aic>;
 83			interrupts = <AIC_IRQ 192 IRQ_TYPE_LEVEL_HIGH>;
 84			/* Use the bootloader-enabled clocks for now. */
 85			clocks = <&clkref>, <&clkref>;
 86			clock-names = "uart", "clk_uart_baud0";
 87			power-domains = <&ps_uart0>;
 88			status = "disabled";
 89		};
 90
 91		i2c0: i2c@20a110000 {
 92			compatible = "apple,s8000-i2c", "apple,i2c";
 93			reg = <0x2 0x0a110000 0x0 0x1000>;
 94			clocks = <&clkref>;
 95			interrupt-parent = <&aic>;
 96			interrupts = <AIC_IRQ 206 IRQ_TYPE_LEVEL_HIGH>;
 97			pinctrl-0 = <&i2c0_pins>;
 98			pinctrl-names = "default";
 99			power-domains = <&ps_i2c0>;
100			#address-cells = <1>;
101			#size-cells = <0>;
102			status = "disabled";
103		};
104
105		i2c1: i2c@20a111000 {
106			compatible = "apple,s8000-i2c", "apple,i2c";
107			reg = <0x2 0x0a111000 0x0 0x1000>;
108			clocks = <&clkref>;
109			interrupt-parent = <&aic>;
110			interrupts = <AIC_IRQ 207 IRQ_TYPE_LEVEL_HIGH>;
111			pinctrl-0 = <&i2c1_pins>;
112			pinctrl-names = "default";
113			power-domains = <&ps_i2c1>;
114			#address-cells = <1>;
115			#size-cells = <0>;
116			status = "disabled";
117		};
118
119		i2c2: i2c@20a112000 {
120			compatible = "apple,s8000-i2c", "apple,i2c";
121			reg = <0x2 0x0a112000 0x0 0x1000>;
122			clocks = <&clkref>;
123			interrupt-parent = <&aic>;
124			interrupts = <AIC_IRQ 208 IRQ_TYPE_LEVEL_HIGH>;
125			pinctrl-0 = <&i2c2_pins>;
126			pinctrl-names = "default";
127			power-domains = <&ps_i2c2>;
128			#address-cells = <1>;
129			#size-cells = <0>;
130			status = "disabled";
131		};
132
133		pmgr: power-management@20e000000 {
134			compatible = "apple,s8000-pmgr", "apple,pmgr", "syscon", "simple-mfd";
135			#address-cells = <1>;
136			#size-cells = <1>;
137
138			reg = <0x2 0xe000000 0 0x8c000>;
139		};
140
141		aic: interrupt-controller@20e100000 {
142			compatible = "apple,s8000-aic", "apple,aic";
143			reg = <0x2 0x0e100000 0x0 0x100000>;
144			#interrupt-cells = <3>;
145			interrupt-controller;
146			power-domains = <&ps_aic>;
147		};
148
149		dwi_bl: backlight@20e200080 {
150			compatible = "apple,s8000-dwi-bl", "apple,dwi-bl";
151			reg = <0x2 0x0e200080 0x0 0x8>;
152			power-domains = <&ps_dwi>;
153			status = "disabled";
154		};
155
156		pinctrl_ap: pinctrl@20f100000 {
157			compatible = "apple,s8000-pinctrl", "apple,pinctrl";
158			reg = <0x2 0x0f100000 0x0 0x100000>;
159			power-domains = <&ps_gpio>;
160
161			gpio-controller;
162			#gpio-cells = <2>;
163			gpio-ranges = <&pinctrl_ap 0 0 208>;
164			apple,npins = <208>;
165
166			interrupt-controller;
167			#interrupt-cells = <2>;
168			interrupt-parent = <&aic>;
169			interrupts = <AIC_IRQ 42 IRQ_TYPE_LEVEL_HIGH>,
170				     <AIC_IRQ 43 IRQ_TYPE_LEVEL_HIGH>,
171				     <AIC_IRQ 44 IRQ_TYPE_LEVEL_HIGH>,
172				     <AIC_IRQ 45 IRQ_TYPE_LEVEL_HIGH>,
173				     <AIC_IRQ 46 IRQ_TYPE_LEVEL_HIGH>,
174				     <AIC_IRQ 47 IRQ_TYPE_LEVEL_HIGH>,
175				     <AIC_IRQ 48 IRQ_TYPE_LEVEL_HIGH>;
176
177			i2c0_pins: i2c0-pins {
178				pinmux = <APPLE_PINMUX(46, 1)>,
179					 <APPLE_PINMUX(45, 1)>;
180			};
181
182			i2c1_pins: i2c1-pins {
183				pinmux = <APPLE_PINMUX(115, 1)>,
184					 <APPLE_PINMUX(114, 1)>;
185			};
186
187			i2c2_pins: i2c2-pins {
188				pinmux = <APPLE_PINMUX(23, 1)>,
189					 <APPLE_PINMUX(22, 1)>;
190			};
191		};
192
193		pinctrl_aop: pinctrl@2100f0000 {
194			compatible = "apple,s8000-pinctrl", "apple,pinctrl";
195			reg = <0x2 0x100f0000 0x0 0x100000>;
196			power-domains = <&ps_aop_gpio>;
197
198			gpio-controller;
199			#gpio-cells = <2>;
200			gpio-ranges = <&pinctrl_aop 0 0 42>;
201			apple,npins = <42>;
202
203			interrupt-controller;
204			#interrupt-cells = <2>;
205			interrupt-parent = <&aic>;
206			interrupts = <AIC_IRQ 113 IRQ_TYPE_LEVEL_HIGH>,
207				     <AIC_IRQ 114 IRQ_TYPE_LEVEL_HIGH>,
208				     <AIC_IRQ 115 IRQ_TYPE_LEVEL_HIGH>,
209				     <AIC_IRQ 116 IRQ_TYPE_LEVEL_HIGH>,
210				     <AIC_IRQ 117 IRQ_TYPE_LEVEL_HIGH>,
211				     <AIC_IRQ 118 IRQ_TYPE_LEVEL_HIGH>,
212				     <AIC_IRQ 119 IRQ_TYPE_LEVEL_HIGH>;
213		};
214
215		pmgr_mini: power-management@210200000 {
216			compatible = "apple,s8000-pmgr", "apple,pmgr", "syscon", "simple-mfd";
217			#address-cells = <1>;
218			#size-cells = <1>;
219
220			reg = <0x2 0x10200000 0 0x84000>;
221		};
222
223		wdt: watchdog@2102b0000 {
224			compatible = "apple,s8000-wdt", "apple,wdt";
225			reg = <0x2 0x102b0000 0x0 0x4000>;
226			clocks = <&clkref>;
227			interrupt-parent = <&aic>;
228			interrupts = <AIC_IRQ 4 IRQ_TYPE_LEVEL_HIGH>;
229		};
230	};
231
232	timer {
233		compatible = "arm,armv8-timer";
234		interrupt-parent = <&aic>;
235		interrupt-names = "phys", "virt";
236		/* Note that A9 doesn't actually have a hypervisor (EL2 is not implemented). */
237		interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>,
238			     <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>;
239	};
240};
241
242#include "s800-0-3-pmgr.dtsi"
243
244/*
245 * The A9 was made by two separate fabs on two different process
246 * nodes: Samsung made the S8000 (APL0898) on 14nm and TSMC made
247 * the S8003 (APL1022) on 16nm. There are some minor differences
248 * such as timing in cpufreq state transistions.
249 */