meson-g12a.dtsi

  1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2/*
  3 * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
  4 */
  5
  6#include "meson-g12.dtsi"
  7
  8/ {
  9	compatible = "amlogic,g12a";
 10
 11	cpus {
 12		#address-cells = <0x2>;
 13		#size-cells = <0x0>;
 14
 15		cpu0: cpu@0 {
 16			device_type = "cpu";
 17			compatible = "arm,cortex-a53";
 18			reg = <0x0 0x0>;
 19			enable-method = "psci";
 20			d-cache-line-size = <32>;
 21			d-cache-size = <0x8000>;
 22			d-cache-sets = <32>;
 23			i-cache-line-size = <32>;
 24			i-cache-size = <0x8000>;
 25			i-cache-sets = <32>;
 26			next-level-cache = <&l2>;
 27			#cooling-cells = <2>;
 28		};
 29
 30		cpu1: cpu@1 {
 31			device_type = "cpu";
 32			compatible = "arm,cortex-a53";
 33			reg = <0x0 0x1>;
 34			enable-method = "psci";
 35			d-cache-line-size = <32>;
 36			d-cache-size = <0x8000>;
 37			d-cache-sets = <32>;
 38			i-cache-line-size = <32>;
 39			i-cache-size = <0x8000>;
 40			i-cache-sets = <32>;
 41			next-level-cache = <&l2>;
 42			#cooling-cells = <2>;
 43		};
 44
 45		cpu2: cpu@2 {
 46			device_type = "cpu";
 47			compatible = "arm,cortex-a53";
 48			reg = <0x0 0x2>;
 49			enable-method = "psci";
 50			d-cache-line-size = <32>;
 51			d-cache-size = <0x8000>;
 52			d-cache-sets = <32>;
 53			i-cache-line-size = <32>;
 54			i-cache-size = <0x8000>;
 55			i-cache-sets = <32>;
 56			next-level-cache = <&l2>;
 57			#cooling-cells = <2>;
 58		};
 59
 60		cpu3: cpu@3 {
 61			device_type = "cpu";
 62			compatible = "arm,cortex-a53";
 63			reg = <0x0 0x3>;
 64			enable-method = "psci";
 65			d-cache-line-size = <32>;
 66			d-cache-size = <0x8000>;
 67			d-cache-sets = <32>;
 68			i-cache-line-size = <32>;
 69			i-cache-size = <0x8000>;
 70			i-cache-sets = <32>;
 71			next-level-cache = <&l2>;
 72			#cooling-cells = <2>;
 73		};
 74
 75		l2: l2-cache0 {
 76			compatible = "cache";
 77			cache-level = <2>;
 78			cache-unified;
 79			cache-size = <0x80000>; /* L2. 512 KB */
 80			cache-line-size = <64>;
 81			cache-sets = <512>;
 82		};
 83	};
 84
 85	cpu_opp_table: opp-table {
 86		compatible = "operating-points-v2";
 87		opp-shared;
 88
 89		opp-1000000000 {
 90			opp-hz = /bits/ 64 <1000000000>;
 91			opp-microvolt = <731000>;
 92			clock-latency-ns = <50000>;
 93		};
 94
 95		opp-1200000000 {
 96			opp-hz = /bits/ 64 <1200000000>;
 97			opp-microvolt = <731000>;
 98		};
 99
100		opp-1398000000 {
101			opp-hz = /bits/ 64 <1398000000>;
102			opp-microvolt = <761000>;
103		};
104
105		opp-1512000000 {
106			opp-hz = /bits/ 64 <1512000000>;
107			opp-microvolt = <791000>;
108		};
109
110		opp-1608000000 {
111			opp-hz = /bits/ 64 <1608000000>;
112			opp-microvolt = <831000>;
113		};
114
115		opp-1704000000 {
116			opp-hz = /bits/ 64 <1704000000>;
117			opp-microvolt = <861000>;
118		};
119
120		opp-1800000000 {
121			opp-hz = /bits/ 64 <1800000000>;
122			opp-microvolt = <981000>;
123		};
124	};
125};
126
127&cpu_thermal {
128	cooling-maps {
129		map0 {
130			trip = <&cpu_passive>;
131			cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
132					<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
133					<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
134					<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
135		};
136
137		map1 {
138			trip = <&cpu_hot>;
139			cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
140					<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
141					<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
142					<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
143		};
144	};
145};
146
147&pmu {
148	compatible = "amlogic,g12a-ddr-pmu";
149};