amlogic-s7.dtsi

  1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2/*
  3 * Copyright (c) 2025 Amlogic, Inc. All rights reserved.
  4 */
  5
  6#include <dt-bindings/interrupt-controller/irq.h>
  7#include <dt-bindings/interrupt-controller/arm-gic.h>
  8#include <dt-bindings/gpio/gpio.h>
  9#include <dt-bindings/pinctrl/amlogic,pinctrl.h>
 10#include <dt-bindings/power/amlogic,s7-pwrc.h>
 11
 12/ {
 13	cpus {
 14		#address-cells = <2>;
 15		#size-cells = <0>;
 16
 17		cpu0: cpu@0 {
 18			device_type = "cpu";
 19			compatible = "arm,cortex-a55";
 20			reg = <0x0 0x0>;
 21			enable-method = "psci";
 22			d-cache-line-size = <32>;
 23			d-cache-size = <0x8000>;
 24			d-cache-sets = <32>;
 25			i-cache-line-size = <32>;
 26			i-cache-size = <0x8000>;
 27			i-cache-sets = <32>;
 28			next-level-cache = <&l2>;
 29		};
 30
 31		cpu1: cpu@100 {
 32			device_type = "cpu";
 33			compatible = "arm,cortex-a55";
 34			reg = <0x0 0x100>;
 35			enable-method = "psci";
 36			d-cache-line-size = <32>;
 37			d-cache-size = <0x8000>;
 38			d-cache-sets = <32>;
 39			i-cache-line-size = <32>;
 40			i-cache-size = <0x8000>;
 41			i-cache-sets = <32>;
 42			next-level-cache = <&l2>;
 43		};
 44
 45		cpu2: cpu@200 {
 46			device_type = "cpu";
 47			compatible = "arm,cortex-a55";
 48			reg = <0x0 0x200>;
 49			enable-method = "psci";
 50			d-cache-line-size = <32>;
 51			d-cache-size = <0x8000>;
 52			d-cache-sets = <32>;
 53			i-cache-line-size = <32>;
 54			i-cache-size = <0x8000>;
 55			i-cache-sets = <32>;
 56			next-level-cache = <&l2>;
 57		};
 58
 59		cpu3: cpu@300 {
 60			device_type = "cpu";
 61			compatible = "arm,cortex-a55";
 62			reg = <0x0 0x300>;
 63			enable-method = "psci";
 64			d-cache-line-size = <32>;
 65			d-cache-size = <0x8000>;
 66			d-cache-sets = <32>;
 67			i-cache-line-size = <32>;
 68			i-cache-size = <0x8000>;
 69			i-cache-sets = <32>;
 70			next-level-cache = <&l2>;
 71		};
 72
 73		l2: l2-cache0 {
 74			compatible = "cache";
 75			cache-level = <2>;
 76			cache-unified;
 77			cache-size = <0x40000>; /* L2. 256 KB */
 78			cache-line-size = <64>;
 79			cache-sets = <512>;
 80		};
 81	};
 82
 83	sm: secure-monitor {
 84		compatible = "amlogic,meson-gxbb-sm";
 85
 86		pwrc: power-controller {
 87			compatible = "amlogic,s7-pwrc";
 88			#power-domain-cells = <1>;
 89		};
 90	};
 91
 92	timer {
 93		compatible = "arm,armv8-timer";
 94		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 95			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 96			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 97			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 98	};
 99
100	psci {
101		compatible = "arm,psci-1.0";
102		method = "smc";
103	};
104
105	xtal: xtal-clk {
106		compatible = "fixed-clock";
107		clock-frequency = <24000000>;
108		clock-output-names = "xtal";
109		#clock-cells = <0>;
110	};
111
112	soc {
113		compatible = "simple-bus";
114		#address-cells = <2>;
115		#size-cells = <2>;
116		ranges;
117
118		gic: interrupt-controller@fff01000 {
119			compatible = "arm,gic-400";
120			#interrupt-cells = <3>;
121			#address-cells = <0>;
122			interrupt-controller;
123			reg = <0x0 0xfff01000 0 0x1000>,
124			      <0x0 0xfff02000 0 0x0100>;
125			interrupts = <GIC_PPI 9 0xf04>;
126		};
127
128		apb: bus@fe000000 {
129			compatible = "simple-bus";
130			reg = <0x0 0xfe000000 0x0 0x480000>;
131			#address-cells = <2>;
132			#size-cells = <2>;
133			ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;
134
135			uart_b: serial@7a000 {
136				compatible = "amlogic,s7-uart",
137					     "amlogic,meson-s4-uart";
138				reg = <0x0 0x7a000 0x0 0x18>;
139				interrupts = <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>;
140				clocks = <&xtal>, <&xtal>, <&xtal>;
141				clock-names = "xtal", "pclk", "baud";
142				status = "disabled";
143			};
144
145			periphs_pinctrl: pinctrl@4000 {
146				compatible = "amlogic,pinctrl-s7";
147				#address-cells = <2>;
148				#size-cells = <2>;
149				ranges = <0x0 0x0 0x0 0x4000 0x0 0x340>;
150
151				gpioz: gpio@c0 {
152					reg = <0 0xc0 0 0x20>, <0 0x18 0 0x8>;
153					reg-names = "gpio", "mux";
154					gpio-controller;
155					#gpio-cells = <2>;
156					gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_Z<<8) 13>;
157				};
158
159				gpiox: gpio@100 {
160					reg = <0 0x100 0 0x30>, <0 0xc 0 0x8>;
161					reg-names = "gpio", "mux";
162					gpio-controller;
163					#gpio-cells = <2>;
164					gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_X<<8) 20>;
165				};
166
167				gpioh: gpio@140 {
168					reg = <0 0x140 0 0x20>, <0 0x2c 0 0x8>;
169					reg-names = "gpio", "mux";
170					gpio-controller;
171					#gpio-cells = <2>;
172					gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_H<<8) 12>;
173				};
174
175				gpiod: gpio@180 {
176					reg = <0 0x180 0 0x20>, <0 0x40 0 0x8>;
177					reg-names = "gpio", "mux";
178					gpio-controller;
179					#gpio-cells = <2>;
180					gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_D<<8) 12>;
181				};
182
183				gpioe: gpio@1c0 {
184					reg = <0 0x1c0 0 0x20>, <0 0x48 0 0x4>;
185					reg-names = "gpio", "mux";
186					gpio-controller;
187					#gpio-cells = <2>;
188					gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_E<<8) 2>;
189				};
190
191				gpioc: gpio@200 {
192					reg = <0 0x200 0 0x20>, <0 0x24 0 0x4>;
193					reg-names = "gpio", "mux";
194					gpio-controller;
195					#gpio-cells = <2>;
196					gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_C<<8) 8>;
197				};
198
199				gpiob: gpio@240 {
200					reg = <0 0x240 0 0x20>, <0 0x0 0 0x8>;
201					reg-names = "gpio", "mux";
202					gpio-controller;
203					#gpio-cells = <2>;
204					gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_B<<8) 14>;
205				};
206
207				test_n: gpio@2c0 {
208					reg = <0 0x2c0 0 0x20>;
209					reg-names = "gpio";
210					gpio-controller;
211					#gpio-cells = <2>;
212					gpio-ranges =
213						<&periphs_pinctrl 0 (AMLOGIC_GPIO_TEST_N<<8) 1>;
214				};
215
216				gpiocc: gpio@300 {
217					reg = <0 0x300 0 0x20>, <0 0x14 0 0x4>;
218					reg-names = "gpio", "mux";
219					gpio-controller;
220					#gpio-cells = <2>;
221					gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_CC<<8) 2>;
222				};
223			};
224
225			gpio_intc: interrupt-controller@4080 {
226				compatible = "amlogic,s7-gpio-intc",
227					     "amlogic,meson-gpio-intc";
228				reg = <0x0 0x4080 0x0 0x20>;
229				interrupt-controller;
230				#interrupt-cells = <2>;
231				amlogic,channel-interrupts =
232					<10 11 12 13 14 15 16 17 18 19 20 21>;
233			};
234
235			ao-secure@10220 {
236				compatible = "amlogic,s7-ao-secure",
237					     "amlogic,meson-gx-ao-secure",
238					     "syscon";
239				reg = <0x0 0x10220 0x0 0x140>;
240				amlogic,has-chip-id;
241			};
242		};
243	};
244};