amd-seattle-soc.dtsi

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * DTS file for AMD Seattle SoC
  4 *
  5 * Copyright (C) 2014 Advanced Micro Devices, Inc.
  6 */
  7
  8/ {
  9	compatible = "amd,seattle";
 10	interrupt-parent = <&gic0>;
 11	#address-cells = <2>;
 12	#size-cells = <2>;
 13
 14	/include/ "amd-seattle-clks.dtsi"
 15
 16	gic0: interrupt-controller@e1101000 {
 17		compatible = "arm,gic-400", "arm,cortex-a15-gic";
 18		interrupt-controller;
 19		#interrupt-cells = <3>;
 20		#address-cells = <2>;
 21		#size-cells = <2>;
 22		reg = <0x0 0xe1110000 0 0x1000>,
 23		      <0x0 0xe112f000 0 0x2000>,
 24		      <0x0 0xe1140000 0 0x2000>,
 25		      <0x0 0xe1160000 0 0x2000>;
 26		interrupts = <1 9 0xf04>;
 27		ranges = <0 0 0 0xe1100000 0 0x100000>;
 28		v2m0: v2m@e0080000 {
 29			compatible = "arm,gic-v2m-frame";
 30			msi-controller;
 31			reg = <0x0 0x00080000 0 0x1000>;
 32		};
 33	};
 34
 35	timer {
 36		compatible = "arm,armv8-timer";
 37		interrupts = <1 13 0xff04>,
 38			     <1 14 0xff04>,
 39			     <1 11 0xff04>,
 40			     <1 10 0xff04>;
 41	};
 42
 43	smb0: bus {
 44		compatible = "simple-bus";
 45		#address-cells = <2>;
 46		#size-cells = <2>;
 47		ranges;
 48
 49		/*
 50		 * dma-ranges is 40-bit address space containing:
 51		 * - GICv2m MSI register is at 0xe0080000
 52		 * - DRAM range [0x8000000000 to 0xffffffffff]
 53		 */
 54		dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
 55
 56		sata0: sata@e0300000 {
 57			compatible = "snps,dwc-ahci";
 58			reg = <0 0xe0300000 0 0xf0000>;
 59			interrupts = <0 355 4>;
 60			clocks = <&sataclk_333mhz>;
 61			iommus = <&sata0_smmu 0x0 0x1f>;
 62			dma-coherent;
 63		};
 64
 65		/* This is for Rev B only */
 66		sata1: sata@e0d00000 {
 67			status = "disabled";
 68			compatible = "snps,dwc-ahci";
 69			reg = <0 0xe0d00000 0 0xf0000>;
 70			interrupts = <0 354 4>;
 71			clocks = <&sataclk_333mhz>;
 72			iommus = <&sata1_smmu 0x0e>,
 73				 <&sata1_smmu 0x0f>,
 74				 <&sata1_smmu 0x1e>;
 75			dma-coherent;
 76		};
 77
 78		sata0_smmu: iommu@e0200000 {
 79			compatible = "arm,mmu-401";
 80			reg = <0 0xe0200000 0 0x10000>;
 81			#global-interrupts = <1>;
 82			interrupts = <0 332 4>, <0 332 4>;
 83			#iommu-cells = <2>;
 84			dma-coherent;
 85		};
 86
 87		sata1_smmu: iommu@e0c00000 {
 88			compatible = "arm,mmu-401";
 89			reg = <0 0xe0c00000 0 0x10000>;
 90			#global-interrupts = <1>;
 91			interrupts = <0 331 4>, <0 331 4>;
 92			#iommu-cells = <1>;
 93			dma-coherent;
 94		};
 95
 96		i2c0: i2c@e1000000 {
 97			status = "disabled";
 98			compatible = "snps,designware-i2c";
 99			reg = <0 0xe1000000 0 0x1000>;
100			interrupts = <0 357 4>;
101			clocks = <&miscclk_250mhz>;
102		};
103
104		i2c1: i2c@e0050000 {
105			status = "disabled";
106			compatible = "snps,designware-i2c";
107			reg = <0 0xe0050000 0 0x1000>;
108			interrupts = <0 340 4>;
109			clocks = <&miscclk_250mhz>;
110		};
111
112		serial0: serial@e1010000 {
113			compatible = "arm,pl011", "arm,primecell";
114			reg = <0 0xe1010000 0 0x1000>;
115			interrupts = <0 328 4>;
116			clocks = <&uartspiclk_100mhz>, <&uartspiclk_100mhz>;
117			clock-names = "uartclk", "apb_pclk";
118		};
119
120		spi0: spi@e1020000 {
121			status = "disabled";
122			compatible = "arm,pl022", "arm,primecell";
123			reg = <0 0xe1020000 0 0x1000>;
124			interrupts = <0 330 4>;
125			clocks = <&uartspiclk_100mhz>, <&uartspiclk_100mhz>;
126			clock-names = "sspclk", "apb_pclk";
127		};
128
129		spi1: spi@e1030000 {
130			status = "disabled";
131			compatible = "arm,pl022", "arm,primecell";
132			reg = <0 0xe1030000 0 0x1000>;
133			interrupts = <0 329 4>;
134			clocks = <&uartspiclk_100mhz>, <&uartspiclk_100mhz>;
135			clock-names = "sspclk", "apb_pclk";
136			num-cs = <1>;
137			#address-cells = <1>;
138			#size-cells = <0>;
139		};
140
141		gpio0: gpio@e1040000 { /* Not available to OS for B0 */
142			status = "disabled";
143			compatible = "arm,pl061", "arm,primecell";
144			#gpio-cells = <2>;
145			reg = <0 0xe1040000 0 0x1000>;
146			gpio-controller;
147			interrupts = <0 359 4>;
148			interrupt-controller;
149			#interrupt-cells = <2>;
150			clocks = <&miscclk_250mhz>;
151			clock-names = "apb_pclk";
152		};
153
154		gpio1: gpio@e1050000 { /* [0:7] */
155			status = "disabled";
156			compatible = "arm,pl061", "arm,primecell";
157			#gpio-cells = <2>;
158			reg = <0 0xe1050000 0 0x1000>;
159			gpio-controller;
160			interrupt-controller;
161			#interrupt-cells = <2>;
162			interrupts = <0 358 4>;
163			clocks = <&miscclk_250mhz>;
164			clock-names = "apb_pclk";
165		};
166
167		gpio2: gpio@e0020000 { /* [8:15] */
168			status = "disabled";
169			compatible = "arm,pl061", "arm,primecell";
170			#gpio-cells = <2>;
171			reg = <0 0xe0020000 0 0x1000>;
172			gpio-controller;
173			interrupt-controller;
174			#interrupt-cells = <2>;
175			interrupts = <0 366 4>;
176			clocks = <&miscclk_250mhz>;
177			clock-names = "apb_pclk";
178		};
179
180		gpio3: gpio@e0030000 { /* [16:23] */
181			status = "disabled";
182			compatible = "arm,pl061", "arm,primecell";
183			#gpio-cells = <2>;
184			reg = <0 0xe0030000 0 0x1000>;
185			gpio-controller;
186			interrupt-controller;
187			#interrupt-cells = <2>;
188			interrupts = <0 365 4>;
189			clocks = <&miscclk_250mhz>;
190			clock-names = "apb_pclk";
191		};
192
193		gpio4: gpio@e0080000 { /* [24] */
194			status = "disabled";
195			compatible = "arm,pl061", "arm,primecell";
196			#gpio-cells = <2>;
197			reg = <0 0xe0080000 0 0x1000>;
198			gpio-controller;
199			interrupt-controller;
200			#interrupt-cells = <2>;
201			interrupts = <0 361 4>;
202			clocks = <&miscclk_250mhz>;
203			clock-names = "apb_pclk";
204		};
205
206		ccp0: ccp@e0100000 {
207			status = "disabled";
208			compatible = "amd,ccp-seattle-v1a";
209			reg = <0 0xe0100000 0 0x10000>;
210			interrupts = <0 3 4>;
211			dma-coherent;
212			iommus = <&sata1_smmu 0x00>,
213				 <&sata1_smmu 0x02>,
214				 <&sata1_smmu 0x40>,
215				 <&sata1_smmu 0x42>;
216		};
217
218		pcie0: pcie@f0000000 {
219			compatible = "pci-host-ecam-generic";
220			#address-cells = <3>;
221			#size-cells = <2>;
222			#interrupt-cells = <1>;
223			device_type = "pci";
224			bus-range = <0 0x7f>;
225			msi-parent = <&v2m0>;
226			reg = <0 0xf0000000 0 0x10000000>;
227
228			interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
229			interrupt-map =
230				<0x1100 0x0 0x0 0x1 &gic0 0x0 0x0 0x0 0x120 0x1>,
231				<0x1100 0x0 0x0 0x2 &gic0 0x0 0x0 0x0 0x121 0x1>,
232				<0x1100 0x0 0x0 0x3 &gic0 0x0 0x0 0x0 0x122 0x1>,
233				<0x1100 0x0 0x0 0x4 &gic0 0x0 0x0 0x0 0x123 0x1>,
234
235				<0x1200 0x0 0x0 0x1 &gic0 0x0 0x0 0x0 0x124 0x1>,
236				<0x1200 0x0 0x0 0x2 &gic0 0x0 0x0 0x0 0x125 0x1>,
237				<0x1200 0x0 0x0 0x3 &gic0 0x0 0x0 0x0 0x126 0x1>,
238				<0x1200 0x0 0x0 0x4 &gic0 0x0 0x0 0x0 0x127 0x1>,
239
240				<0x1300 0x0 0x0 0x1 &gic0 0x0 0x0 0x0 0x128 0x1>,
241				<0x1300 0x0 0x0 0x2 &gic0 0x0 0x0 0x0 0x129 0x1>,
242				<0x1300 0x0 0x0 0x3 &gic0 0x0 0x0 0x0 0x12a 0x1>,
243				<0x1300 0x0 0x0 0x4 &gic0 0x0 0x0 0x0 0x12b 0x1>;
244
245			dma-coherent;
246			dma-ranges = <0x43000000 0x0 0x0 0x0 0x0 0x100 0x0>;
247			ranges =
248				/* I/O Memory (size=64K) */
249				<0x01000000 0x00 0x00000000 0x00 0xefff0000 0x00 0x00010000>,
250				/* 32-bit MMIO (size=2G) */
251				<0x02000000 0x00 0x40000000 0x00 0x40000000 0x00 0x80000000>,
252				/* 64-bit MMIO (size= 508G) */
253				<0x03000000 0x01 0x00000000 0x01 0x00000000 0x7f 0x00000000>;
254			iommu-map = <0x0 &pcie_smmu 0x0 0x10000>;
255		};
256
257		pcie_smmu: iommu@e0a00000 {
258			compatible = "arm,mmu-401";
259			reg = <0 0xe0a00000 0 0x10000>;
260			#global-interrupts = <1>;
261			interrupts = <0 333 4>, <0 333 4>;
262			#iommu-cells = <1>;
263			dma-coherent;
264		};
265
266		/* Perf CCN504 PMU */
267		ccn: ccn@e8000000 {
268			compatible = "arm,ccn-504";
269			reg = <0x0 0xe8000000 0 0x1000000>;
270			interrupts = <0 380 4>;
271		};
272
273		ipmi_kcs: kcs@e0010000 {
274			status = "disabled";
275			compatible = "ipmi-kcs";
276			device_type = "ipmi";
277			reg = <0x0 0xe0010000 0 0x8>;
278			interrupts = <0 389 4>;
279			reg-size = <1>;
280			reg-spacing = <4>;
281		};
282	};
283};