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sun50i-h616.dtsi
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linux-6.19.14/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2// Copyright (C) 2020 Arm Ltd. 3// based on the H6 dtsi, which is: 4// Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/sun50i-h616-ccu.h> 8#include <dt-bindings/clock/sun50i-h6-r-ccu.h> 9#include <dt-bindings/clock/sun6i-rtc.h> 10#include <dt-bindings/reset/sun50i-h616-ccu.h> 11#include <dt-bindings/reset/sun50i-h6-r-ccu.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 cpus { 20 #address-cells = <1>; 21 #size-cells = <0>; 22 23 cpu0: cpu@0 { 24 compatible = "arm,cortex-a53"; 25 device_type = "cpu"; 26 reg = <0>; 27 enable-method = "psci"; 28 clocks = <&ccu CLK_CPUX>; 29 #cooling-cells = <2>; 30 i-cache-size = <0x8000>; 31 i-cache-line-size = <64>; 32 i-cache-sets = <256>; 33 d-cache-size = <0x8000>; 34 d-cache-line-size = <64>; 35 d-cache-sets = <128>; 36 next-level-cache = <&l2_cache>; 37 }; 38 39 cpu1: cpu@1 { 40 compatible = "arm,cortex-a53"; 41 device_type = "cpu"; 42 reg = <1>; 43 enable-method = "psci"; 44 clocks = <&ccu CLK_CPUX>; 45 #cooling-cells = <2>; 46 i-cache-size = <0x8000>; 47 i-cache-line-size = <64>; 48 i-cache-sets = <256>; 49 d-cache-size = <0x8000>; 50 d-cache-line-size = <64>; 51 d-cache-sets = <128>; 52 next-level-cache = <&l2_cache>; 53 }; 54 55 cpu2: cpu@2 { 56 compatible = "arm,cortex-a53"; 57 device_type = "cpu"; 58 reg = <2>; 59 enable-method = "psci"; 60 clocks = <&ccu CLK_CPUX>; 61 #cooling-cells = <2>; 62 i-cache-size = <0x8000>; 63 i-cache-line-size = <64>; 64 i-cache-sets = <256>; 65 d-cache-size = <0x8000>; 66 d-cache-line-size = <64>; 67 d-cache-sets = <128>; 68 next-level-cache = <&l2_cache>; 69 }; 70 71 cpu3: cpu@3 { 72 compatible = "arm,cortex-a53"; 73 device_type = "cpu"; 74 reg = <3>; 75 enable-method = "psci"; 76 clocks = <&ccu CLK_CPUX>; 77 #cooling-cells = <2>; 78 i-cache-size = <0x8000>; 79 i-cache-line-size = <64>; 80 i-cache-sets = <256>; 81 d-cache-size = <0x8000>; 82 d-cache-line-size = <64>; 83 d-cache-sets = <128>; 84 next-level-cache = <&l2_cache>; 85 }; 86 87 l2_cache: l2-cache { 88 compatible = "cache"; 89 cache-level = <2>; 90 cache-unified; 91 cache-size = <0x40000>; 92 cache-line-size = <64>; 93 cache-sets = <256>; 94 }; 95 }; 96 97 reserved-memory { 98 #address-cells = <2>; 99 #size-cells = <2>; 100 ranges; 101 102 /* 103 * 256 KiB reserved for Trusted Firmware-A (BL31). 104 * This is added by BL31 itself, but some bootloaders fail 105 * to propagate this into the DTB handed to kernels. 106 */ 107 secmon@40000000 { 108 reg = <0x0 0x40000000 0x0 0x40000>; 109 no-map; 110 }; 111 }; 112 113 osc24M: osc24M-clk { 114 #clock-cells = <0>; 115 compatible = "fixed-clock"; 116 clock-frequency = <24000000>; 117 clock-output-names = "osc24M"; 118 }; 119 120 pmu { 121 compatible = "arm,cortex-a53-pmu"; 122 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 123 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 124 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 125 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 126 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 127 }; 128 129 psci { 130 compatible = "arm,psci-0.2"; 131 method = "smc"; 132 }; 133 134 timer { 135 compatible = "arm,armv8-timer"; 136 arm,no-tick-in-suspend; 137 interrupts = <GIC_PPI 13 138 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 139 <GIC_PPI 14 140 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 141 <GIC_PPI 11 142 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 143 <GIC_PPI 10 144 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 145 }; 146 147 soc { 148 compatible = "simple-bus"; 149 #address-cells = <1>; 150 #size-cells = <1>; 151 ranges = <0x0 0x0 0x0 0x40000000>; 152 153 gpu: gpu@1800000 { 154 compatible = "allwinner,sun50i-h616-mali", 155 "arm,mali-bifrost"; 156 reg = <0x1800000 0x40000>; 157 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 158 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 159 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 160 interrupt-names = "job", "mmu", "gpu"; 161 clocks = <&ccu CLK_GPU0>, <&ccu CLK_BUS_GPU>; 162 clock-names = "core", "bus"; 163 power-domains = <&prcm_ppu 2>; 164 resets = <&ccu RST_BUS_GPU>; 165 status = "disabled"; 166 }; 167 168 crypto: crypto@1904000 { 169 compatible = "allwinner,sun50i-h616-crypto"; 170 reg = <0x01904000 0x800>; 171 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 172 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>, 173 <&ccu CLK_MBUS_CE>, <&rtc CLK_IOSC>; 174 clock-names = "bus", "mod", "ram", "trng"; 175 resets = <&ccu RST_BUS_CE>; 176 }; 177 178 syscon: syscon@3000000 { 179 compatible = "allwinner,sun50i-h616-system-control"; 180 reg = <0x03000000 0x1000>; 181 #address-cells = <1>; 182 #size-cells = <1>; 183 ranges; 184 185 sram_c: sram@28000 { 186 compatible = "mmio-sram"; 187 reg = <0x00028000 0x30000>; 188 #address-cells = <1>; 189 #size-cells = <1>; 190 ranges = <0 0x00028000 0x30000>; 191 }; 192 }; 193 194 ccu: clock@3001000 { 195 compatible = "allwinner,sun50i-h616-ccu"; 196 reg = <0x03001000 0x1000>; 197 clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>; 198 clock-names = "hosc", "losc", "iosc"; 199 #clock-cells = <1>; 200 #reset-cells = <1>; 201 }; 202 203 dma: dma-controller@3002000 { 204 compatible = "allwinner,sun50i-h616-dma", 205 "allwinner,sun50i-a100-dma"; 206 reg = <0x03002000 0x1000>; 207 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 208 clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>; 209 clock-names = "bus", "mbus"; 210 dma-channels = <16>; 211 dma-requests = <49>; 212 resets = <&ccu RST_BUS_DMA>; 213 #dma-cells = <1>; 214 }; 215 216 sid: efuse@3006000 { 217 compatible = "allwinner,sun50i-h616-sid", "allwinner,sun50i-a64-sid"; 218 reg = <0x03006000 0x1000>; 219 #address-cells = <1>; 220 #size-cells = <1>; 221 222 ths_calibration: thermal-sensor-calibration@14 { 223 reg = <0x14 0x8>; 224 }; 225 226 cpu_speed_grade: cpu-speed-grade@0 { 227 reg = <0x0 2>; 228 }; 229 }; 230 231 watchdog: watchdog@30090a0 { 232 compatible = "allwinner,sun50i-h616-wdt", 233 "allwinner,sun6i-a31-wdt"; 234 reg = <0x030090a0 0x20>; 235 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 236 clocks = <&osc24M>; 237 }; 238 239 pio: pinctrl@300b000 { 240 compatible = "allwinner,sun50i-h616-pinctrl"; 241 reg = <0x0300b000 0x400>; 242 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 243 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 244 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 245 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 246 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 247 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 248 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 249 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 250 clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc CLK_OSC32K>; 251 clock-names = "apb", "hosc", "losc"; 252 gpio-controller; 253 #gpio-cells = <3>; 254 interrupt-controller; 255 #interrupt-cells = <3>; 256 257 ext_rgmii_pins: rgmii-pins { 258 pins = "PI0", "PI1", "PI2", "PI3", "PI4", 259 "PI5", "PI7", "PI8", "PI9", "PI10", 260 "PI11", "PI12", "PI13", "PI14", "PI15", 261 "PI16"; 262 function = "emac0"; 263 drive-strength = <40>; 264 }; 265 266 i2c0_pins: i2c0-pins { 267 pins = "PI5", "PI6"; 268 function = "i2c0"; 269 }; 270 271 i2c3_ph_pins: i2c3-ph-pins { 272 pins = "PH4", "PH5"; 273 function = "i2c3"; 274 }; 275 276 ir_rx_pin: ir-rx-pin { 277 pins = "PH10"; 278 function = "ir_rx"; 279 }; 280 281 mmc0_pins: mmc0-pins { 282 pins = "PF0", "PF1", "PF2", "PF3", 283 "PF4", "PF5"; 284 function = "mmc0"; 285 drive-strength = <30>; 286 bias-pull-up; 287 }; 288 289 /omit-if-no-ref/ 290 mmc1_pins: mmc1-pins { 291 pins = "PG0", "PG1", "PG2", "PG3", 292 "PG4", "PG5"; 293 function = "mmc1"; 294 drive-strength = <30>; 295 bias-pull-up; 296 }; 297 298 mmc2_pins: mmc2-pins { 299 pins = "PC0", "PC1", "PC5", "PC6", 300 "PC8", "PC9", "PC10", "PC11", 301 "PC13", "PC14", "PC15", "PC16"; 302 function = "mmc2"; 303 drive-strength = <30>; 304 bias-pull-up; 305 }; 306 307 /omit-if-no-ref/ 308 nand_pins: nand-pins { 309 pins = "PC0", "PC1", "PC2", "PC5", "PC8", "PC9", 310 "PC10", "PC11", "PC12", "PC13", "PC14", 311 "PC15", "PC16"; 312 function = "nand0"; 313 }; 314 315 /omit-if-no-ref/ 316 nand_cs0_pin: nand-cs0-pin { 317 pins = "PC4"; 318 function = "nand0"; 319 bias-pull-up; 320 }; 321 322 /omit-if-no-ref/ 323 nand_cs1_pin: nand-cs1-pin { 324 pins = "PC3"; 325 function = "nand0"; 326 bias-pull-up; 327 }; 328 329 /omit-if-no-ref/ 330 nand_rb0_pin: nand-rb0-pin { 331 pins = "PC6"; 332 function = "nand0"; 333 bias-pull-up; 334 }; 335 336 /omit-if-no-ref/ 337 nand_rb1_pin: nand-rb1-pin { 338 pins = "PC7"; 339 function = "nand0"; 340 bias-pull-up; 341 }; 342 343 /omit-if-no-ref/ 344 spi0_pins: spi0-pins { 345 pins = "PC0", "PC2", "PC4"; 346 function = "spi0"; 347 }; 348 349 /omit-if-no-ref/ 350 spi0_cs0_pin: spi0-cs0-pin { 351 pins = "PC3"; 352 function = "spi0"; 353 }; 354 355 /omit-if-no-ref/ 356 spi1_pins: spi1-pins { 357 pins = "PH6", "PH7", "PH8"; 358 function = "spi1"; 359 }; 360 361 /omit-if-no-ref/ 362 spi1_cs0_pin: spi1-cs0-pin { 363 pins = "PH5"; 364 function = "spi1"; 365 }; 366 367 spdif_tx_pin: spdif-tx-pin { 368 pins = "PH4"; 369 function = "spdif"; 370 }; 371 372 uart0_ph_pins: uart0-ph-pins { 373 pins = "PH0", "PH1"; 374 function = "uart0"; 375 }; 376 377 /omit-if-no-ref/ 378 uart1_pins: uart1-pins { 379 pins = "PG6", "PG7"; 380 function = "uart1"; 381 }; 382 383 /omit-if-no-ref/ 384 uart1_rts_cts_pins: uart1-rts-cts-pins { 385 pins = "PG8", "PG9"; 386 function = "uart1"; 387 }; 388 389 /omit-if-no-ref/ 390 x32clk_fanout_pin: x32clk-fanout-pin { 391 pins = "PG10"; 392 function = "clock"; 393 }; 394 }; 395 396 gic: interrupt-controller@3021000 { 397 compatible = "arm,gic-400"; 398 reg = <0x03021000 0x1000>, 399 <0x03022000 0x2000>, 400 <0x03024000 0x2000>, 401 <0x03026000 0x2000>; 402 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 403 interrupt-controller; 404 #interrupt-cells = <3>; 405 }; 406 407 iommu: iommu@30f0000 { 408 compatible = "allwinner,sun50i-h616-iommu"; 409 reg = <0x030f0000 0x10000>; 410 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 411 clocks = <&ccu CLK_BUS_IOMMU>; 412 resets = <&ccu RST_BUS_IOMMU>; 413 #iommu-cells = <1>; 414 }; 415 416 nfc: nand-controller@4011000 { 417 compatible = "allwinner,sun50i-h616-nand-controller"; 418 reg = <0x04011000 0x1000>; 419 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 420 clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND0>, 421 <&ccu CLK_NAND1>, <&ccu CLK_MBUS_NAND>; 422 clock-names = "ahb", "mod", "ecc", "mbus"; 423 resets = <&ccu RST_BUS_NAND>; 424 reset-names = "ahb"; 425 dmas = <&dma 10>; 426 dma-names = "rxtx"; 427 #address-cells = <1>; 428 #size-cells = <0>; 429 status = "disabled"; 430 }; 431 432 mmc0: mmc@4020000 { 433 compatible = "allwinner,sun50i-h616-mmc", 434 "allwinner,sun50i-a100-mmc"; 435 reg = <0x04020000 0x1000>; 436 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 437 clock-names = "ahb", "mmc"; 438 resets = <&ccu RST_BUS_MMC0>; 439 reset-names = "ahb"; 440 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 441 pinctrl-names = "default"; 442 pinctrl-0 = <&mmc0_pins>; 443 status = "disabled"; 444 max-frequency = <150000000>; 445 cap-sd-highspeed; 446 cap-mmc-highspeed; 447 mmc-ddr-3_3v; 448 cap-sdio-irq; 449 #address-cells = <1>; 450 #size-cells = <0>; 451 }; 452 453 mmc1: mmc@4021000 { 454 compatible = "allwinner,sun50i-h616-mmc", 455 "allwinner,sun50i-a100-mmc"; 456 reg = <0x04021000 0x1000>; 457 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 458 clock-names = "ahb", "mmc"; 459 resets = <&ccu RST_BUS_MMC1>; 460 reset-names = "ahb"; 461 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 462 pinctrl-names = "default"; 463 pinctrl-0 = <&mmc1_pins>; 464 status = "disabled"; 465 max-frequency = <150000000>; 466 cap-sd-highspeed; 467 cap-mmc-highspeed; 468 mmc-ddr-3_3v; 469 cap-sdio-irq; 470 #address-cells = <1>; 471 #size-cells = <0>; 472 }; 473 474 mmc2: mmc@4022000 { 475 compatible = "allwinner,sun50i-h616-emmc", 476 "allwinner,sun50i-a100-emmc"; 477 reg = <0x04022000 0x1000>; 478 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 479 clock-names = "ahb", "mmc"; 480 resets = <&ccu RST_BUS_MMC2>; 481 reset-names = "ahb"; 482 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 483 pinctrl-names = "default"; 484 pinctrl-0 = <&mmc2_pins>; 485 status = "disabled"; 486 max-frequency = <150000000>; 487 cap-sd-highspeed; 488 cap-mmc-highspeed; 489 mmc-ddr-3_3v; 490 cap-sdio-irq; 491 #address-cells = <1>; 492 #size-cells = <0>; 493 }; 494 495 uart0: serial@5000000 { 496 compatible = "snps,dw-apb-uart"; 497 reg = <0x05000000 0x400>; 498 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 499 reg-shift = <2>; 500 reg-io-width = <4>; 501 clocks = <&ccu CLK_BUS_UART0>; 502 dmas = <&dma 14>, <&dma 14>; 503 dma-names = "tx", "rx"; 504 resets = <&ccu RST_BUS_UART0>; 505 status = "disabled"; 506 }; 507 508 uart1: serial@5000400 { 509 compatible = "snps,dw-apb-uart"; 510 reg = <0x05000400 0x400>; 511 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 512 reg-shift = <2>; 513 reg-io-width = <4>; 514 clocks = <&ccu CLK_BUS_UART1>; 515 dmas = <&dma 15>, <&dma 15>; 516 dma-names = "tx", "rx"; 517 resets = <&ccu RST_BUS_UART1>; 518 status = "disabled"; 519 }; 520 521 uart2: serial@5000800 { 522 compatible = "snps,dw-apb-uart"; 523 reg = <0x05000800 0x400>; 524 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 525 reg-shift = <2>; 526 reg-io-width = <4>; 527 clocks = <&ccu CLK_BUS_UART2>; 528 dmas = <&dma 16>, <&dma 16>; 529 dma-names = "tx", "rx"; 530 resets = <&ccu RST_BUS_UART2>; 531 status = "disabled"; 532 }; 533 534 uart3: serial@5000c00 { 535 compatible = "snps,dw-apb-uart"; 536 reg = <0x05000c00 0x400>; 537 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 538 reg-shift = <2>; 539 reg-io-width = <4>; 540 clocks = <&ccu CLK_BUS_UART3>; 541 dmas = <&dma 17>, <&dma 17>; 542 dma-names = "tx", "rx"; 543 resets = <&ccu RST_BUS_UART3>; 544 status = "disabled"; 545 }; 546 547 uart4: serial@5001000 { 548 compatible = "snps,dw-apb-uart"; 549 reg = <0x05001000 0x400>; 550 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 551 reg-shift = <2>; 552 reg-io-width = <4>; 553 clocks = <&ccu CLK_BUS_UART4>; 554 dmas = <&dma 18>, <&dma 18>; 555 dma-names = "tx", "rx"; 556 resets = <&ccu RST_BUS_UART4>; 557 status = "disabled"; 558 }; 559 560 uart5: serial@5001400 { 561 compatible = "snps,dw-apb-uart"; 562 reg = <0x05001400 0x400>; 563 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 564 reg-shift = <2>; 565 reg-io-width = <4>; 566 clocks = <&ccu CLK_BUS_UART5>; 567 dmas = <&dma 19>, <&dma 19>; 568 dma-names = "tx", "rx"; 569 resets = <&ccu RST_BUS_UART5>; 570 status = "disabled"; 571 }; 572 573 i2c0: i2c@5002000 { 574 compatible = "allwinner,sun50i-h616-i2c", 575 "allwinner,sun8i-v536-i2c", 576 "allwinner,sun6i-a31-i2c"; 577 reg = <0x05002000 0x400>; 578 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 579 clocks = <&ccu CLK_BUS_I2C0>; 580 dmas = <&dma 43>, <&dma 43>; 581 dma-names = "rx", "tx"; 582 resets = <&ccu RST_BUS_I2C0>; 583 pinctrl-names = "default"; 584 pinctrl-0 = <&i2c0_pins>; 585 status = "disabled"; 586 #address-cells = <1>; 587 #size-cells = <0>; 588 }; 589 590 i2c1: i2c@5002400 { 591 compatible = "allwinner,sun50i-h616-i2c", 592 "allwinner,sun8i-v536-i2c", 593 "allwinner,sun6i-a31-i2c"; 594 reg = <0x05002400 0x400>; 595 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 596 clocks = <&ccu CLK_BUS_I2C1>; 597 dmas = <&dma 44>, <&dma 44>; 598 dma-names = "rx", "tx"; 599 resets = <&ccu RST_BUS_I2C1>; 600 status = "disabled"; 601 #address-cells = <1>; 602 #size-cells = <0>; 603 }; 604 605 i2c2: i2c@5002800 { 606 compatible = "allwinner,sun50i-h616-i2c", 607 "allwinner,sun8i-v536-i2c", 608 "allwinner,sun6i-a31-i2c"; 609 reg = <0x05002800 0x400>; 610 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 611 clocks = <&ccu CLK_BUS_I2C2>; 612 dmas = <&dma 45>, <&dma 45>; 613 dma-names = "rx", "tx"; 614 resets = <&ccu RST_BUS_I2C2>; 615 status = "disabled"; 616 #address-cells = <1>; 617 #size-cells = <0>; 618 }; 619 620 i2c3: i2c@5002c00 { 621 compatible = "allwinner,sun50i-h616-i2c", 622 "allwinner,sun8i-v536-i2c", 623 "allwinner,sun6i-a31-i2c"; 624 reg = <0x05002c00 0x400>; 625 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 626 clocks = <&ccu CLK_BUS_I2C3>; 627 dmas = <&dma 46>, <&dma 46>; 628 dma-names = "rx", "tx"; 629 resets = <&ccu RST_BUS_I2C3>; 630 status = "disabled"; 631 #address-cells = <1>; 632 #size-cells = <0>; 633 }; 634 635 i2c4: i2c@5003000 { 636 compatible = "allwinner,sun50i-h616-i2c", 637 "allwinner,sun8i-v536-i2c", 638 "allwinner,sun6i-a31-i2c"; 639 reg = <0x05003000 0x400>; 640 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 641 clocks = <&ccu CLK_BUS_I2C4>; 642 dmas = <&dma 47>, <&dma 47>; 643 dma-names = "rx", "tx"; 644 resets = <&ccu RST_BUS_I2C4>; 645 status = "disabled"; 646 #address-cells = <1>; 647 #size-cells = <0>; 648 }; 649 650 spi0: spi@5010000 { 651 compatible = "allwinner,sun50i-h616-spi", 652 "allwinner,sun8i-h3-spi"; 653 reg = <0x05010000 0x1000>; 654 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 655 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 656 clock-names = "ahb", "mod"; 657 dmas = <&dma 22>, <&dma 22>; 658 dma-names = "rx", "tx"; 659 resets = <&ccu RST_BUS_SPI0>; 660 status = "disabled"; 661 #address-cells = <1>; 662 #size-cells = <0>; 663 }; 664 665 spi1: spi@5011000 { 666 compatible = "allwinner,sun50i-h616-spi", 667 "allwinner,sun8i-h3-spi"; 668 reg = <0x05011000 0x1000>; 669 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 670 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 671 clock-names = "ahb", "mod"; 672 dmas = <&dma 23>, <&dma 23>; 673 dma-names = "rx", "tx"; 674 resets = <&ccu RST_BUS_SPI1>; 675 status = "disabled"; 676 #address-cells = <1>; 677 #size-cells = <0>; 678 }; 679 680 emac0: ethernet@5020000 { 681 compatible = "allwinner,sun50i-h616-emac0", 682 "allwinner,sun50i-a64-emac"; 683 reg = <0x05020000 0x10000>; 684 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 685 interrupt-names = "macirq"; 686 clocks = <&ccu CLK_BUS_EMAC0>; 687 clock-names = "stmmaceth"; 688 resets = <&ccu RST_BUS_EMAC0>; 689 reset-names = "stmmaceth"; 690 syscon = <&syscon>; 691 status = "disabled"; 692 693 mdio0: mdio { 694 compatible = "snps,dwmac-mdio"; 695 #address-cells = <1>; 696 #size-cells = <0>; 697 }; 698 }; 699 700 gpadc: adc@5070000 { 701 compatible = "allwinner,sun50i-h616-gpadc", 702 "allwinner,sun20i-d1-gpadc"; 703 reg = <0x05070000 0x400>; 704 clocks = <&ccu CLK_BUS_GPADC>; 705 resets = <&ccu RST_BUS_GPADC>; 706 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 707 status = "disabled"; 708 #io-channel-cells = <1>; 709 }; 710 711 ths: thermal-sensor@5070400 { 712 compatible = "allwinner,sun50i-h616-ths"; 713 reg = <0x05070400 0x400>; 714 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 715 clocks = <&ccu CLK_BUS_THS>; 716 clock-names = "bus"; 717 resets = <&ccu RST_BUS_THS>; 718 nvmem-cells = <&ths_calibration>; 719 nvmem-cell-names = "calibration"; 720 allwinner,sram = <&syscon>; 721 #thermal-sensor-cells = <1>; 722 }; 723 724 lradc: lradc@5070800 { 725 compatible = "allwinner,sun50i-h616-lradc", 726 "allwinner,sun50i-r329-lradc"; 727 reg = <0x05070800 0x400>; 728 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 729 clocks = <&ccu CLK_BUS_KEYADC>; 730 resets = <&ccu RST_BUS_KEYADC>; 731 status = "disabled"; 732 }; 733 734 spdif: spdif@5093000 { 735 compatible = "allwinner,sun50i-h616-spdif"; 736 reg = <0x05093000 0x400>; 737 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 738 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 739 clock-names = "apb", "spdif"; 740 resets = <&ccu RST_BUS_SPDIF>; 741 dmas = <&dma 2>; 742 dma-names = "tx"; 743 pinctrl-names = "default"; 744 pinctrl-0 = <&spdif_tx_pin>; 745 #sound-dai-cells = <0>; 746 status = "disabled"; 747 }; 748 749 codec: codec@5096000 { 750 #sound-dai-cells = <0>; 751 compatible = "allwinner,sun50i-h616-codec"; 752 reg = <0x05096000 0x31c>; 753 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 754 clocks = <&ccu CLK_BUS_AUDIO_CODEC>, 755 <&ccu CLK_AUDIO_CODEC_1X>; 756 clock-names = "apb", "codec"; 757 resets = <&ccu RST_BUS_AUDIO_CODEC>; 758 dmas = <&dma 6>; 759 dma-names = "tx"; 760 status = "disabled"; 761 }; 762 763 usbotg: usb@5100000 { 764 compatible = "allwinner,sun50i-h616-musb", 765 "allwinner,sun8i-h3-musb"; 766 reg = <0x05100000 0x0400>; 767 clocks = <&ccu CLK_BUS_OTG>; 768 resets = <&ccu RST_BUS_OTG>; 769 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 770 interrupt-names = "mc"; 771 phys = <&usbphy 0>; 772 phy-names = "usb"; 773 extcon = <&usbphy 0>; 774 status = "disabled"; 775 }; 776 777 usbphy: phy@5100400 { 778 compatible = "allwinner,sun50i-h616-usb-phy"; 779 reg = <0x05100400 0x24>, 780 <0x05101800 0x14>, 781 <0x05200800 0x14>, 782 <0x05310800 0x14>, 783 <0x05311800 0x14>; 784 reg-names = "phy_ctrl", 785 "pmu0", 786 "pmu1", 787 "pmu2", 788 "pmu3"; 789 clocks = <&ccu CLK_USB_PHY0>, 790 <&ccu CLK_USB_PHY1>, 791 <&ccu CLK_USB_PHY2>, 792 <&ccu CLK_USB_PHY3>, 793 <&ccu CLK_BUS_EHCI2>; 794 clock-names = "usb0_phy", 795 "usb1_phy", 796 "usb2_phy", 797 "usb3_phy", 798 "pmu2_clk"; 799 resets = <&ccu RST_USB_PHY0>, 800 <&ccu RST_USB_PHY1>, 801 <&ccu RST_USB_PHY2>, 802 <&ccu RST_USB_PHY3>; 803 reset-names = "usb0_reset", 804 "usb1_reset", 805 "usb2_reset", 806 "usb3_reset"; 807 status = "disabled"; 808 #phy-cells = <1>; 809 }; 810 811 ehci0: usb@5101000 { 812 compatible = "allwinner,sun50i-h616-ehci", 813 "generic-ehci"; 814 reg = <0x05101000 0x100>; 815 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 816 clocks = <&ccu CLK_BUS_OHCI0>, 817 <&ccu CLK_BUS_EHCI0>, 818 <&ccu CLK_USB_OHCI0>; 819 resets = <&ccu RST_BUS_OHCI0>, 820 <&ccu RST_BUS_EHCI0>; 821 phys = <&usbphy 0>; 822 phy-names = "usb"; 823 status = "disabled"; 824 }; 825 826 ohci0: usb@5101400 { 827 compatible = "allwinner,sun50i-h616-ohci", 828 "generic-ohci"; 829 reg = <0x05101400 0x100>; 830 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 831 clocks = <&ccu CLK_BUS_OHCI0>, 832 <&ccu CLK_USB_OHCI0>; 833 resets = <&ccu RST_BUS_OHCI0>; 834 phys = <&usbphy 0>; 835 phy-names = "usb"; 836 status = "disabled"; 837 }; 838 839 ehci1: usb@5200000 { 840 compatible = "allwinner,sun50i-h616-ehci", 841 "generic-ehci"; 842 reg = <0x05200000 0x100>; 843 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 844 clocks = <&ccu CLK_BUS_OHCI1>, 845 <&ccu CLK_BUS_EHCI1>, 846 <&ccu CLK_USB_OHCI1>; 847 resets = <&ccu RST_BUS_OHCI1>, 848 <&ccu RST_BUS_EHCI1>; 849 phys = <&usbphy 1>; 850 phy-names = "usb"; 851 status = "disabled"; 852 }; 853 854 ohci1: usb@5200400 { 855 compatible = "allwinner,sun50i-h616-ohci", 856 "generic-ohci"; 857 reg = <0x05200400 0x100>; 858 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 859 clocks = <&ccu CLK_BUS_OHCI1>, 860 <&ccu CLK_USB_OHCI1>; 861 resets = <&ccu RST_BUS_OHCI1>; 862 phys = <&usbphy 1>; 863 phy-names = "usb"; 864 status = "disabled"; 865 }; 866 867 ehci2: usb@5310000 { 868 compatible = "allwinner,sun50i-h616-ehci", 869 "generic-ehci"; 870 reg = <0x05310000 0x100>; 871 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 872 clocks = <&ccu CLK_BUS_OHCI2>, 873 <&ccu CLK_BUS_EHCI2>, 874 <&ccu CLK_USB_OHCI2>; 875 resets = <&ccu RST_BUS_OHCI2>, 876 <&ccu RST_BUS_EHCI2>; 877 phys = <&usbphy 2>; 878 phy-names = "usb"; 879 status = "disabled"; 880 }; 881 882 ohci2: usb@5310400 { 883 compatible = "allwinner,sun50i-h616-ohci", 884 "generic-ohci"; 885 reg = <0x05310400 0x100>; 886 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 887 clocks = <&ccu CLK_BUS_OHCI2>, 888 <&ccu CLK_USB_OHCI2>; 889 resets = <&ccu RST_BUS_OHCI2>; 890 phys = <&usbphy 2>; 891 phy-names = "usb"; 892 status = "disabled"; 893 }; 894 895 ehci3: usb@5311000 { 896 compatible = "allwinner,sun50i-h616-ehci", 897 "generic-ehci"; 898 reg = <0x05311000 0x100>; 899 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 900 clocks = <&ccu CLK_BUS_OHCI3>, 901 <&ccu CLK_BUS_EHCI3>, 902 <&ccu CLK_USB_OHCI3>; 903 resets = <&ccu RST_BUS_OHCI3>, 904 <&ccu RST_BUS_EHCI3>; 905 phys = <&usbphy 3>; 906 phy-names = "usb"; 907 status = "disabled"; 908 }; 909 910 ohci3: usb@5311400 { 911 compatible = "allwinner,sun50i-h616-ohci", 912 "generic-ohci"; 913 reg = <0x05311400 0x100>; 914 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 915 clocks = <&ccu CLK_BUS_OHCI3>, 916 <&ccu CLK_USB_OHCI3>; 917 resets = <&ccu RST_BUS_OHCI3>; 918 phys = <&usbphy 3>; 919 phy-names = "usb"; 920 status = "disabled"; 921 }; 922 923 rtc: rtc@7000000 { 924 compatible = "allwinner,sun50i-h616-rtc"; 925 reg = <0x07000000 0x400>; 926 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 927 clocks = <&r_ccu CLK_R_APB1_RTC>, <&osc24M>, 928 <&ccu CLK_PLL_SYSTEM_32K>; 929 clock-names = "bus", "hosc", 930 "pll-32k"; 931 #clock-cells = <1>; 932 }; 933 934 r_ccu: clock@7010000 { 935 compatible = "allwinner,sun50i-h616-r-ccu"; 936 reg = <0x07010000 0x210>; 937 clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>, 938 <&ccu CLK_PLL_PERIPH0>; 939 clock-names = "hosc", "losc", "iosc", "pll-periph"; 940 #clock-cells = <1>; 941 #reset-cells = <1>; 942 }; 943 944 prcm_ppu: power-controller@7010250 { 945 compatible = "allwinner,sun50i-h616-prcm-ppu"; 946 reg = <0x07010250 0x10>; 947 #power-domain-cells = <1>; 948 }; 949 950 nmi_intc: interrupt-controller@7010320 { 951 compatible = "allwinner,sun50i-h616-nmi", 952 "allwinner,sun9i-a80-nmi"; 953 reg = <0x07010320 0xc>; 954 interrupt-controller; 955 #interrupt-cells = <2>; 956 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 957 }; 958 959 r_pio: pinctrl@7022000 { 960 compatible = "allwinner,sun50i-h616-r-pinctrl"; 961 reg = <0x07022000 0x400>; 962 clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, 963 <&rtc CLK_OSC32K>; 964 clock-names = "apb", "hosc", "losc"; 965 gpio-controller; 966 #gpio-cells = <3>; 967 968 /omit-if-no-ref/ 969 r_i2c_pins: r-i2c-pins { 970 pins = "PL0", "PL1"; 971 function = "s_i2c"; 972 }; 973 974 r_rsb_pins: r-rsb-pins { 975 pins = "PL0", "PL1"; 976 function = "s_rsb"; 977 }; 978 }; 979 980 ir: ir@7040000 { 981 compatible = "allwinner,sun50i-h616-ir", 982 "allwinner,sun6i-a31-ir"; 983 reg = <0x07040000 0x400>; 984 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 985 clocks = <&r_ccu CLK_R_APB1_IR>, 986 <&r_ccu CLK_IR>; 987 clock-names = "apb", "ir"; 988 resets = <&r_ccu RST_R_APB1_IR>; 989 pinctrl-names = "default"; 990 pinctrl-0 = <&ir_rx_pin>; 991 status = "disabled"; 992 }; 993 994 r_i2c: i2c@7081400 { 995 compatible = "allwinner,sun50i-h616-i2c", 996 "allwinner,sun8i-v536-i2c", 997 "allwinner,sun6i-a31-i2c"; 998 reg = <0x07081400 0x400>; 999 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 1000 clocks = <&r_ccu CLK_R_APB2_I2C>; 1001 dmas = <&dma 48>, <&dma 48>; 1002 dma-names = "rx", "tx"; 1003 resets = <&r_ccu RST_R_APB2_I2C>; 1004 pinctrl-names = "default"; 1005 pinctrl-0 = <&r_i2c_pins>; 1006 status = "disabled"; 1007 #address-cells = <1>; 1008 #size-cells = <0>; 1009 }; 1010 1011 r_rsb: rsb@7083000 { 1012 compatible = "allwinner,sun50i-h616-rsb", 1013 "allwinner,sun8i-a23-rsb"; 1014 reg = <0x07083000 0x400>; 1015 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 1016 clocks = <&r_ccu CLK_R_APB2_RSB>; 1017 clock-frequency = <3000000>; 1018 resets = <&r_ccu RST_R_APB2_RSB>; 1019 pinctrl-names = "default"; 1020 pinctrl-0 = <&r_rsb_pins>; 1021 status = "disabled"; 1022 #address-cells = <1>; 1023 #size-cells = <0>; 1024 }; 1025 }; 1026 1027 thermal-zones { 1028 cpu-thermal { 1029 polling-delay-passive = <500>; 1030 polling-delay = <1000>; 1031 thermal-sensors = <&ths 2>; 1032 sustainable-power = <1000>; 1033 1034 trips { 1035 cpu_threshold: cpu-trip-0 { 1036 temperature = <60000>; 1037 type = "passive"; 1038 hysteresis = <0>; 1039 }; 1040 cpu_target: cpu-trip-1 { 1041 temperature = <70000>; 1042 type = "passive"; 1043 hysteresis = <0>; 1044 }; 1045 cpu_critical: cpu-trip-2 { 1046 temperature = <110000>; 1047 type = "critical"; 1048 hysteresis = <0>; 1049 }; 1050 }; 1051 }; 1052 1053 gpu-thermal { 1054 polling-delay-passive = <500>; 1055 polling-delay = <1000>; 1056 thermal-sensors = <&ths 0>; 1057 sustainable-power = <1100>; 1058 1059 trips { 1060 gpu_temp_critical: gpu-trip-0 { 1061 temperature = <110000>; 1062 type = "critical"; 1063 hysteresis = <0>; 1064 }; 1065 }; 1066 }; 1067 1068 ve-thermal { 1069 polling-delay-passive = <0>; 1070 polling-delay = <0>; 1071 thermal-sensors = <&ths 1>; 1072 1073 trips { 1074 ve_temp_critical: ve-trip-0 { 1075 temperature = <110000>; 1076 type = "critical"; 1077 hysteresis = <0>; 1078 }; 1079 }; 1080 }; 1081 1082 ddr-thermal { 1083 polling-delay-passive = <0>; 1084 polling-delay = <0>; 1085 thermal-sensors = <&ths 3>; 1086 1087 trips { 1088 ddr_temp_critical: ddr-trip-0 { 1089 temperature = <110000>; 1090 type = "critical"; 1091 hysteresis = <0>; 1092 }; 1093 }; 1094 }; 1095 }; 1096};
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