sun50i-h5.dtsi

  1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2// Copyright (C) 2016 ARM Ltd.
  3
  4#include <arm/allwinner/sunxi-h3-h5.dtsi>
  5
  6#include <dt-bindings/thermal/thermal.h>
  7
  8/ {
  9	cpus {
 10		#address-cells = <1>;
 11		#size-cells = <0>;
 12
 13		cpu0: cpu@0 {
 14			compatible = "arm,cortex-a53";
 15			device_type = "cpu";
 16			reg = <0>;
 17			enable-method = "psci";
 18			clocks = <&ccu CLK_CPUX>;
 19			#cooling-cells = <2>;
 20		};
 21
 22		cpu1: cpu@1 {
 23			compatible = "arm,cortex-a53";
 24			device_type = "cpu";
 25			reg = <1>;
 26			enable-method = "psci";
 27			clocks = <&ccu CLK_CPUX>;
 28			#cooling-cells = <2>;
 29		};
 30
 31		cpu2: cpu@2 {
 32			compatible = "arm,cortex-a53";
 33			device_type = "cpu";
 34			reg = <2>;
 35			enable-method = "psci";
 36			clocks = <&ccu CLK_CPUX>;
 37			#cooling-cells = <2>;
 38		};
 39
 40		cpu3: cpu@3 {
 41			compatible = "arm,cortex-a53";
 42			device_type = "cpu";
 43			reg = <3>;
 44			enable-method = "psci";
 45			clocks = <&ccu CLK_CPUX>;
 46			#cooling-cells = <2>;
 47		};
 48	};
 49
 50	pmu {
 51		compatible = "arm,cortex-a53-pmu";
 52		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 53			     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 54			     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 55			     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 56		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 57	};
 58
 59	psci {
 60		compatible = "arm,psci-0.2";
 61		method = "smc";
 62	};
 63
 64	timer {
 65		compatible = "arm,armv8-timer";
 66		arm,no-tick-in-suspend;
 67		interrupts = <GIC_PPI 13
 68				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 69			     <GIC_PPI 14
 70				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 71			     <GIC_PPI 11
 72				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 73			     <GIC_PPI 10
 74				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 75	};
 76
 77	soc {
 78		syscon: system-control@1c00000 {
 79			compatible = "allwinner,sun50i-h5-system-control";
 80			reg = <0x01c00000 0x1000>;
 81			#address-cells = <1>;
 82			#size-cells = <1>;
 83			ranges;
 84
 85			sram_c1: sram@18000 {
 86				compatible = "mmio-sram";
 87				reg = <0x00018000 0x1c000>;
 88				#address-cells = <1>;
 89				#size-cells = <1>;
 90				ranges = <0 0x00018000 0x1c000>;
 91
 92				ve_sram: sram-section@0 {
 93					compatible = "allwinner,sun50i-h5-sram-c1",
 94						     "allwinner,sun4i-a10-sram-c1";
 95					reg = <0x000000 0x1c000>;
 96				};
 97			};
 98		};
 99
100		video-codec@1c0e000 {
101			compatible = "allwinner,sun50i-h5-video-engine";
102			reg = <0x01c0e000 0x1000>;
103			clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
104				 <&ccu CLK_DRAM_VE>;
105			clock-names = "ahb", "mod", "ram";
106			resets = <&ccu RST_BUS_VE>;
107			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
108			allwinner,sram = <&ve_sram 1>;
109		};
110
111		crypto: crypto@1c15000 {
112			compatible = "allwinner,sun50i-h5-crypto";
113			reg = <0x01c15000 0x1000>;
114			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
115			clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
116			clock-names = "bus", "mod";
117			resets = <&ccu RST_BUS_CE>;
118		};
119
120		deinterlace: deinterlace@1e00000 {
121			compatible = "allwinner,sun8i-h3-deinterlace";
122			reg = <0x01e00000 0x20000>;
123			clocks = <&ccu CLK_BUS_DEINTERLACE>,
124				 <&ccu CLK_DEINTERLACE>,
125				 <&ccu CLK_DRAM_DEINTERLACE>;
126			clock-names = "bus", "mod", "ram";
127			resets = <&ccu RST_BUS_DEINTERLACE>;
128			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
129			interconnects = <&mbus 9>;
130			interconnect-names = "dma-mem";
131		};
132
133		mali: gpu@1e80000 {
134			compatible = "allwinner,sun50i-h5-mali", "arm,mali-450";
135			reg = <0x01e80000 0x30000>;
136			/*
137			 * While the datasheet lists an interrupt for the
138			 * PMU, the actual silicon does not have the PMU
139			 * block. Reads all return zero, and writes are
140			 * ignored.
141			 */
142			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
143				     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
144				     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
145				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
146				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
147				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
148				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
149				     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
150				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
151				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
152				     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
153			interrupt-names = "gp",
154					  "gpmmu",
155					  "pp",
156					  "pp0",
157					  "ppmmu0",
158					  "pp1",
159					  "ppmmu1",
160					  "pp2",
161					  "ppmmu2",
162					  "pp3",
163					  "ppmmu3";
164			clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
165			clock-names = "bus", "core";
166			resets = <&ccu RST_BUS_GPU>;
167
168			assigned-clocks = <&ccu CLK_GPU>;
169			assigned-clock-rates = <384000000>;
170		};
171
172		ths: thermal-sensor@1c25000 {
173			compatible = "allwinner,sun50i-h5-ths";
174			reg = <0x01c25000 0x400>;
175			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
176			resets = <&ccu RST_BUS_THS>;
177			clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
178			clock-names = "bus", "mod";
179			nvmem-cells = <&ths_calibration>;
180			nvmem-cell-names = "calibration";
181			#thermal-sensor-cells = <1>;
182		};
183	};
184
185	thermal-zones {
186		cpu_thermal: cpu-thermal {
187			polling-delay-passive = <0>;
188			polling-delay = <0>;
189			thermal-sensors = <&ths 0>;
190
191			trips {
192				cpu_hot_trip: cpu-hot {
193					temperature = <80000>;
194					hysteresis = <2000>;
195					type = "passive";
196				};
197
198				cpu_very_hot_trip: cpu-very-hot {
199					temperature = <100000>;
200					hysteresis = <0>;
201					type = "critical";
202				};
203			};
204
205			cooling-maps {
206				map0 {
207					trip = <&cpu_hot_trip>;
208					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
209							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
210							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
211							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
212				};
213			};
214		};
215
216		gpu-thermal {
217			polling-delay-passive = <0>;
218			polling-delay = <0>;
219			thermal-sensors = <&ths 1>;
220		};
221	};
222};
223
224&ccu {
225	compatible = "allwinner,sun50i-h5-ccu";
226};
227
228&display_clocks {
229	compatible = "allwinner,sun50i-h5-de2-clk";
230};
231
232&mbus {
233	compatible = "allwinner,sun50i-h5-mbus";
234};
235
236&mmc0 {
237	compatible = "allwinner,sun50i-h5-mmc",
238		     "allwinner,sun50i-a64-mmc";
239	clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
240	clock-names = "ahb", "mmc";
241};
242
243&mmc1 {
244	compatible = "allwinner,sun50i-h5-mmc",
245		     "allwinner,sun50i-a64-mmc";
246	clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
247	clock-names = "ahb", "mmc";
248};
249
250&mmc2 {
251	compatible = "allwinner,sun50i-h5-emmc",
252		     "allwinner,sun50i-a64-emmc";
253	clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
254	clock-names = "ahb", "mmc";
255};
256
257&pio {
258	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
259		     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
260		     <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
261	compatible = "allwinner,sun50i-h5-pinctrl";
262};
263
264&rtc {
265	compatible = "allwinner,sun50i-h5-rtc";
266};
267
268&sid {
269	compatible = "allwinner,sun50i-h5-sid";
270};