mmu.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 *  linux/arch/arm/mm/mmu.c
   4 *
   5 *  Copyright (C) 1995-2005 Russell King
   6 */
   7#include <linux/module.h>
   8#include <linux/kernel.h>
   9#include <linux/errno.h>
  10#include <linux/init.h>
  11#include <linux/mman.h>
  12#include <linux/nodemask.h>
  13#include <linux/memblock.h>
  14#include <linux/fs.h>
  15#include <linux/vmalloc.h>
  16#include <linux/sizes.h>
  17
  18#include <asm/cp15.h>
  19#include <asm/cputype.h>
  20#include <asm/cachetype.h>
  21#include <asm/sections.h>
  22#include <asm/setup.h>
  23#include <asm/smp_plat.h>
  24#include <asm/tcm.h>
  25#include <asm/tlb.h>
  26#include <asm/highmem.h>
  27#include <asm/system_info.h>
  28#include <asm/traps.h>
  29#include <asm/procinfo.h>
  30#include <asm/page.h>
  31#include <asm/pgalloc.h>
  32#include <asm/kasan_def.h>
  33
  34#include <asm/mach/arch.h>
  35#include <asm/mach/map.h>
  36#include <asm/mach/pci.h>
  37#include <asm/fixmap.h>
  38
  39#include "fault.h"
  40#include "mm.h"
  41
  42extern unsigned long __atags_pointer;
  43
  44/*
  45 * empty_zero_page is a special page that is used for
  46 * zero-initialized data and COW.
  47 */
  48struct page *empty_zero_page;
  49EXPORT_SYMBOL(empty_zero_page);
  50
  51/*
  52 * The pmd table for the upper-most set of pages.
  53 */
  54pmd_t *top_pmd;
  55
  56pmdval_t user_pmd_table = _PAGE_USER_TABLE;
  57
  58#define CPOLICY_UNCACHED	0
  59#define CPOLICY_BUFFERED	1
  60#define CPOLICY_WRITETHROUGH	2
  61#define CPOLICY_WRITEBACK	3
  62#define CPOLICY_WRITEALLOC	4
  63
  64static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
  65static unsigned int ecc_mask __initdata = 0;
  66pgprot_t pgprot_user;
  67pgprot_t pgprot_kernel;
  68
  69EXPORT_SYMBOL(pgprot_user);
  70EXPORT_SYMBOL(pgprot_kernel);
  71
  72struct cachepolicy {
  73	const char	policy[16];
  74	unsigned int	cr_mask;
  75	pmdval_t	pmd;
  76	pteval_t	pte;
  77};
  78
  79static struct cachepolicy cache_policies[] __initdata = {
  80	{
  81		.policy		= "uncached",
  82		.cr_mask	= CR_W|CR_C,
  83		.pmd		= PMD_SECT_UNCACHED,
  84		.pte		= L_PTE_MT_UNCACHED,
  85	}, {
  86		.policy		= "buffered",
  87		.cr_mask	= CR_C,
  88		.pmd		= PMD_SECT_BUFFERED,
  89		.pte		= L_PTE_MT_BUFFERABLE,
  90	}, {
  91		.policy		= "writethrough",
  92		.cr_mask	= 0,
  93		.pmd		= PMD_SECT_WT,
  94		.pte		= L_PTE_MT_WRITETHROUGH,
  95	}, {
  96		.policy		= "writeback",
  97		.cr_mask	= 0,
  98		.pmd		= PMD_SECT_WB,
  99		.pte		= L_PTE_MT_WRITEBACK,
 100	}, {
 101		.policy		= "writealloc",
 102		.cr_mask	= 0,
 103		.pmd		= PMD_SECT_WBWA,
 104		.pte		= L_PTE_MT_WRITEALLOC,
 105	}
 106};
 107
 108#ifdef CONFIG_CPU_CP15
 109static unsigned long initial_pmd_value __initdata = 0;
 110
 111/*
 112 * Initialise the cache_policy variable with the initial state specified
 113 * via the "pmd" value.  This is used to ensure that on ARMv6 and later,
 114 * the C code sets the page tables up with the same policy as the head
 115 * assembly code, which avoids an illegal state where the TLBs can get
 116 * confused.  See comments in early_cachepolicy() for more information.
 117 */
 118void __init init_default_cache_policy(unsigned long pmd)
 119{
 120	int i;
 121
 122	initial_pmd_value = pmd;
 123
 124	pmd &= PMD_SECT_CACHE_MASK;
 125
 126	for (i = 0; i < ARRAY_SIZE(cache_policies); i++)
 127		if (cache_policies[i].pmd == pmd) {
 128			cachepolicy = i;
 129			break;
 130		}
 131
 132	if (i == ARRAY_SIZE(cache_policies))
 133		pr_err("ERROR: could not find cache policy\n");
 134}
 135
 136/*
 137 * These are useful for identifying cache coherency problems by allowing
 138 * the cache or the cache and writebuffer to be turned off.  (Note: the
 139 * write buffer should not be on and the cache off).
 140 */
 141static int __init early_cachepolicy(char *p)
 142{
 143	int i, selected = -1;
 144
 145	for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
 146		int len = strlen(cache_policies[i].policy);
 147
 148		if (memcmp(p, cache_policies[i].policy, len) == 0) {
 149			selected = i;
 150			break;
 151		}
 152	}
 153
 154	if (selected == -1)
 155		pr_err("ERROR: unknown or unsupported cache policy\n");
 156
 157	/*
 158	 * This restriction is partly to do with the way we boot; it is
 159	 * unpredictable to have memory mapped using two different sets of
 160	 * memory attributes (shared, type, and cache attribs).  We can not
 161	 * change these attributes once the initial assembly has setup the
 162	 * page tables.
 163	 */
 164	if (cpu_architecture() >= CPU_ARCH_ARMv6 && selected != cachepolicy) {
 165		pr_warn("Only cachepolicy=%s supported on ARMv6 and later\n",
 166			cache_policies[cachepolicy].policy);
 167		return 0;
 168	}
 169
 170	if (selected != cachepolicy) {
 171		unsigned long cr = __clear_cr(cache_policies[selected].cr_mask);
 172		cachepolicy = selected;
 173		flush_cache_all();
 174		set_cr(cr);
 175	}
 176	return 0;
 177}
 178early_param("cachepolicy", early_cachepolicy);
 179
 180static int __init early_nocache(char *__unused)
 181{
 182	char *p = "buffered";
 183	pr_warn("nocache is deprecated; use cachepolicy=%s\n", p);
 184	early_cachepolicy(p);
 185	return 0;
 186}
 187early_param("nocache", early_nocache);
 188
 189static int __init early_nowrite(char *__unused)
 190{
 191	char *p = "uncached";
 192	pr_warn("nowb is deprecated; use cachepolicy=%s\n", p);
 193	early_cachepolicy(p);
 194	return 0;
 195}
 196early_param("nowb", early_nowrite);
 197
 198#ifndef CONFIG_ARM_LPAE
 199static int __init early_ecc(char *p)
 200{
 201	if (memcmp(p, "on", 2) == 0)
 202		ecc_mask = PMD_PROTECTION;
 203	else if (memcmp(p, "off", 3) == 0)
 204		ecc_mask = 0;
 205	return 0;
 206}
 207early_param("ecc", early_ecc);
 208#endif
 209
 210#else /* ifdef CONFIG_CPU_CP15 */
 211
 212static int __init early_cachepolicy(char *p)
 213{
 214	pr_warn("cachepolicy kernel parameter not supported without cp15\n");
 215	return 0;
 216}
 217early_param("cachepolicy", early_cachepolicy);
 218
 219static int __init noalign_setup(char *__unused)
 220{
 221	pr_warn("noalign kernel parameter not supported without cp15\n");
 222	return 1;
 223}
 224__setup("noalign", noalign_setup);
 225
 226#endif /* ifdef CONFIG_CPU_CP15 / else */
 227
 228#define PROT_PTE_DEVICE		L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
 229#define PROT_PTE_S2_DEVICE	PROT_PTE_DEVICE
 230#define PROT_SECT_DEVICE	PMD_TYPE_SECT|PMD_SECT_AP_WRITE
 231
 232static struct mem_type mem_types[] __ro_after_init = {
 233	[MT_DEVICE] = {		  /* Strongly ordered / ARMv6 shared device */
 234		.prot_pte	= PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
 235				  L_PTE_SHARED,
 236		.prot_l1	= PMD_TYPE_TABLE,
 237		.prot_sect	= PROT_SECT_DEVICE | PMD_SECT_S,
 238		.domain		= DOMAIN_IO,
 239	},
 240	[MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
 241		.prot_pte	= PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
 242		.prot_l1	= PMD_TYPE_TABLE,
 243		.prot_sect	= PROT_SECT_DEVICE,
 244		.domain		= DOMAIN_IO,
 245	},
 246	[MT_DEVICE_CACHED] = {	  /* ioremap_cache */
 247		.prot_pte	= PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
 248		.prot_l1	= PMD_TYPE_TABLE,
 249		.prot_sect	= PROT_SECT_DEVICE | PMD_SECT_WB,
 250		.domain		= DOMAIN_IO,
 251	},
 252	[MT_DEVICE_WC] = {	/* ioremap_wc */
 253		.prot_pte	= PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
 254		.prot_l1	= PMD_TYPE_TABLE,
 255		.prot_sect	= PROT_SECT_DEVICE,
 256		.domain		= DOMAIN_IO,
 257	},
 258	[MT_UNCACHED] = {
 259		.prot_pte	= PROT_PTE_DEVICE,
 260		.prot_l1	= PMD_TYPE_TABLE,
 261		.prot_sect	= PMD_TYPE_SECT | PMD_SECT_XN,
 262		.domain		= DOMAIN_IO,
 263	},
 264	[MT_CACHECLEAN] = {
 265		.prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
 266		.domain    = DOMAIN_KERNEL,
 267	},
 268#ifndef CONFIG_ARM_LPAE
 269	[MT_MINICLEAN] = {
 270		.prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
 271		.domain    = DOMAIN_KERNEL,
 272	},
 273#endif
 274	[MT_LOW_VECTORS] = {
 275		.prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 276				L_PTE_RDONLY,
 277		.prot_l1   = PMD_TYPE_TABLE,
 278		.domain    = DOMAIN_VECTORS,
 279	},
 280	[MT_HIGH_VECTORS] = {
 281		.prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 282				L_PTE_USER | L_PTE_RDONLY,
 283		.prot_l1   = PMD_TYPE_TABLE,
 284		.domain    = DOMAIN_VECTORS,
 285	},
 286	[MT_MEMORY_RWX] = {
 287		.prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
 288		.prot_l1   = PMD_TYPE_TABLE,
 289		.prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
 290		.domain    = DOMAIN_KERNEL,
 291	},
 292	[MT_MEMORY_RW] = {
 293		.prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 294			     L_PTE_XN,
 295		.prot_l1   = PMD_TYPE_TABLE,
 296		.prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
 297		.domain    = DOMAIN_KERNEL,
 298	},
 299	[MT_MEMORY_RO] = {
 300		.prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 301			     L_PTE_XN | L_PTE_RDONLY,
 302		.prot_l1   = PMD_TYPE_TABLE,
 303#ifdef CONFIG_ARM_LPAE
 304		.prot_sect = PMD_TYPE_SECT | L_PMD_SECT_RDONLY | PMD_SECT_AP2,
 305#else
 306		.prot_sect = PMD_TYPE_SECT,
 307#endif
 308		.domain    = DOMAIN_KERNEL,
 309	},
 310	[MT_ROM] = {
 311		.prot_sect = PMD_TYPE_SECT,
 312		.domain    = DOMAIN_KERNEL,
 313	},
 314	[MT_MEMORY_RWX_NONCACHED] = {
 315		.prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 316				L_PTE_MT_BUFFERABLE,
 317		.prot_l1   = PMD_TYPE_TABLE,
 318		.prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
 319		.domain    = DOMAIN_KERNEL,
 320	},
 321	[MT_MEMORY_RW_DTCM] = {
 322		.prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 323				L_PTE_XN,
 324		.prot_l1   = PMD_TYPE_TABLE,
 325		.prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
 326		.domain    = DOMAIN_KERNEL,
 327	},
 328	[MT_MEMORY_RWX_ITCM] = {
 329		.prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
 330		.prot_l1   = PMD_TYPE_TABLE,
 331		.domain    = DOMAIN_KERNEL,
 332	},
 333	[MT_MEMORY_RW_SO] = {
 334		.prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 335				L_PTE_MT_UNCACHED | L_PTE_XN,
 336		.prot_l1   = PMD_TYPE_TABLE,
 337		.prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S |
 338				PMD_SECT_UNCACHED | PMD_SECT_XN,
 339		.domain    = DOMAIN_KERNEL,
 340	},
 341	[MT_MEMORY_DMA_READY] = {
 342		.prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 343				L_PTE_XN,
 344		.prot_l1   = PMD_TYPE_TABLE,
 345		.domain    = DOMAIN_KERNEL,
 346	},
 347};
 348
 349const struct mem_type *get_mem_type(unsigned int type)
 350{
 351	return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
 352}
 353EXPORT_SYMBOL(get_mem_type);
 354
 355static pte_t *(*pte_offset_fixmap)(pmd_t *dir, unsigned long addr);
 356
 357static pte_t bm_pte[PTRS_PER_PTE + PTE_HWTABLE_PTRS]
 358	__aligned(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE) __initdata;
 359
 360static pte_t * __init pte_offset_early_fixmap(pmd_t *dir, unsigned long addr)
 361{
 362	return &bm_pte[pte_index(addr)];
 363}
 364
 365static pte_t *pte_offset_late_fixmap(pmd_t *dir, unsigned long addr)
 366{
 367	return pte_offset_kernel(dir, addr);
 368}
 369
 370static inline pmd_t * __init fixmap_pmd(unsigned long addr)
 371{
 372	return pmd_off_k(addr);
 373}
 374
 375void __init early_fixmap_init(void)
 376{
 377	pmd_t *pmd;
 378
 379	/*
 380	 * The early fixmap range spans multiple pmds, for which
 381	 * we are not prepared:
 382	 */
 383	BUILD_BUG_ON((__fix_to_virt(__end_of_early_ioremap_region) >> PMD_SHIFT)
 384		     != FIXADDR_TOP >> PMD_SHIFT);
 385
 386	pmd = fixmap_pmd(FIXADDR_TOP);
 387	pmd_populate_kernel(&init_mm, pmd, bm_pte);
 388
 389	pte_offset_fixmap = pte_offset_early_fixmap;
 390}
 391
 392/*
 393 * To avoid TLB flush broadcasts, this uses local_flush_tlb_kernel_range().
 394 * As a result, this can only be called with preemption disabled, as under
 395 * stop_machine().
 396 */
 397void __set_fixmap(enum fixed_addresses idx, phys_addr_t phys, pgprot_t prot)
 398{
 399	unsigned long vaddr = __fix_to_virt(idx);
 400	pte_t *pte = pte_offset_fixmap(pmd_off_k(vaddr), vaddr);
 401
 402	/* Make sure fixmap region does not exceed available allocation. */
 403	BUILD_BUG_ON(__fix_to_virt(__end_of_fixed_addresses) < FIXADDR_START);
 404	BUG_ON(idx >= __end_of_fixed_addresses);
 405
 406	/* We support only device mappings before pgprot_kernel is set. */
 407	if (WARN_ON(pgprot_val(prot) != pgprot_val(FIXMAP_PAGE_IO) &&
 408		    pgprot_val(prot) && pgprot_val(pgprot_kernel) == 0))
 409		return;
 410
 411	if (pgprot_val(prot))
 412		set_pte_at(NULL, vaddr, pte,
 413			pfn_pte(phys >> PAGE_SHIFT, prot));
 414	else
 415		pte_clear(NULL, vaddr, pte);
 416	local_flush_tlb_kernel_range(vaddr, vaddr + PAGE_SIZE);
 417}
 418
 419static pgprot_t protection_map[16] __ro_after_init = {
 420	[VM_NONE]					= __PAGE_NONE,
 421	[VM_READ]					= __PAGE_READONLY,
 422	[VM_WRITE]					= __PAGE_COPY,
 423	[VM_WRITE | VM_READ]				= __PAGE_COPY,
 424	[VM_EXEC]					= __PAGE_READONLY_EXEC,
 425	[VM_EXEC | VM_READ]				= __PAGE_READONLY_EXEC,
 426	[VM_EXEC | VM_WRITE]				= __PAGE_COPY_EXEC,
 427	[VM_EXEC | VM_WRITE | VM_READ]			= __PAGE_COPY_EXEC,
 428	[VM_SHARED]					= __PAGE_NONE,
 429	[VM_SHARED | VM_READ]				= __PAGE_READONLY,
 430	[VM_SHARED | VM_WRITE]				= __PAGE_SHARED,
 431	[VM_SHARED | VM_WRITE | VM_READ]		= __PAGE_SHARED,
 432	[VM_SHARED | VM_EXEC]				= __PAGE_READONLY_EXEC,
 433	[VM_SHARED | VM_EXEC | VM_READ]			= __PAGE_READONLY_EXEC,
 434	[VM_SHARED | VM_EXEC | VM_WRITE]		= __PAGE_SHARED_EXEC,
 435	[VM_SHARED | VM_EXEC | VM_WRITE | VM_READ]	= __PAGE_SHARED_EXEC
 436};
 437DECLARE_VM_GET_PAGE_PROT
 438
 439/*
 440 * Adjust the PMD section entries according to the CPU in use.
 441 */
 442static void __init build_mem_type_table(void)
 443{
 444	struct cachepolicy *cp;
 445	unsigned int cr = get_cr();
 446	pteval_t user_pgprot, kern_pgprot, vecs_pgprot;
 447	int cpu_arch = cpu_architecture();
 448	int i;
 449
 450	if (cpu_arch < CPU_ARCH_ARMv6) {
 451#if defined(CONFIG_CPU_DCACHE_DISABLE)
 452		if (cachepolicy > CPOLICY_BUFFERED)
 453			cachepolicy = CPOLICY_BUFFERED;
 454#elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
 455		if (cachepolicy > CPOLICY_WRITETHROUGH)
 456			cachepolicy = CPOLICY_WRITETHROUGH;
 457#endif
 458	}
 459	if (cpu_arch < CPU_ARCH_ARMv5) {
 460		if (cachepolicy >= CPOLICY_WRITEALLOC)
 461			cachepolicy = CPOLICY_WRITEBACK;
 462		ecc_mask = 0;
 463	}
 464
 465	if (is_smp()) {
 466		if (cachepolicy != CPOLICY_WRITEALLOC) {
 467			pr_warn("Forcing write-allocate cache policy for SMP\n");
 468			cachepolicy = CPOLICY_WRITEALLOC;
 469		}
 470		if (!(initial_pmd_value & PMD_SECT_S)) {
 471			pr_warn("Forcing shared mappings for SMP\n");
 472			initial_pmd_value |= PMD_SECT_S;
 473		}
 474	}
 475
 476	/*
 477	 * Strip out features not present on earlier architectures.
 478	 * Pre-ARMv5 CPUs don't have TEX bits.  Pre-ARMv6 CPUs or those
 479	 * without extended page tables don't have the 'Shared' bit.
 480	 */
 481	if (cpu_arch < CPU_ARCH_ARMv5)
 482		for (i = 0; i < ARRAY_SIZE(mem_types); i++)
 483			mem_types[i].prot_sect &= ~PMD_SECT_TEX(7);
 484	if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3())
 485		for (i = 0; i < ARRAY_SIZE(mem_types); i++)
 486			mem_types[i].prot_sect &= ~PMD_SECT_S;
 487
 488	/*
 489	 * ARMv5 and lower, bit 4 must be set for page tables (was: cache
 490	 * "update-able on write" bit on ARM610).  However, Xscale and
 491	 * Xscale3 require this bit to be cleared.
 492	 */
 493	if (cpu_is_xscale_family()) {
 494		for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
 495			mem_types[i].prot_sect &= ~PMD_BIT4;
 496			mem_types[i].prot_l1 &= ~PMD_BIT4;
 497		}
 498	} else if (cpu_arch < CPU_ARCH_ARMv6) {
 499		for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
 500			if (mem_types[i].prot_l1)
 501				mem_types[i].prot_l1 |= PMD_BIT4;
 502			if (mem_types[i].prot_sect)
 503				mem_types[i].prot_sect |= PMD_BIT4;
 504		}
 505	}
 506
 507	/*
 508	 * Mark the device areas according to the CPU/architecture.
 509	 */
 510	if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) {
 511		if (!cpu_is_xsc3()) {
 512			/*
 513			 * Mark device regions on ARMv6+ as execute-never
 514			 * to prevent speculative instruction fetches.
 515			 */
 516			mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN;
 517			mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN;
 518			mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN;
 519			mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN;
 520
 521			/* Also setup NX memory mapping */
 522			mem_types[MT_MEMORY_RW].prot_sect |= PMD_SECT_XN;
 523			mem_types[MT_MEMORY_RO].prot_sect |= PMD_SECT_XN;
 524		}
 525		if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
 526			/*
 527			 * For ARMv7 with TEX remapping,
 528			 * - shared device is SXCB=1100
 529			 * - nonshared device is SXCB=0100
 530			 * - write combine device mem is SXCB=0001
 531			 * (Uncached Normal memory)
 532			 */
 533			mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1);
 534			mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1);
 535			mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
 536		} else if (cpu_is_xsc3()) {
 537			/*
 538			 * For Xscale3,
 539			 * - shared device is TEXCB=00101
 540			 * - nonshared device is TEXCB=01000
 541			 * - write combine device mem is TEXCB=00100
 542			 * (Inner/Outer Uncacheable in xsc3 parlance)
 543			 */
 544			mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED;
 545			mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
 546			mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
 547		} else {
 548			/*
 549			 * For ARMv6 and ARMv7 without TEX remapping,
 550			 * - shared device is TEXCB=00001
 551			 * - nonshared device is TEXCB=01000
 552			 * - write combine device mem is TEXCB=00100
 553			 * (Uncached Normal in ARMv6 parlance).
 554			 */
 555			mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
 556			mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
 557			mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
 558		}
 559	} else {
 560		/*
 561		 * On others, write combining is "Uncached/Buffered"
 562		 */
 563		mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
 564	}
 565
 566	/*
 567	 * Now deal with the memory-type mappings
 568	 */
 569	cp = &cache_policies[cachepolicy];
 570	vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
 571
 572#ifndef CONFIG_ARM_LPAE
 573	/*
 574	 * We don't use domains on ARMv6 (since this causes problems with
 575	 * v6/v7 kernels), so we must use a separate memory type for user
 576	 * r/o, kernel r/w to map the vectors page.
 577	 */
 578	if (cpu_arch == CPU_ARCH_ARMv6)
 579		vecs_pgprot |= L_PTE_MT_VECTORS;
 580
 581	/*
 582	 * Check is it with support for the PXN bit
 583	 * in the Short-descriptor translation table format descriptors.
 584	 */
 585	if (cpu_arch == CPU_ARCH_ARMv7 &&
 586		(read_cpuid_ext(CPUID_EXT_MMFR0) & 0xF) >= 4) {
 587		user_pmd_table |= PMD_PXNTABLE;
 588	}
 589#endif
 590
 591	/*
 592	 * ARMv6 and above have extended page tables.
 593	 */
 594	if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
 595#ifndef CONFIG_ARM_LPAE
 596		/*
 597		 * Mark cache clean areas and XIP ROM read only
 598		 * from SVC mode and no access from userspace.
 599		 */
 600		mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 601		mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 602		mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 603		mem_types[MT_MEMORY_RO].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 604#endif
 605
 606		/*
 607		 * If the initial page tables were created with the S bit
 608		 * set, then we need to do the same here for the same
 609		 * reasons given in early_cachepolicy().
 610		 */
 611		if (initial_pmd_value & PMD_SECT_S) {
 612			user_pgprot |= L_PTE_SHARED;
 613			kern_pgprot |= L_PTE_SHARED;
 614			vecs_pgprot |= L_PTE_SHARED;
 615			mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
 616			mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
 617			mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
 618			mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
 619			mem_types[MT_MEMORY_RWX].prot_sect |= PMD_SECT_S;
 620			mem_types[MT_MEMORY_RWX].prot_pte |= L_PTE_SHARED;
 621			mem_types[MT_MEMORY_RW].prot_sect |= PMD_SECT_S;
 622			mem_types[MT_MEMORY_RW].prot_pte |= L_PTE_SHARED;
 623			mem_types[MT_MEMORY_RO].prot_sect |= PMD_SECT_S;
 624			mem_types[MT_MEMORY_RO].prot_pte |= L_PTE_SHARED;
 625			mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED;
 626			mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_S;
 627			mem_types[MT_MEMORY_RWX_NONCACHED].prot_pte |= L_PTE_SHARED;
 628		}
 629	}
 630
 631	/*
 632	 * Non-cacheable Normal - intended for memory areas that must
 633	 * not cause dirty cache line writebacks when used
 634	 */
 635	if (cpu_arch >= CPU_ARCH_ARMv6) {
 636		if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
 637			/* Non-cacheable Normal is XCB = 001 */
 638			mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |=
 639				PMD_SECT_BUFFERED;
 640		} else {
 641			/* For both ARMv6 and non-TEX-remapping ARMv7 */
 642			mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |=
 643				PMD_SECT_TEX(1);
 644		}
 645	} else {
 646		mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
 647	}
 648
 649#ifdef CONFIG_ARM_LPAE
 650	/*
 651	 * Do not generate access flag faults for the kernel mappings.
 652	 */
 653	for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
 654		mem_types[i].prot_pte |= PTE_EXT_AF;
 655		if (mem_types[i].prot_sect)
 656			mem_types[i].prot_sect |= PMD_SECT_AF;
 657	}
 658	kern_pgprot |= PTE_EXT_AF;
 659	vecs_pgprot |= PTE_EXT_AF;
 660
 661	/*
 662	 * Set PXN for user mappings
 663	 */
 664	user_pgprot |= PTE_EXT_PXN;
 665#endif
 666
 667	for (i = 0; i < 16; i++) {
 668		pteval_t v = pgprot_val(protection_map[i]);
 669		protection_map[i] = __pgprot(v | user_pgprot);
 670	}
 671
 672	mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;
 673	mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;
 674
 675	pgprot_user   = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
 676	pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
 677				 L_PTE_DIRTY | kern_pgprot);
 678
 679	mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
 680	mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
 681	mem_types[MT_MEMORY_RWX].prot_sect |= ecc_mask | cp->pmd;
 682	mem_types[MT_MEMORY_RWX].prot_pte |= kern_pgprot;
 683	mem_types[MT_MEMORY_RW].prot_sect |= ecc_mask | cp->pmd;
 684	mem_types[MT_MEMORY_RW].prot_pte |= kern_pgprot;
 685	mem_types[MT_MEMORY_RO].prot_sect |= ecc_mask | cp->pmd;
 686	mem_types[MT_MEMORY_RO].prot_pte |= kern_pgprot;
 687	mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot;
 688	mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= ecc_mask;
 689	mem_types[MT_ROM].prot_sect |= cp->pmd;
 690
 691	switch (cp->pmd) {
 692	case PMD_SECT_WT:
 693		mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
 694		break;
 695	case PMD_SECT_WB:
 696	case PMD_SECT_WBWA:
 697		mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
 698		break;
 699	}
 700	pr_info("Memory policy: %sData cache %s\n",
 701		ecc_mask ? "ECC enabled, " : "", cp->policy);
 702
 703	for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
 704		struct mem_type *t = &mem_types[i];
 705		if (t->prot_l1)
 706			t->prot_l1 |= PMD_DOMAIN(t->domain);
 707		if (t->prot_sect)
 708			t->prot_sect |= PMD_DOMAIN(t->domain);
 709	}
 710}
 711
 712#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
 713pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
 714			      unsigned long size, pgprot_t vma_prot)
 715{
 716	if (!pfn_valid(pfn))
 717		return pgprot_noncached(vma_prot);
 718	else if (file->f_flags & O_SYNC)
 719		return pgprot_writecombine(vma_prot);
 720	return vma_prot;
 721}
 722EXPORT_SYMBOL(phys_mem_access_prot);
 723#endif
 724
 725#define vectors_base()	(vectors_high() ? 0xffff0000 : 0)
 726
 727static void __init *early_alloc(unsigned long sz)
 728{
 729	return memblock_alloc_or_panic(sz, sz);
 730
 731}
 732
 733static void *__init late_alloc(unsigned long sz)
 734{
 735	void *ptdesc = pagetable_alloc(GFP_PGTABLE_KERNEL & ~__GFP_HIGHMEM,
 736			get_order(sz));
 737
 738	if (!ptdesc || !pagetable_pte_ctor(NULL, ptdesc))
 739		BUG();
 740	return ptdesc_address(ptdesc);
 741}
 742
 743static pte_t * __init arm_pte_alloc(pmd_t *pmd, unsigned long addr,
 744				unsigned long prot,
 745				void *(*alloc)(unsigned long sz))
 746{
 747	if (pmd_none(*pmd)) {
 748		pte_t *pte = alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE);
 749		__pmd_populate(pmd, __pa(pte), prot);
 750	}
 751	BUG_ON(pmd_bad(*pmd));
 752	return pte_offset_kernel(pmd, addr);
 753}
 754
 755static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr,
 756				      unsigned long prot)
 757{
 758	return arm_pte_alloc(pmd, addr, prot, early_alloc);
 759}
 760
 761static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
 762				  unsigned long end, unsigned long pfn,
 763				  const struct mem_type *type,
 764				  void *(*alloc)(unsigned long sz),
 765				  bool ng)
 766{
 767	pte_t *pte = arm_pte_alloc(pmd, addr, type->prot_l1, alloc);
 768	do {
 769		set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)),
 770			    ng ? PTE_EXT_NG : 0);
 771		pfn++;
 772	} while (pte++, addr += PAGE_SIZE, addr != end);
 773}
 774
 775static void __init __map_init_section(pmd_t *pmd, unsigned long addr,
 776			unsigned long end, phys_addr_t phys,
 777			const struct mem_type *type, bool ng)
 778{
 779	pmd_t *p = pmd;
 780
 781#ifndef CONFIG_ARM_LPAE
 782	/*
 783	 * In classic MMU format, puds and pmds are folded in to
 784	 * the pgds. pmd_offset gives the PGD entry. PGDs refer to a
 785	 * group of L1 entries making up one logical pointer to
 786	 * an L2 table (2MB), where as PMDs refer to the individual
 787	 * L1 entries (1MB). Hence increment to get the correct
 788	 * offset for odd 1MB sections.
 789	 * (See arch/arm/include/asm/pgtable-2level.h)
 790	 */
 791	if (addr & SECTION_SIZE)
 792		pmd++;
 793#endif
 794	do {
 795		*pmd = __pmd(phys | type->prot_sect | (ng ? PMD_SECT_nG : 0));
 796		phys += SECTION_SIZE;
 797	} while (pmd++, addr += SECTION_SIZE, addr != end);
 798
 799	flush_pmd_entry(p);
 800}
 801
 802static void __init alloc_init_pmd(pud_t *pud, unsigned long addr,
 803				      unsigned long end, phys_addr_t phys,
 804				      const struct mem_type *type,
 805				      void *(*alloc)(unsigned long sz), bool ng)
 806{
 807	pmd_t *pmd = pmd_offset(pud, addr);
 808	unsigned long next;
 809
 810	do {
 811		/*
 812		 * With LPAE, we must loop over to map
 813		 * all the pmds for the given range.
 814		 */
 815		next = pmd_addr_end(addr, end);
 816
 817		/*
 818		 * Try a section mapping - addr, next and phys must all be
 819		 * aligned to a section boundary.
 820		 */
 821		if (type->prot_sect &&
 822				((addr | next | phys) & ~SECTION_MASK) == 0) {
 823			__map_init_section(pmd, addr, next, phys, type, ng);
 824		} else {
 825			alloc_init_pte(pmd, addr, next,
 826				       __phys_to_pfn(phys), type, alloc, ng);
 827		}
 828
 829		phys += next - addr;
 830
 831	} while (pmd++, addr = next, addr != end);
 832}
 833
 834static void __init alloc_init_pud(p4d_t *p4d, unsigned long addr,
 835				  unsigned long end, phys_addr_t phys,
 836				  const struct mem_type *type,
 837				  void *(*alloc)(unsigned long sz), bool ng)
 838{
 839	pud_t *pud = pud_offset(p4d, addr);
 840	unsigned long next;
 841
 842	do {
 843		next = pud_addr_end(addr, end);
 844		alloc_init_pmd(pud, addr, next, phys, type, alloc, ng);
 845		phys += next - addr;
 846	} while (pud++, addr = next, addr != end);
 847}
 848
 849static void __init alloc_init_p4d(pgd_t *pgd, unsigned long addr,
 850				  unsigned long end, phys_addr_t phys,
 851				  const struct mem_type *type,
 852				  void *(*alloc)(unsigned long sz), bool ng)
 853{
 854	p4d_t *p4d = p4d_offset(pgd, addr);
 855	unsigned long next;
 856
 857	do {
 858		next = p4d_addr_end(addr, end);
 859		alloc_init_pud(p4d, addr, next, phys, type, alloc, ng);
 860		phys += next - addr;
 861	} while (p4d++, addr = next, addr != end);
 862}
 863
 864#ifndef CONFIG_ARM_LPAE
 865static void __init create_36bit_mapping(struct mm_struct *mm,
 866					struct map_desc *md,
 867					const struct mem_type *type,
 868					bool ng)
 869{
 870	unsigned long addr, length, end;
 871	phys_addr_t phys;
 872	pgd_t *pgd;
 873
 874	addr = md->virtual;
 875	phys = __pfn_to_phys(md->pfn);
 876	length = PAGE_ALIGN(md->length);
 877
 878	if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
 879		pr_err("MM: CPU does not support supersection mapping for 0x%08llx at 0x%08lx\n",
 880		       (long long)__pfn_to_phys((u64)md->pfn), addr);
 881		return;
 882	}
 883
 884	/* N.B.	ARMv6 supersections are only defined to work with domain 0.
 885	 *	Since domain assignments can in fact be arbitrary, the
 886	 *	'domain == 0' check below is required to insure that ARMv6
 887	 *	supersections are only allocated for domain 0 regardless
 888	 *	of the actual domain assignments in use.
 889	 */
 890	if (type->domain) {
 891		pr_err("MM: invalid domain in supersection mapping for 0x%08llx at 0x%08lx\n",
 892		       (long long)__pfn_to_phys((u64)md->pfn), addr);
 893		return;
 894	}
 895
 896	if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
 897		pr_err("MM: cannot create mapping for 0x%08llx at 0x%08lx invalid alignment\n",
 898		       (long long)__pfn_to_phys((u64)md->pfn), addr);
 899		return;
 900	}
 901
 902	/*
 903	 * Shift bits [35:32] of address into bits [23:20] of PMD
 904	 * (See ARMv6 spec).
 905	 */
 906	phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
 907
 908	pgd = pgd_offset(mm, addr);
 909	end = addr + length;
 910	do {
 911		p4d_t *p4d = p4d_offset(pgd, addr);
 912		pud_t *pud = pud_offset(p4d, addr);
 913		pmd_t *pmd = pmd_offset(pud, addr);
 914		int i;
 915
 916		for (i = 0; i < 16; i++)
 917			*pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER |
 918				       (ng ? PMD_SECT_nG : 0));
 919
 920		addr += SUPERSECTION_SIZE;
 921		phys += SUPERSECTION_SIZE;
 922		pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
 923	} while (addr != end);
 924}
 925#endif	/* !CONFIG_ARM_LPAE */
 926
 927static void __init __create_mapping(struct mm_struct *mm, struct map_desc *md,
 928				    void *(*alloc)(unsigned long sz),
 929				    bool ng)
 930{
 931	unsigned long addr, length, end;
 932	phys_addr_t phys;
 933	const struct mem_type *type;
 934	pgd_t *pgd;
 935
 936	type = &mem_types[md->type];
 937
 938#ifndef CONFIG_ARM_LPAE
 939	/*
 940	 * Catch 36-bit addresses
 941	 */
 942	if (md->pfn >= 0x100000) {
 943		create_36bit_mapping(mm, md, type, ng);
 944		return;
 945	}
 946#endif
 947
 948	addr = md->virtual & PAGE_MASK;
 949	phys = __pfn_to_phys(md->pfn);
 950	length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
 951
 952	if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
 953		pr_warn("BUG: map for 0x%08llx at 0x%08lx can not be mapped using pages, ignoring.\n",
 954			(long long)__pfn_to_phys(md->pfn), addr);
 955		return;
 956	}
 957
 958	pgd = pgd_offset(mm, addr);
 959	end = addr + length;
 960	do {
 961		unsigned long next = pgd_addr_end(addr, end);
 962
 963		alloc_init_p4d(pgd, addr, next, phys, type, alloc, ng);
 964
 965		phys += next - addr;
 966		addr = next;
 967	} while (pgd++, addr != end);
 968}
 969
 970/*
 971 * Create the page directory entries and any necessary
 972 * page tables for the mapping specified by `md'.  We
 973 * are able to cope here with varying sizes and address
 974 * offsets, and we take full advantage of sections and
 975 * supersections.
 976 */
 977static void __init create_mapping(struct map_desc *md)
 978{
 979	if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
 980		pr_warn("BUG: not creating mapping for 0x%08llx at 0x%08lx in user region\n",
 981			(long long)__pfn_to_phys((u64)md->pfn), md->virtual);
 982		return;
 983	}
 984
 985	if (md->type == MT_DEVICE &&
 986	    md->virtual >= PAGE_OFFSET && md->virtual < FIXADDR_START &&
 987	    (md->virtual < VMALLOC_START || md->virtual >= VMALLOC_END)) {
 988		pr_warn("BUG: mapping for 0x%08llx at 0x%08lx out of vmalloc space\n",
 989			(long long)__pfn_to_phys((u64)md->pfn), md->virtual);
 990	}
 991
 992	__create_mapping(&init_mm, md, early_alloc, false);
 993}
 994
 995void __init create_mapping_late(struct mm_struct *mm, struct map_desc *md,
 996				bool ng)
 997{
 998#ifdef CONFIG_ARM_LPAE
 999	p4d_t *p4d;
1000	pud_t *pud;
1001
1002	p4d = p4d_alloc(mm, pgd_offset(mm, md->virtual), md->virtual);
1003	if (WARN_ON(!p4d))
1004		return;
1005	pud = pud_alloc(mm, p4d, md->virtual);
1006	if (WARN_ON(!pud))
1007		return;
1008	pmd_alloc(mm, pud, 0);
1009#endif
1010	__create_mapping(mm, md, late_alloc, ng);
1011}
1012
1013/*
1014 * Create the architecture specific mappings
1015 */
1016void __init iotable_init(struct map_desc *io_desc, int nr)
1017{
1018	struct map_desc *md;
1019	struct vm_struct *vm;
1020	struct static_vm *svm;
1021
1022	if (!nr)
1023		return;
1024
1025	svm = memblock_alloc_or_panic(sizeof(*svm) * nr, __alignof__(*svm));
1026
1027	for (md = io_desc; nr; md++, nr--) {
1028		create_mapping(md);
1029
1030		vm = &svm->vm;
1031		vm->addr = (void *)(md->virtual & PAGE_MASK);
1032		vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
1033		vm->phys_addr = __pfn_to_phys(md->pfn);
1034		vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING;
1035		vm->flags |= VM_ARM_MTYPE(md->type);
1036		vm->caller = iotable_init;
1037		add_static_vm_early(svm++);
1038	}
1039}
1040
1041void __init vm_reserve_area_early(unsigned long addr, unsigned long size,
1042				  void *caller)
1043{
1044	struct vm_struct *vm;
1045	struct static_vm *svm;
1046
1047	svm = memblock_alloc_or_panic(sizeof(*svm), __alignof__(*svm));
1048
1049	vm = &svm->vm;
1050	vm->addr = (void *)addr;
1051	vm->size = size;
1052	vm->flags = VM_IOREMAP | VM_ARM_EMPTY_MAPPING;
1053	vm->caller = caller;
1054	add_static_vm_early(svm);
1055}
1056
1057#ifndef CONFIG_ARM_LPAE
1058
1059/*
1060 * The Linux PMD is made of two consecutive section entries covering 2MB
1061 * (see definition in include/asm/pgtable-2level.h).  However a call to
1062 * create_mapping() may optimize static mappings by using individual
1063 * 1MB section mappings.  This leaves the actual PMD potentially half
1064 * initialized if the top or bottom section entry isn't used, leaving it
1065 * open to problems if a subsequent ioremap() or vmalloc() tries to use
1066 * the virtual space left free by that unused section entry.
1067 *
1068 * Let's avoid the issue by inserting dummy vm entries covering the unused
1069 * PMD halves once the static mappings are in place.
1070 */
1071
1072static void __init pmd_empty_section_gap(unsigned long addr)
1073{
1074	vm_reserve_area_early(addr, SECTION_SIZE, pmd_empty_section_gap);
1075}
1076
1077static void __init fill_pmd_gaps(void)
1078{
1079	struct static_vm *svm;
1080	struct vm_struct *vm;
1081	unsigned long addr, next = 0;
1082	pmd_t *pmd;
1083
1084	list_for_each_entry(svm, &static_vmlist, list) {
1085		vm = &svm->vm;
1086		addr = (unsigned long)vm->addr;
1087		if (addr < next)
1088			continue;
1089
1090		/*
1091		 * Check if this vm starts on an odd section boundary.
1092		 * If so and the first section entry for this PMD is free
1093		 * then we block the corresponding virtual address.
1094		 */
1095		if ((addr & ~PMD_MASK) == SECTION_SIZE) {
1096			pmd = pmd_off_k(addr);
1097			if (pmd_none(*pmd))
1098				pmd_empty_section_gap(addr & PMD_MASK);
1099		}
1100
1101		/*
1102		 * Then check if this vm ends on an odd section boundary.
1103		 * If so and the second section entry for this PMD is empty
1104		 * then we block the corresponding virtual address.
1105		 */
1106		addr += vm->size;
1107		if ((addr & ~PMD_MASK) == SECTION_SIZE) {
1108			pmd = pmd_off_k(addr) + 1;
1109			if (pmd_none(*pmd))
1110				pmd_empty_section_gap(addr);
1111		}
1112
1113		/* no need to look at any vm entry until we hit the next PMD */
1114		next = (addr + PMD_SIZE - 1) & PMD_MASK;
1115	}
1116}
1117
1118#else
1119#define fill_pmd_gaps() do { } while (0)
1120#endif
1121
1122#if defined(CONFIG_PCI) && !defined(CONFIG_NEED_MACH_IO_H)
1123static void __init pci_reserve_io(void)
1124{
1125	struct static_vm *svm;
1126
1127	svm = find_static_vm_vaddr((void *)PCI_IO_VIRT_BASE);
1128	if (svm)
1129		return;
1130
1131	vm_reserve_area_early(PCI_IO_VIRT_BASE, SZ_2M, pci_reserve_io);
1132}
1133#else
1134#define pci_reserve_io() do { } while (0)
1135#endif
1136
1137#ifdef CONFIG_DEBUG_LL
1138void __init debug_ll_io_init(void)
1139{
1140	struct map_desc map;
1141
1142	debug_ll_addr(&map.pfn, &map.virtual);
1143	if (!map.pfn || !map.virtual)
1144		return;
1145	map.pfn = __phys_to_pfn(map.pfn);
1146	map.virtual &= PAGE_MASK;
1147	map.length = PAGE_SIZE;
1148	map.type = MT_DEVICE;
1149	iotable_init(&map, 1);
1150}
1151#endif
1152
1153static unsigned long __initdata vmalloc_size = 240 * SZ_1M;
1154
1155/*
1156 * vmalloc=size forces the vmalloc area to be exactly 'size'
1157 * bytes. This can be used to increase (or decrease) the vmalloc
1158 * area - the default is 240MiB.
1159 */
1160static int __init early_vmalloc(char *arg)
1161{
1162	unsigned long vmalloc_reserve = memparse(arg, NULL);
1163	unsigned long vmalloc_max;
1164
1165	if (vmalloc_reserve < SZ_16M) {
1166		vmalloc_reserve = SZ_16M;
1167		pr_warn("vmalloc area is too small, limiting to %luMiB\n",
1168			vmalloc_reserve >> 20);
1169	}
1170
1171	vmalloc_max = VMALLOC_END - (PAGE_OFFSET + SZ_32M + VMALLOC_OFFSET);
1172	if (vmalloc_reserve > vmalloc_max) {
1173		vmalloc_reserve = vmalloc_max;
1174		pr_warn("vmalloc area is too big, limiting to %luMiB\n",
1175			vmalloc_reserve >> 20);
1176	}
1177
1178	vmalloc_size = vmalloc_reserve;
1179	return 0;
1180}
1181early_param("vmalloc", early_vmalloc);
1182
1183phys_addr_t arm_lowmem_limit __initdata = 0;
1184
1185void __init adjust_lowmem_bounds(void)
1186{
1187	phys_addr_t block_start, block_end, memblock_limit = 0;
1188	u64 vmalloc_limit, i;
1189	phys_addr_t lowmem_limit = 0;
1190
1191	/*
1192	 * Let's use our own (unoptimized) equivalent of __pa() that is
1193	 * not affected by wrap-arounds when sizeof(phys_addr_t) == 4.
1194	 * The result is used as the upper bound on physical memory address
1195	 * and may itself be outside the valid range for which phys_addr_t
1196	 * and therefore __pa() is defined.
1197	 */
1198	vmalloc_limit = (u64)VMALLOC_END - vmalloc_size - VMALLOC_OFFSET -
1199			PAGE_OFFSET + PHYS_OFFSET;
1200
1201	/*
1202	 * The first usable region must be PMD aligned. Mark its start
1203	 * as MEMBLOCK_NOMAP if it isn't
1204	 */
1205	for_each_mem_range(i, &block_start, &block_end) {
1206		if (!IS_ALIGNED(block_start, PMD_SIZE)) {
1207			phys_addr_t len;
1208
1209			len = round_up(block_start, PMD_SIZE) - block_start;
1210			memblock_mark_nomap(block_start, len);
1211		}
1212		break;
1213	}
1214
1215	for_each_mem_range(i, &block_start, &block_end) {
1216		if (block_start < vmalloc_limit) {
1217			if (block_end > lowmem_limit)
1218				/*
1219				 * Compare as u64 to ensure vmalloc_limit does
1220				 * not get truncated. block_end should always
1221				 * fit in phys_addr_t so there should be no
1222				 * issue with assignment.
1223				 */
1224				lowmem_limit = min_t(u64,
1225							 vmalloc_limit,
1226							 block_end);
1227
1228			/*
1229			 * Find the first non-pmd-aligned page, and point
1230			 * memblock_limit at it. This relies on rounding the
1231			 * limit down to be pmd-aligned, which happens at the
1232			 * end of this function.
1233			 *
1234			 * With this algorithm, the start or end of almost any
1235			 * bank can be non-pmd-aligned. The only exception is
1236			 * that the start of the bank 0 must be section-
1237			 * aligned, since otherwise memory would need to be
1238			 * allocated when mapping the start of bank 0, which
1239			 * occurs before any free memory is mapped.
1240			 */
1241			if (!memblock_limit) {
1242				if (!IS_ALIGNED(block_start, PMD_SIZE))
1243					memblock_limit = block_start;
1244				else if (!IS_ALIGNED(block_end, PMD_SIZE))
1245					memblock_limit = lowmem_limit;
1246			}
1247
1248		}
1249	}
1250
1251	arm_lowmem_limit = lowmem_limit;
1252
1253	high_memory = __va(arm_lowmem_limit - 1) + 1;
1254
1255	if (!memblock_limit)
1256		memblock_limit = arm_lowmem_limit;
1257
1258	/*
1259	 * Round the memblock limit down to a pmd size.  This
1260	 * helps to ensure that we will allocate memory from the
1261	 * last full pmd, which should be mapped.
1262	 */
1263	memblock_limit = round_down(memblock_limit, PMD_SIZE);
1264
1265	if (!IS_ENABLED(CONFIG_HIGHMEM) || cache_is_vipt_aliasing()) {
1266		if (memblock_end_of_DRAM() > arm_lowmem_limit) {
1267			phys_addr_t end = memblock_end_of_DRAM();
1268
1269			pr_notice("Ignoring RAM at %pa-%pa\n",
1270				  &memblock_limit, &end);
1271			pr_notice("Consider using a HIGHMEM enabled kernel.\n");
1272
1273			memblock_remove(memblock_limit, end - memblock_limit);
1274		}
1275	}
1276
1277	memblock_set_current_limit(memblock_limit);
1278}
1279
1280static __init void prepare_page_table(void)
1281{
1282	unsigned long addr;
1283	phys_addr_t end;
1284
1285	/*
1286	 * Clear out all the mappings below the kernel image.
1287	 */
1288#ifdef CONFIG_KASAN
1289	/*
1290	 * KASan's shadow memory inserts itself between the TASK_SIZE
1291	 * and MODULES_VADDR. Do not clear the KASan shadow memory mappings.
1292	 */
1293	for (addr = 0; addr < KASAN_SHADOW_START; addr += PMD_SIZE)
1294		pmd_clear(pmd_off_k(addr));
1295	/*
1296	 * Skip over the KASan shadow area. KASAN_SHADOW_END is sometimes
1297	 * equal to MODULES_VADDR and then we exit the pmd clearing. If we
1298	 * are using a thumb-compiled kernel, there there will be 8MB more
1299	 * to clear as KASan always offset to 16 MB below MODULES_VADDR.
1300	 */
1301	for (addr = KASAN_SHADOW_END; addr < MODULES_VADDR; addr += PMD_SIZE)
1302		pmd_clear(pmd_off_k(addr));
1303#else
1304	for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE)
1305		pmd_clear(pmd_off_k(addr));
1306#endif
1307
1308#ifdef CONFIG_XIP_KERNEL
1309	/* The XIP kernel is mapped in the module area -- skip over it */
1310	addr = ((unsigned long)_exiprom + PMD_SIZE - 1) & PMD_MASK;
1311#endif
1312	for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE)
1313		pmd_clear(pmd_off_k(addr));
1314
1315	/*
1316	 * Find the end of the first block of lowmem.
1317	 */
1318	end = memblock.memory.regions[0].base + memblock.memory.regions[0].size;
1319	if (end >= arm_lowmem_limit)
1320		end = arm_lowmem_limit;
1321
1322	/*
1323	 * Clear out all the kernel space mappings, except for the first
1324	 * memory bank, up to the vmalloc region.
1325	 */
1326	for (addr = __phys_to_virt(end);
1327	     addr < VMALLOC_START; addr += PMD_SIZE)
1328		pmd_clear(pmd_off_k(addr));
1329}
1330
1331#ifdef CONFIG_ARM_LPAE
1332/* the first page is reserved for pgd */
1333#define SWAPPER_PG_DIR_SIZE	(PAGE_SIZE + \
1334				 PTRS_PER_PGD * PTRS_PER_PMD * sizeof(pmd_t))
1335#else
1336#define SWAPPER_PG_DIR_SIZE	(PTRS_PER_PGD * sizeof(pgd_t))
1337#endif
1338
1339/*
1340 * Reserve the special regions of memory
1341 */
1342void __init arm_mm_memblock_reserve(void)
1343{
1344	/*
1345	 * Reserve the page tables.  These are already in use,
1346	 * and can only be in node 0.
1347	 */
1348	memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE);
1349
1350#ifdef CONFIG_SA1111
1351	/*
1352	 * Because of the SA1111 DMA bug, we want to preserve our
1353	 * precious DMA-able memory...
1354	 */
1355	memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
1356#endif
1357}
1358
1359/*
1360 * Set up the device mappings.  Since we clear out the page tables for all
1361 * mappings above VMALLOC_START, except early fixmap, we might remove debug
1362 * device mappings.  This means earlycon can be used to debug this function
1363 * Any other function or debugging method which may touch any device _will_
1364 * crash the kernel.
1365 */
1366static void __init devicemaps_init(const struct machine_desc *mdesc)
1367{
1368	struct map_desc map;
1369	unsigned long addr;
1370	void *vectors;
1371
1372	/*
1373	 * Allocate the vector page early.
1374	 */
1375	vectors = early_alloc(PAGE_SIZE * 2);
1376
1377	early_trap_init(vectors);
1378
1379	/*
1380	 * Clear page table except top pmd used by early fixmaps
1381	 */
1382	for (addr = VMALLOC_START; addr < (FIXADDR_TOP & PMD_MASK); addr += PMD_SIZE)
1383		pmd_clear(pmd_off_k(addr));
1384
1385	if (__atags_pointer) {
1386		/* create a read-only mapping of the device tree */
1387		map.pfn = __phys_to_pfn(__atags_pointer & SECTION_MASK);
1388		map.virtual = FDT_FIXED_BASE;
1389		map.length = FDT_FIXED_SIZE;
1390		map.type = MT_MEMORY_RO;
1391		create_mapping(&map);
1392	}
1393
1394	/*
1395	 * Map the cache flushing regions.
1396	 */
1397#ifdef FLUSH_BASE
1398	map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
1399	map.virtual = FLUSH_BASE;
1400	map.length = SZ_1M;
1401	map.type = MT_CACHECLEAN;
1402	create_mapping(&map);
1403#endif
1404#ifdef FLUSH_BASE_MINICACHE
1405	map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
1406	map.virtual = FLUSH_BASE_MINICACHE;
1407	map.length = SZ_1M;
1408	map.type = MT_MINICLEAN;
1409	create_mapping(&map);
1410#endif
1411
1412	/*
1413	 * Create a mapping for the machine vectors at the high-vectors
1414	 * location (0xffff0000).  If we aren't using high-vectors, also
1415	 * create a mapping at the low-vectors virtual address.
1416	 */
1417	map.pfn = __phys_to_pfn(virt_to_phys(vectors));
1418	map.virtual = 0xffff0000;
1419	map.length = PAGE_SIZE;
1420#ifdef CONFIG_KUSER_HELPERS
1421	map.type = MT_HIGH_VECTORS;
1422#else
1423	map.type = MT_LOW_VECTORS;
1424#endif
1425	create_mapping(&map);
1426
1427	if (!vectors_high()) {
1428		map.virtual = 0;
1429		map.length = PAGE_SIZE * 2;
1430		map.type = MT_LOW_VECTORS;
1431		create_mapping(&map);
1432	}
1433
1434	/* Now create a kernel read-only mapping */
1435	map.pfn += 1;
1436	map.virtual = 0xffff0000 + PAGE_SIZE;
1437	map.length = PAGE_SIZE;
1438	map.type = MT_LOW_VECTORS;
1439	create_mapping(&map);
1440
1441	/*
1442	 * Ask the machine support to map in the statically mapped devices.
1443	 */
1444	if (mdesc->map_io)
1445		mdesc->map_io();
1446	else
1447		debug_ll_io_init();
1448	fill_pmd_gaps();
1449
1450	/* Reserve fixed i/o space in VMALLOC region */
1451	pci_reserve_io();
1452
1453	/*
1454	 * Finally flush the caches and tlb to ensure that we're in a
1455	 * consistent state wrt the writebuffer.  This also ensures that
1456	 * any write-allocated cache lines in the vector page are written
1457	 * back.  After this point, we can start to touch devices again.
1458	 */
1459	local_flush_tlb_all();
1460	flush_cache_all();
1461
1462	/* Enable asynchronous aborts */
1463	early_abt_enable();
1464}
1465
1466static void __init kmap_init(void)
1467{
1468#ifdef CONFIG_HIGHMEM
1469	pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE),
1470		PKMAP_BASE, _PAGE_KERNEL_TABLE);
1471#endif
1472
1473	early_pte_alloc(pmd_off_k(FIXADDR_START), FIXADDR_START,
1474			_PAGE_KERNEL_TABLE);
1475}
1476
1477static void __init map_lowmem(void)
1478{
1479	phys_addr_t start, end;
1480	u64 i;
1481
1482	/* Map all the lowmem memory banks. */
1483	for_each_mem_range(i, &start, &end) {
1484		struct map_desc map;
1485
1486		pr_debug("map lowmem start: 0x%08llx, end: 0x%08llx\n",
1487			 (long long)start, (long long)end);
1488		if (end > arm_lowmem_limit)
1489			end = arm_lowmem_limit;
1490		if (start >= end)
1491			break;
1492
1493		/*
1494		 * If our kernel image is in the VMALLOC area we need to remove
1495		 * the kernel physical memory from lowmem since the kernel will
1496		 * be mapped separately.
1497		 *
1498		 * The kernel will typically be at the very start of lowmem,
1499		 * but any placement relative to memory ranges is possible.
1500		 *
1501		 * If the memblock contains the kernel, we have to chisel out
1502		 * the kernel memory from it and map each part separately. We
1503		 * get 6 different theoretical cases:
1504		 *
1505		 *                            +--------+ +--------+
1506		 *  +-- start --+  +--------+ | Kernel | | Kernel |
1507		 *  |           |  | Kernel | | case 2 | | case 5 |
1508		 *  |           |  | case 1 | +--------+ |        | +--------+
1509		 *  |  Memory   |  +--------+            |        | | Kernel |
1510		 *  |  range    |  +--------+            |        | | case 6 |
1511		 *  |           |  | Kernel | +--------+ |        | +--------+
1512		 *  |           |  | case 3 | | Kernel | |        |
1513		 *  +-- end ----+  +--------+ | case 4 | |        |
1514		 *                            +--------+ +--------+
1515		 */
1516
1517		/* Case 5: kernel covers range, don't map anything, should be rare */
1518		if ((start > kernel_sec_start) && (end < kernel_sec_end))
1519			break;
1520
1521		/* Cases where the kernel is starting inside the range */
1522		if ((kernel_sec_start >= start) && (kernel_sec_start <= end)) {
1523			/* Case 6: kernel is embedded in the range, we need two mappings */
1524			if ((start < kernel_sec_start) && (end > kernel_sec_end)) {
1525				/* Map memory below the kernel */
1526				map.pfn = __phys_to_pfn(start);
1527				map.virtual = __phys_to_virt(start);
1528				map.length = kernel_sec_start - start;
1529				map.type = MT_MEMORY_RW;
1530				create_mapping(&map);
1531				/* Map memory above the kernel */
1532				map.pfn = __phys_to_pfn(kernel_sec_end);
1533				map.virtual = __phys_to_virt(kernel_sec_end);
1534				map.length = end - kernel_sec_end;
1535				map.type = MT_MEMORY_RW;
1536				create_mapping(&map);
1537				break;
1538			}
1539			/* Case 1: kernel and range start at the same address, should be common */
1540			if (kernel_sec_start == start)
1541				start = kernel_sec_end;
1542			/* Case 3: kernel and range end at the same address, should be rare */
1543			if (kernel_sec_end == end)
1544				end = kernel_sec_start;
1545		} else if ((kernel_sec_start < start) && (kernel_sec_end > start) && (kernel_sec_end < end)) {
1546			/* Case 2: kernel ends inside range, starts below it */
1547			start = kernel_sec_end;
1548		} else if ((kernel_sec_start > start) && (kernel_sec_start < end) && (kernel_sec_end > end)) {
1549			/* Case 4: kernel starts inside range, ends above it */
1550			end = kernel_sec_start;
1551		}
1552		map.pfn = __phys_to_pfn(start);
1553		map.virtual = __phys_to_virt(start);
1554		map.length = end - start;
1555		map.type = MT_MEMORY_RW;
1556		create_mapping(&map);
1557	}
1558}
1559
1560static void __init map_kernel(void)
1561{
1562	/*
1563	 * We use the well known kernel section start and end and split the area in the
1564	 * middle like this:
1565	 *  .                .
1566	 *  | RW memory      |
1567	 *  +----------------+ kernel_x_start
1568	 *  | Executable     |
1569	 *  | kernel memory  |
1570	 *  +----------------+ kernel_x_end / kernel_nx_start
1571	 *  | Non-executable |
1572	 *  | kernel memory  |
1573	 *  +----------------+ kernel_nx_end
1574	 *  | RW memory      |
1575	 *  .                .
1576	 *
1577	 * Notice that we are dealing with section sized mappings here so all of this
1578	 * will be bumped to the closest section boundary. This means that some of the
1579	 * non-executable part of the kernel memory is actually mapped as executable.
1580	 * This will only persist until we turn on proper memory management later on
1581	 * and we remap the whole kernel with page granularity.
1582	 */
1583#ifdef CONFIG_XIP_KERNEL
1584	phys_addr_t kernel_nx_start = kernel_sec_start;
1585#else
1586	phys_addr_t kernel_x_start = kernel_sec_start;
1587	phys_addr_t kernel_x_end = round_up(__pa(__init_end), SECTION_SIZE);
1588	phys_addr_t kernel_nx_start = kernel_x_end;
1589#endif
1590	phys_addr_t kernel_nx_end = kernel_sec_end;
1591	struct map_desc map;
1592
1593	/*
1594	 * Map the kernel if it is XIP.
1595	 * It is always first in the modulearea.
1596	 */
1597#ifdef CONFIG_XIP_KERNEL
1598	map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
1599	map.virtual = MODULES_VADDR;
1600	map.length = ((unsigned long)_exiprom - map.virtual + ~SECTION_MASK) & SECTION_MASK;
1601	map.type = MT_ROM;
1602	create_mapping(&map);
1603#else
1604	map.pfn = __phys_to_pfn(kernel_x_start);
1605	map.virtual = __phys_to_virt(kernel_x_start);
1606	map.length = kernel_x_end - kernel_x_start;
1607	map.type = MT_MEMORY_RWX;
1608	create_mapping(&map);
1609
1610	/* If the nx part is small it may end up covered by the tail of the RWX section */
1611	if (kernel_x_end == kernel_nx_end)
1612		return;
1613#endif
1614	map.pfn = __phys_to_pfn(kernel_nx_start);
1615	map.virtual = __phys_to_virt(kernel_nx_start);
1616	map.length = kernel_nx_end - kernel_nx_start;
1617	map.type = MT_MEMORY_RW;
1618	create_mapping(&map);
1619}
1620
1621#ifdef CONFIG_ARM_PV_FIXUP
1622typedef void pgtables_remap(long long offset, unsigned long pgd);
1623pgtables_remap lpae_pgtables_remap_asm;
1624
1625/*
1626 * early_paging_init() recreates boot time page table setup, allowing machines
1627 * to switch over to a high (>4G) address space on LPAE systems
1628 */
1629static void __init early_paging_init(const struct machine_desc *mdesc)
1630{
1631	pgtables_remap *lpae_pgtables_remap;
1632	unsigned long pa_pgd;
1633	u32 cr, ttbcr, tmp;
1634	long long offset;
1635
1636	if (!mdesc->pv_fixup)
1637		return;
1638
1639	offset = mdesc->pv_fixup();
1640	if (offset == 0)
1641		return;
1642
1643	/*
1644	 * Offset the kernel section physical offsets so that the kernel
1645	 * mapping will work out later on.
1646	 */
1647	kernel_sec_start += offset;
1648	kernel_sec_end += offset;
1649
1650	/*
1651	 * Get the address of the remap function in the 1:1 identity
1652	 * mapping setup by the early page table assembly code.  We
1653	 * must get this prior to the pv update.  The following barrier
1654	 * ensures that this is complete before we fixup any P:V offsets.
1655	 */
1656	lpae_pgtables_remap = (pgtables_remap *)(unsigned long)__pa(lpae_pgtables_remap_asm);
1657	pa_pgd = __pa(swapper_pg_dir);
1658	barrier();
1659
1660	pr_info("Switching physical address space to 0x%08llx\n",
1661		(u64)PHYS_OFFSET + offset);
1662
1663	/* Re-set the phys pfn offset, and the pv offset */
1664	__pv_offset += offset;
1665	__pv_phys_pfn_offset += PFN_DOWN(offset);
1666
1667	/* Run the patch stub to update the constants */
1668	fixup_pv_table(&__pv_table_begin,
1669		(&__pv_table_end - &__pv_table_begin) << 2);
1670
1671	/*
1672	 * We changing not only the virtual to physical mapping, but also
1673	 * the physical addresses used to access memory.  We need to flush
1674	 * all levels of cache in the system with caching disabled to
1675	 * ensure that all data is written back, and nothing is prefetched
1676	 * into the caches.  We also need to prevent the TLB walkers
1677	 * allocating into the caches too.  Note that this is ARMv7 LPAE
1678	 * specific.
1679	 */
1680	cr = get_cr();
1681	set_cr(cr & ~(CR_I | CR_C));
1682	ttbcr = cpu_get_ttbcr();
1683	/* Disable all kind of caching of the translation table */
1684	tmp = ttbcr & ~(TTBCR_ORGN0_MASK | TTBCR_IRGN0_MASK);
1685	cpu_set_ttbcr(tmp);
1686	flush_cache_all();
1687
1688	/*
1689	 * Fixup the page tables - this must be in the idmap region as
1690	 * we need to disable the MMU to do this safely, and hence it
1691	 * needs to be assembly.  It's fairly simple, as we're using the
1692	 * temporary tables setup by the initial assembly code.
1693	 */
1694	lpae_pgtables_remap(offset, pa_pgd);
1695
1696	/* Re-enable the caches and cacheable TLB walks */
1697	cpu_set_ttbcr(ttbcr);
1698	set_cr(cr);
1699}
1700
1701#else
1702
1703static void __init early_paging_init(const struct machine_desc *mdesc)
1704{
1705	long long offset;
1706
1707	if (!mdesc->pv_fixup)
1708		return;
1709
1710	offset = mdesc->pv_fixup();
1711	if (offset == 0)
1712		return;
1713
1714	pr_crit("Physical address space modification is only to support Keystone2.\n");
1715	pr_crit("Please enable ARM_LPAE and ARM_PATCH_PHYS_VIRT support to use this\n");
1716	pr_crit("feature. Your kernel may crash now, have a good day.\n");
1717	add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
1718}
1719
1720#endif
1721
1722static void __init early_fixmap_shutdown(void)
1723{
1724	int i;
1725	unsigned long va = fix_to_virt(__end_of_permanent_fixed_addresses - 1);
1726
1727	pte_offset_fixmap = pte_offset_late_fixmap;
1728	pmd_clear(fixmap_pmd(va));
1729	local_flush_tlb_kernel_page(va);
1730
1731	for (i = 0; i < __end_of_permanent_fixed_addresses; i++) {
1732		pte_t *pte;
1733		struct map_desc map;
1734
1735		map.virtual = fix_to_virt(i);
1736		pte = pte_offset_early_fixmap(pmd_off_k(map.virtual), map.virtual);
1737
1738		/* Only i/o device mappings are supported ATM */
1739		if (pte_none(*pte) ||
1740		    (pte_val(*pte) & L_PTE_MT_MASK) != L_PTE_MT_DEV_SHARED)
1741			continue;
1742
1743		map.pfn = pte_pfn(*pte);
1744		map.type = MT_DEVICE;
1745		map.length = PAGE_SIZE;
1746
1747		create_mapping(&map);
1748	}
1749}
1750
1751/*
1752 * paging_init() sets up the page tables, initialises the zone memory
1753 * maps, and sets up the zero page, bad page and bad page tables.
1754 */
1755void __init paging_init(const struct machine_desc *mdesc)
1756{
1757	void *zero_page;
1758
1759#ifdef CONFIG_XIP_KERNEL
1760	/* Store the kernel RW RAM region start/end in these variables */
1761	kernel_sec_start = CONFIG_PHYS_OFFSET & SECTION_MASK;
1762	kernel_sec_end = round_up(__pa(_end), SECTION_SIZE);
1763#endif
1764	pr_debug("physical kernel sections: 0x%08llx-0x%08llx\n",
1765		 kernel_sec_start, kernel_sec_end);
1766
1767	prepare_page_table();
1768	map_lowmem();
1769	memblock_set_current_limit(arm_lowmem_limit);
1770	pr_debug("lowmem limit is %08llx\n", (long long)arm_lowmem_limit);
1771	/*
1772	 * After this point early_alloc(), i.e. the memblock allocator, can
1773	 * be used
1774	 */
1775	map_kernel();
1776	dma_contiguous_remap();
1777	early_fixmap_shutdown();
1778	devicemaps_init(mdesc);
1779	kmap_init();
1780	tcm_init();
1781
1782	top_pmd = pmd_off_k(0xffff0000);
1783
1784	/* allocate the zero page. */
1785	zero_page = early_alloc(PAGE_SIZE);
1786
1787	bootmem_init();
1788
1789	empty_zero_page = virt_to_page(zero_page);
1790	__flush_dcache_folio(NULL, page_folio(empty_zero_page));
1791}
1792
1793void __init early_mm_init(const struct machine_desc *mdesc)
1794{
1795	build_mem_type_table();
1796	early_paging_init(mdesc);
1797}
1798
1799void set_ptes(struct mm_struct *mm, unsigned long addr,
1800			      pte_t *ptep, pte_t pteval, unsigned int nr)
1801{
1802	unsigned long ext = 0;
1803
1804	if (addr < TASK_SIZE && pte_valid_user(pteval)) {
1805		if (!pte_special(pteval))
1806			__sync_icache_dcache(pteval);
1807		ext |= PTE_EXT_NG;
1808	}
1809
1810	for (;;) {
1811		set_pte_ext(ptep, pteval, ext);
1812		if (--nr == 0)
1813			break;
1814		ptep++;
1815		pteval = pte_next_pfn(pteval);
1816	}
1817}