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alignment.c
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linux-6.19.14/arch/arm/mm/alignment.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * linux/arch/arm/mm/alignment.c 4 * 5 * Copyright (C) 1995 Linus Torvalds 6 * Modifications for ARM processor (c) 1995-2001 Russell King 7 * Thumb alignment fault fixups (c) 2004 MontaVista Software, Inc. 8 * - Adapted from gdb/sim/arm/thumbemu.c -- Thumb instruction emulation. 9 * Copyright (C) 1996, Cygnus Software Technologies Ltd. 10 */ 11#include <linux/moduleparam.h> 12#include <linux/compiler.h> 13#include <linux/kernel.h> 14#include <linux/sched/debug.h> 15#include <linux/errno.h> 16#include <linux/string.h> 17#include <linux/proc_fs.h> 18#include <linux/seq_file.h> 19#include <linux/init.h> 20#include <linux/sched/signal.h> 21#include <linux/uaccess.h> 22#include <linux/unaligned.h> 23 24#include <asm/cp15.h> 25#include <asm/system_info.h> 26#include <asm/system_misc.h> 27#include <asm/opcodes.h> 28 29#include "fault.h" 30#include "mm.h" 31 32/* 33 * 32-bit misaligned trap handler (c) 1998 San Mehat (CCC) -July 1998 34 * /proc/sys/debug/alignment, modified and integrated into 35 * Linux 2.1 by Russell King 36 * 37 * Speed optimisations and better fault handling by Russell King. 38 * 39 * *** NOTE *** 40 * This code is not portable to processors with late data abort handling. 41 */ 42#define CODING_BITS(i) (i & 0x0e000000) 43#define COND_BITS(i) (i & 0xf0000000) 44 45#define LDST_I_BIT(i) (i & (1 << 26)) /* Immediate constant */ 46#define LDST_P_BIT(i) (i & (1 << 24)) /* Preindex */ 47#define LDST_U_BIT(i) (i & (1 << 23)) /* Add offset */ 48#define LDST_W_BIT(i) (i & (1 << 21)) /* Writeback */ 49#define LDST_L_BIT(i) (i & (1 << 20)) /* Load */ 50 51#define LDST_P_EQ_U(i) ((((i) ^ ((i) >> 1)) & (1 << 23)) == 0) 52 53#define LDSTHD_I_BIT(i) (i & (1 << 22)) /* double/half-word immed */ 54#define LDM_S_BIT(i) (i & (1 << 22)) /* write CPSR from SPSR */ 55 56#define RN_BITS(i) ((i >> 16) & 15) /* Rn */ 57#define RD_BITS(i) ((i >> 12) & 15) /* Rd */ 58#define RM_BITS(i) (i & 15) /* Rm */ 59 60#define REGMASK_BITS(i) (i & 0xffff) 61#define OFFSET_BITS(i) (i & 0x0fff) 62 63#define IS_SHIFT(i) (i & 0x0ff0) 64#define SHIFT_BITS(i) ((i >> 7) & 0x1f) 65#define SHIFT_TYPE(i) (i & 0x60) 66#define SHIFT_LSL 0x00 67#define SHIFT_LSR 0x20 68#define SHIFT_ASR 0x40 69#define SHIFT_RORRRX 0x60 70 71#define BAD_INSTR 0xdeadc0de 72 73/* Thumb-2 32 bit format per ARMv7 DDI0406A A6.3, either f800h,e800h,f800h */ 74#define IS_T32(hi16) \ 75 (((hi16) & 0xe000) == 0xe000 && ((hi16) & 0x1800)) 76 77static unsigned long ai_user; 78static unsigned long ai_sys; 79static void *ai_sys_last_pc; 80static unsigned long ai_skipped; 81static unsigned long ai_half; 82static unsigned long ai_word; 83static unsigned long ai_dword; 84static unsigned long ai_multi; 85static int ai_usermode; 86static unsigned long cr_no_alignment; 87 88core_param(alignment, ai_usermode, int, 0600); 89 90#define UM_WARN (1 << 0) 91#define UM_FIXUP (1 << 1) 92#define UM_SIGNAL (1 << 2) 93 94/* Return true if and only if the ARMv6 unaligned access model is in use. */ 95static bool cpu_is_v6_unaligned(void) 96{ 97 return cpu_architecture() >= CPU_ARCH_ARMv6 && get_cr() & CR_U; 98} 99 100static int safe_usermode(int new_usermode, bool warn) 101{ 102 /* 103 * ARMv6 and later CPUs can perform unaligned accesses for 104 * most single load and store instructions up to word size. 105 * LDM, STM, LDRD and STRD still need to be handled. 106 * 107 * Ignoring the alignment fault is not an option on these 108 * CPUs since we spin re-faulting the instruction without 109 * making any progress. 110 */ 111 if (cpu_is_v6_unaligned() && !(new_usermode & (UM_FIXUP | UM_SIGNAL))) { 112 new_usermode |= UM_FIXUP; 113 114 if (warn) 115 pr_warn("alignment: ignoring faults is unsafe on this CPU. Defaulting to fixup mode.\n"); 116 } 117 118 return new_usermode; 119} 120 121#ifdef CONFIG_PROC_FS 122static const char *usermode_action[] = { 123 "ignored", 124 "warn", 125 "fixup", 126 "fixup+warn", 127 "signal", 128 "signal+warn" 129}; 130 131static int alignment_proc_show(struct seq_file *m, void *v) 132{ 133 seq_printf(m, "User:\t\t%lu\n", ai_user); 134 seq_printf(m, "System:\t\t%lu (%pS)\n", ai_sys, ai_sys_last_pc); 135 seq_printf(m, "Skipped:\t%lu\n", ai_skipped); 136 seq_printf(m, "Half:\t\t%lu\n", ai_half); 137 seq_printf(m, "Word:\t\t%lu\n", ai_word); 138 if (cpu_architecture() >= CPU_ARCH_ARMv5TE) 139 seq_printf(m, "DWord:\t\t%lu\n", ai_dword); 140 seq_printf(m, "Multi:\t\t%lu\n", ai_multi); 141 seq_printf(m, "User faults:\t%i (%s)\n", ai_usermode, 142 usermode_action[ai_usermode]); 143 144 return 0; 145} 146 147static int alignment_proc_open(struct inode *inode, struct file *file) 148{ 149 return single_open(file, alignment_proc_show, NULL); 150} 151 152static ssize_t alignment_proc_write(struct file *file, const char __user *buffer, 153 size_t count, loff_t *pos) 154{ 155 char mode; 156 157 if (count > 0) { 158 if (get_user(mode, buffer)) 159 return -EFAULT; 160 if (mode >= '0' && mode <= '5') 161 ai_usermode = safe_usermode(mode - '0', true); 162 } 163 return count; 164} 165 166static const struct proc_ops alignment_proc_ops = { 167 .proc_open = alignment_proc_open, 168 .proc_read = seq_read, 169 .proc_lseek = seq_lseek, 170 .proc_release = single_release, 171 .proc_write = alignment_proc_write, 172}; 173#endif /* CONFIG_PROC_FS */ 174 175union offset_union { 176 unsigned long un; 177 signed long sn; 178}; 179 180#define TYPE_ERROR 0 181#define TYPE_FAULT 1 182#define TYPE_LDST 2 183#define TYPE_DONE 3 184 185#ifdef __ARMEB__ 186#define BE 1 187#define FIRST_BYTE_16 "mov %1, %1, ror #8\n" 188#define FIRST_BYTE_32 "mov %1, %1, ror #24\n" 189#define NEXT_BYTE "ror #24" 190#else 191#define BE 0 192#define FIRST_BYTE_16 193#define FIRST_BYTE_32 194#define NEXT_BYTE "lsr #8" 195#endif 196 197#define __get8_unaligned_check(ins,val,addr,err) \ 198 __asm__( \ 199 ARM( "1: "ins" %1, [%2], #1\n" ) \ 200 THUMB( "1: "ins" %1, [%2]\n" ) \ 201 THUMB( " add %2, %2, #1\n" ) \ 202 "2:\n" \ 203 " .pushsection .text.fixup,\"ax\"\n" \ 204 " .align 2\n" \ 205 "3: mov %0, #1\n" \ 206 " b 2b\n" \ 207 " .popsection\n" \ 208 " .pushsection __ex_table,\"a\"\n" \ 209 " .align 3\n" \ 210 " .long 1b, 3b\n" \ 211 " .popsection\n" \ 212 : "=r" (err), "=&r" (val), "=r" (addr) \ 213 : "0" (err), "2" (addr)) 214 215#define __get16_unaligned_check(ins,val,addr) \ 216 do { \ 217 unsigned int err = 0, v, a = addr; \ 218 __get8_unaligned_check(ins,v,a,err); \ 219 val = v << ((BE) ? 8 : 0); \ 220 __get8_unaligned_check(ins,v,a,err); \ 221 val |= v << ((BE) ? 0 : 8); \ 222 if (err) \ 223 goto fault; \ 224 } while (0) 225 226#define get16_unaligned_check(val,addr) \ 227 __get16_unaligned_check("ldrb",val,addr) 228 229#define get16t_unaligned_check(val,addr) \ 230 __get16_unaligned_check("ldrbt",val,addr) 231 232#define __get32_unaligned_check(ins,val,addr) \ 233 do { \ 234 unsigned int err = 0, v, a = addr; \ 235 __get8_unaligned_check(ins,v,a,err); \ 236 val = v << ((BE) ? 24 : 0); \ 237 __get8_unaligned_check(ins,v,a,err); \ 238 val |= v << ((BE) ? 16 : 8); \ 239 __get8_unaligned_check(ins,v,a,err); \ 240 val |= v << ((BE) ? 8 : 16); \ 241 __get8_unaligned_check(ins,v,a,err); \ 242 val |= v << ((BE) ? 0 : 24); \ 243 if (err) \ 244 goto fault; \ 245 } while (0) 246 247#define get32_unaligned_check(val,addr) \ 248 __get32_unaligned_check("ldrb",val,addr) 249 250#define get32t_unaligned_check(val,addr) \ 251 __get32_unaligned_check("ldrbt",val,addr) 252 253#define __put16_unaligned_check(ins,val,addr) \ 254 do { \ 255 unsigned int err = 0, v = val, a = addr; \ 256 __asm__( FIRST_BYTE_16 \ 257 ARM( "1: "ins" %1, [%2], #1\n" ) \ 258 THUMB( "1: "ins" %1, [%2]\n" ) \ 259 THUMB( " add %2, %2, #1\n" ) \ 260 " mov %1, %1, "NEXT_BYTE"\n" \ 261 "2: "ins" %1, [%2]\n" \ 262 "3:\n" \ 263 " .pushsection .text.fixup,\"ax\"\n" \ 264 " .align 2\n" \ 265 "4: mov %0, #1\n" \ 266 " b 3b\n" \ 267 " .popsection\n" \ 268 " .pushsection __ex_table,\"a\"\n" \ 269 " .align 3\n" \ 270 " .long 1b, 4b\n" \ 271 " .long 2b, 4b\n" \ 272 " .popsection\n" \ 273 : "=r" (err), "=&r" (v), "=&r" (a) \ 274 : "0" (err), "1" (v), "2" (a)); \ 275 if (err) \ 276 goto fault; \ 277 } while (0) 278 279#define put16_unaligned_check(val,addr) \ 280 __put16_unaligned_check("strb",val,addr) 281 282#define put16t_unaligned_check(val,addr) \ 283 __put16_unaligned_check("strbt",val,addr) 284 285#define __put32_unaligned_check(ins,val,addr) \ 286 do { \ 287 unsigned int err = 0, v = val, a = addr; \ 288 __asm__( FIRST_BYTE_32 \ 289 ARM( "1: "ins" %1, [%2], #1\n" ) \ 290 THUMB( "1: "ins" %1, [%2]\n" ) \ 291 THUMB( " add %2, %2, #1\n" ) \ 292 " mov %1, %1, "NEXT_BYTE"\n" \ 293 ARM( "2: "ins" %1, [%2], #1\n" ) \ 294 THUMB( "2: "ins" %1, [%2]\n" ) \ 295 THUMB( " add %2, %2, #1\n" ) \ 296 " mov %1, %1, "NEXT_BYTE"\n" \ 297 ARM( "3: "ins" %1, [%2], #1\n" ) \ 298 THUMB( "3: "ins" %1, [%2]\n" ) \ 299 THUMB( " add %2, %2, #1\n" ) \ 300 " mov %1, %1, "NEXT_BYTE"\n" \ 301 "4: "ins" %1, [%2]\n" \ 302 "5:\n" \ 303 " .pushsection .text.fixup,\"ax\"\n" \ 304 " .align 2\n" \ 305 "6: mov %0, #1\n" \ 306 " b 5b\n" \ 307 " .popsection\n" \ 308 " .pushsection __ex_table,\"a\"\n" \ 309 " .align 3\n" \ 310 " .long 1b, 6b\n" \ 311 " .long 2b, 6b\n" \ 312 " .long 3b, 6b\n" \ 313 " .long 4b, 6b\n" \ 314 " .popsection\n" \ 315 : "=r" (err), "=&r" (v), "=&r" (a) \ 316 : "0" (err), "1" (v), "2" (a)); \ 317 if (err) \ 318 goto fault; \ 319 } while (0) 320 321#define put32_unaligned_check(val,addr) \ 322 __put32_unaligned_check("strb", val, addr) 323 324#define put32t_unaligned_check(val,addr) \ 325 __put32_unaligned_check("strbt", val, addr) 326 327static void 328do_alignment_finish_ldst(unsigned long addr, u32 instr, struct pt_regs *regs, union offset_union offset) 329{ 330 if (!LDST_U_BIT(instr)) 331 offset.un = -offset.un; 332 333 if (!LDST_P_BIT(instr)) 334 addr += offset.un; 335 336 if (!LDST_P_BIT(instr) || LDST_W_BIT(instr)) 337 regs->uregs[RN_BITS(instr)] = addr; 338} 339 340static int 341do_alignment_ldrhstrh(unsigned long addr, u32 instr, struct pt_regs *regs) 342{ 343 unsigned int rd = RD_BITS(instr); 344 345 ai_half += 1; 346 347 if (user_mode(regs)) 348 goto user; 349 350 if (LDST_L_BIT(instr)) { 351 unsigned long val; 352 get16_unaligned_check(val, addr); 353 354 /* signed half-word? */ 355 if (instr & 0x40) 356 val = (signed long)((signed short) val); 357 358 regs->uregs[rd] = val; 359 } else 360 put16_unaligned_check(regs->uregs[rd], addr); 361 362 return TYPE_LDST; 363 364 user: 365 if (LDST_L_BIT(instr)) { 366 unsigned long val; 367 unsigned int __ua_flags = uaccess_save_and_enable(); 368 369 get16t_unaligned_check(val, addr); 370 uaccess_restore(__ua_flags); 371 372 /* signed half-word? */ 373 if (instr & 0x40) 374 val = (signed long)((signed short) val); 375 376 regs->uregs[rd] = val; 377 } else { 378 unsigned int __ua_flags = uaccess_save_and_enable(); 379 put16t_unaligned_check(regs->uregs[rd], addr); 380 uaccess_restore(__ua_flags); 381 } 382 383 return TYPE_LDST; 384 385 fault: 386 return TYPE_FAULT; 387} 388 389static int 390do_alignment_ldrdstrd(unsigned long addr, u32 instr, struct pt_regs *regs) 391{ 392 unsigned int rd = RD_BITS(instr); 393 unsigned int rd2; 394 int load; 395 396 if ((instr & 0xfe000000) == 0xe8000000) { 397 /* ARMv7 Thumb-2 32-bit LDRD/STRD */ 398 rd2 = (instr >> 8) & 0xf; 399 load = !!(LDST_L_BIT(instr)); 400 } else if (((rd & 1) == 1) || (rd == 14)) 401 goto bad; 402 else { 403 load = ((instr & 0xf0) == 0xd0); 404 rd2 = rd + 1; 405 } 406 407 ai_dword += 1; 408 409 if (user_mode(regs)) 410 goto user; 411 412 if (load) { 413 unsigned long val; 414 get32_unaligned_check(val, addr); 415 regs->uregs[rd] = val; 416 get32_unaligned_check(val, addr + 4); 417 regs->uregs[rd2] = val; 418 } else { 419 put32_unaligned_check(regs->uregs[rd], addr); 420 put32_unaligned_check(regs->uregs[rd2], addr + 4); 421 } 422 423 return TYPE_LDST; 424 425 user: 426 if (load) { 427 unsigned long val, val2; 428 unsigned int __ua_flags = uaccess_save_and_enable(); 429 430 get32t_unaligned_check(val, addr); 431 get32t_unaligned_check(val2, addr + 4); 432 433 uaccess_restore(__ua_flags); 434 435 regs->uregs[rd] = val; 436 regs->uregs[rd2] = val2; 437 } else { 438 unsigned int __ua_flags = uaccess_save_and_enable(); 439 put32t_unaligned_check(regs->uregs[rd], addr); 440 put32t_unaligned_check(regs->uregs[rd2], addr + 4); 441 uaccess_restore(__ua_flags); 442 } 443 444 return TYPE_LDST; 445 bad: 446 return TYPE_ERROR; 447 fault: 448 return TYPE_FAULT; 449} 450 451static int 452do_alignment_ldrstr(unsigned long addr, u32 instr, struct pt_regs *regs) 453{ 454 unsigned int rd = RD_BITS(instr); 455 456 ai_word += 1; 457 458 if ((!LDST_P_BIT(instr) && LDST_W_BIT(instr)) || user_mode(regs)) 459 goto trans; 460 461 if (LDST_L_BIT(instr)) { 462 unsigned int val; 463 get32_unaligned_check(val, addr); 464 regs->uregs[rd] = val; 465 } else 466 put32_unaligned_check(regs->uregs[rd], addr); 467 return TYPE_LDST; 468 469 trans: 470 if (LDST_L_BIT(instr)) { 471 unsigned int val; 472 unsigned int __ua_flags = uaccess_save_and_enable(); 473 get32t_unaligned_check(val, addr); 474 uaccess_restore(__ua_flags); 475 regs->uregs[rd] = val; 476 } else { 477 unsigned int __ua_flags = uaccess_save_and_enable(); 478 put32t_unaligned_check(regs->uregs[rd], addr); 479 uaccess_restore(__ua_flags); 480 } 481 return TYPE_LDST; 482 483 fault: 484 return TYPE_FAULT; 485} 486 487/* 488 * LDM/STM alignment handler. 489 * 490 * There are 4 variants of this instruction: 491 * 492 * B = rn pointer before instruction, A = rn pointer after instruction 493 * ------ increasing address -----> 494 * | | r0 | r1 | ... | rx | | 495 * PU = 01 B A 496 * PU = 11 B A 497 * PU = 00 A B 498 * PU = 10 A B 499 */ 500static int 501do_alignment_ldmstm(unsigned long addr, u32 instr, struct pt_regs *regs) 502{ 503 unsigned int rd, rn, correction, nr_regs, regbits; 504 unsigned long eaddr, newaddr; 505 506 if (LDM_S_BIT(instr)) 507 goto bad; 508 509 correction = 4; /* processor implementation defined */ 510 regs->ARM_pc += correction; 511 512 ai_multi += 1; 513 514 /* count the number of registers in the mask to be transferred */ 515 nr_regs = hweight16(REGMASK_BITS(instr)) * 4; 516 517 rn = RN_BITS(instr); 518 newaddr = eaddr = regs->uregs[rn]; 519 520 if (!LDST_U_BIT(instr)) 521 nr_regs = -nr_regs; 522 newaddr += nr_regs; 523 if (!LDST_U_BIT(instr)) 524 eaddr = newaddr; 525 526 if (LDST_P_EQ_U(instr)) /* U = P */ 527 eaddr += 4; 528 529 /* 530 * For alignment faults on the ARM922T/ARM920T the MMU makes 531 * the FSR (and hence addr) equal to the updated base address 532 * of the multiple access rather than the restored value. 533 * Switch this message off if we've got a ARM92[02], otherwise 534 * [ls]dm alignment faults are noisy! 535 */ 536#if !(defined CONFIG_CPU_ARM922T) && !(defined CONFIG_CPU_ARM920T) 537 /* 538 * This is a "hint" - we already have eaddr worked out by the 539 * processor for us. 540 */ 541 if (addr != eaddr) { 542 pr_err("LDMSTM: PC = %08lx, instr = %08x, " 543 "addr = %08lx, eaddr = %08lx\n", 544 instruction_pointer(regs), instr, addr, eaddr); 545 show_regs(regs); 546 } 547#endif 548 549 if (user_mode(regs)) { 550 unsigned int __ua_flags = uaccess_save_and_enable(); 551 for (regbits = REGMASK_BITS(instr), rd = 0; regbits; 552 regbits >>= 1, rd += 1) 553 if (regbits & 1) { 554 if (LDST_L_BIT(instr)) { 555 unsigned int val; 556 get32t_unaligned_check(val, eaddr); 557 regs->uregs[rd] = val; 558 } else 559 put32t_unaligned_check(regs->uregs[rd], eaddr); 560 eaddr += 4; 561 } 562 uaccess_restore(__ua_flags); 563 } else { 564 for (regbits = REGMASK_BITS(instr), rd = 0; regbits; 565 regbits >>= 1, rd += 1) 566 if (regbits & 1) { 567 if (LDST_L_BIT(instr)) { 568 unsigned int val; 569 get32_unaligned_check(val, eaddr); 570 regs->uregs[rd] = val; 571 } else 572 put32_unaligned_check(regs->uregs[rd], eaddr); 573 eaddr += 4; 574 } 575 } 576 577 if (LDST_W_BIT(instr)) 578 regs->uregs[rn] = newaddr; 579 if (!LDST_L_BIT(instr) || !(REGMASK_BITS(instr) & (1 << 15))) 580 regs->ARM_pc -= correction; 581 return TYPE_DONE; 582 583fault: 584 regs->ARM_pc -= correction; 585 return TYPE_FAULT; 586 587bad: 588 pr_err("Alignment trap: not handling ldm with s-bit set\n"); 589 return TYPE_ERROR; 590} 591 592/* 593 * Convert Thumb ld/st instruction forms to equivalent ARM instructions so 594 * we can reuse ARM userland alignment fault fixups for Thumb. 595 * 596 * This implementation was initially based on the algorithm found in 597 * gdb/sim/arm/thumbemu.c. It is basically just a code reduction of same 598 * to convert only Thumb ld/st instruction forms to equivalent ARM forms. 599 * 600 * NOTES: 601 * 1. Comments below refer to ARM ARM DDI0100E Thumb Instruction sections. 602 * 2. If for some reason we're passed an non-ld/st Thumb instruction to 603 * decode, we return 0xdeadc0de. This should never happen under normal 604 * circumstances but if it does, we've got other problems to deal with 605 * elsewhere and we obviously can't fix those problems here. 606 */ 607 608static unsigned long 609thumb2arm(u16 tinstr) 610{ 611 u32 L = (tinstr & (1<<11)) >> 11; 612 613 switch ((tinstr & 0xf800) >> 11) { 614 /* 6.5.1 Format 1: */ 615 case 0x6000 >> 11: /* 7.1.52 STR(1) */ 616 case 0x6800 >> 11: /* 7.1.26 LDR(1) */ 617 case 0x7000 >> 11: /* 7.1.55 STRB(1) */ 618 case 0x7800 >> 11: /* 7.1.30 LDRB(1) */ 619 return 0xe5800000 | 620 ((tinstr & (1<<12)) << (22-12)) | /* fixup */ 621 (L<<20) | /* L==1? */ 622 ((tinstr & (7<<0)) << (12-0)) | /* Rd */ 623 ((tinstr & (7<<3)) << (16-3)) | /* Rn */ 624 ((tinstr & (31<<6)) >> /* immed_5 */ 625 (6 - ((tinstr & (1<<12)) ? 0 : 2))); 626 case 0x8000 >> 11: /* 7.1.57 STRH(1) */ 627 case 0x8800 >> 11: /* 7.1.32 LDRH(1) */ 628 return 0xe1c000b0 | 629 (L<<20) | /* L==1? */ 630 ((tinstr & (7<<0)) << (12-0)) | /* Rd */ 631 ((tinstr & (7<<3)) << (16-3)) | /* Rn */ 632 ((tinstr & (7<<6)) >> (6-1)) | /* immed_5[2:0] */ 633 ((tinstr & (3<<9)) >> (9-8)); /* immed_5[4:3] */ 634 635 /* 6.5.1 Format 2: */ 636 case 0x5000 >> 11: 637 case 0x5800 >> 11: 638 { 639 static const u32 subset[8] = { 640 0xe7800000, /* 7.1.53 STR(2) */ 641 0xe18000b0, /* 7.1.58 STRH(2) */ 642 0xe7c00000, /* 7.1.56 STRB(2) */ 643 0xe19000d0, /* 7.1.34 LDRSB */ 644 0xe7900000, /* 7.1.27 LDR(2) */ 645 0xe19000b0, /* 7.1.33 LDRH(2) */ 646 0xe7d00000, /* 7.1.31 LDRB(2) */ 647 0xe19000f0 /* 7.1.35 LDRSH */ 648 }; 649 return subset[(tinstr & (7<<9)) >> 9] | 650 ((tinstr & (7<<0)) << (12-0)) | /* Rd */ 651 ((tinstr & (7<<3)) << (16-3)) | /* Rn */ 652 ((tinstr & (7<<6)) >> (6-0)); /* Rm */ 653 } 654 655 /* 6.5.1 Format 3: */ 656 case 0x4800 >> 11: /* 7.1.28 LDR(3) */ 657 /* NOTE: This case is not technically possible. We're 658 * loading 32-bit memory data via PC relative 659 * addressing mode. So we can and should eliminate 660 * this case. But I'll leave it here for now. 661 */ 662 return 0xe59f0000 | 663 ((tinstr & (7<<8)) << (12-8)) | /* Rd */ 664 ((tinstr & 255) << (2-0)); /* immed_8 */ 665 666 /* 6.5.1 Format 4: */ 667 case 0x9000 >> 11: /* 7.1.54 STR(3) */ 668 case 0x9800 >> 11: /* 7.1.29 LDR(4) */ 669 return 0xe58d0000 | 670 (L<<20) | /* L==1? */ 671 ((tinstr & (7<<8)) << (12-8)) | /* Rd */ 672 ((tinstr & 255) << 2); /* immed_8 */ 673 674 /* 6.6.1 Format 1: */ 675 case 0xc000 >> 11: /* 7.1.51 STMIA */ 676 case 0xc800 >> 11: /* 7.1.25 LDMIA */ 677 { 678 u32 Rn = (tinstr & (7<<8)) >> 8; 679 u32 W = ((L<<Rn) & (tinstr&255)) ? 0 : 1<<21; 680 681 return 0xe8800000 | W | (L<<20) | (Rn<<16) | 682 (tinstr&255); 683 } 684 685 /* 6.6.1 Format 2: */ 686 case 0xb000 >> 11: /* 7.1.48 PUSH */ 687 case 0xb800 >> 11: /* 7.1.47 POP */ 688 if ((tinstr & (3 << 9)) == 0x0400) { 689 static const u32 subset[4] = { 690 0xe92d0000, /* STMDB sp!,{registers} */ 691 0xe92d4000, /* STMDB sp!,{registers,lr} */ 692 0xe8bd0000, /* LDMIA sp!,{registers} */ 693 0xe8bd8000 /* LDMIA sp!,{registers,pc} */ 694 }; 695 return subset[(L<<1) | ((tinstr & (1<<8)) >> 8)] | 696 (tinstr & 255); /* register_list */ 697 } 698 fallthrough; /* for illegal instruction case */ 699 700 default: 701 return BAD_INSTR; 702 } 703} 704 705/* 706 * Convert Thumb-2 32 bit LDM, STM, LDRD, STRD to equivalent instruction 707 * handlable by ARM alignment handler, also find the corresponding handler, 708 * so that we can reuse ARM userland alignment fault fixups for Thumb. 709 * 710 * @pinstr: original Thumb-2 instruction; returns new handlable instruction 711 * @regs: register context. 712 * @poffset: return offset from faulted addr for later writeback 713 * 714 * NOTES: 715 * 1. Comments below refer to ARMv7 DDI0406A Thumb Instruction sections. 716 * 2. Register name Rt from ARMv7 is same as Rd from ARMv6 (Rd is Rt) 717 */ 718static void * 719do_alignment_t32_to_handler(u32 *pinstr, struct pt_regs *regs, 720 union offset_union *poffset) 721{ 722 u32 instr = *pinstr; 723 u16 tinst1 = (instr >> 16) & 0xffff; 724 u16 tinst2 = instr & 0xffff; 725 726 switch (tinst1 & 0xffe0) { 727 /* A6.3.5 Load/Store multiple */ 728 case 0xe880: /* STM/STMIA/STMEA,LDM/LDMIA, PUSH/POP T2 */ 729 case 0xe8a0: /* ...above writeback version */ 730 case 0xe900: /* STMDB/STMFD, LDMDB/LDMEA */ 731 case 0xe920: /* ...above writeback version */ 732 /* no need offset decision since handler calculates it */ 733 return do_alignment_ldmstm; 734 735 case 0xf840: /* POP/PUSH T3 (single register) */ 736 if (RN_BITS(instr) == 13 && (tinst2 & 0x09ff) == 0x0904) { 737 u32 L = !!(LDST_L_BIT(instr)); 738 const u32 subset[2] = { 739 0xe92d0000, /* STMDB sp!,{registers} */ 740 0xe8bd0000, /* LDMIA sp!,{registers} */ 741 }; 742 *pinstr = subset[L] | (1<<RD_BITS(instr)); 743 return do_alignment_ldmstm; 744 } 745 /* Else fall through for illegal instruction case */ 746 break; 747 748 /* A6.3.6 Load/store double, STRD/LDRD(immed, lit, reg) */ 749 case 0xe860: 750 case 0xe960: 751 case 0xe8e0: 752 case 0xe9e0: 753 poffset->un = (tinst2 & 0xff) << 2; 754 fallthrough; 755 756 case 0xe940: 757 case 0xe9c0: 758 return do_alignment_ldrdstrd; 759 760 /* 761 * No need to handle load/store instructions up to word size 762 * since ARMv6 and later CPUs can perform unaligned accesses. 763 */ 764 default: 765 break; 766 } 767 return NULL; 768} 769 770static int alignment_get_arm(struct pt_regs *regs, u32 *ip, u32 *inst) 771{ 772 u32 instr = 0; 773 int fault; 774 775 if (user_mode(regs)) 776 fault = get_user(instr, ip); 777 else 778 fault = get_kernel_nofault(instr, ip); 779 780 *inst = __mem_to_opcode_arm(instr); 781 782 return fault; 783} 784 785static int alignment_get_thumb(struct pt_regs *regs, u16 *ip, u16 *inst) 786{ 787 u16 instr = 0; 788 int fault; 789 790 if (user_mode(regs)) 791 fault = get_user(instr, ip); 792 else 793 fault = get_kernel_nofault(instr, ip); 794 795 *inst = __mem_to_opcode_thumb16(instr); 796 797 return fault; 798} 799 800static int 801do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs) 802{ 803 union offset_union offset; 804 unsigned long instrptr; 805 int (*handler)(unsigned long addr, u32 instr, struct pt_regs *regs); 806 unsigned int type; 807 u32 instr = 0; 808 u16 tinstr = 0; 809 int isize = 4; 810 int thumb2_32b = 0; 811 int fault; 812 813 if (addr >= TASK_SIZE && user_mode(regs)) 814 harden_branch_predictor(); 815 816 if (interrupts_enabled(regs)) 817 local_irq_enable(); 818 819 instrptr = instruction_pointer(regs); 820 821 if (thumb_mode(regs)) { 822 u16 *ptr = (u16 *)(instrptr & ~1); 823 824 fault = alignment_get_thumb(regs, ptr, &tinstr); 825 if (!fault) { 826 if (cpu_architecture() >= CPU_ARCH_ARMv7 && 827 IS_T32(tinstr)) { 828 /* Thumb-2 32-bit */ 829 u16 tinst2; 830 fault = alignment_get_thumb(regs, ptr + 1, &tinst2); 831 instr = __opcode_thumb32_compose(tinstr, tinst2); 832 thumb2_32b = 1; 833 } else { 834 isize = 2; 835 instr = thumb2arm(tinstr); 836 } 837 } 838 } else { 839 fault = alignment_get_arm(regs, (void *)instrptr, &instr); 840 } 841 842 if (fault) { 843 type = TYPE_FAULT; 844 goto bad_or_fault; 845 } 846 847 if (user_mode(regs)) 848 goto user; 849 850 ai_sys += 1; 851 ai_sys_last_pc = (void *)instruction_pointer(regs); 852 853 fixup: 854 855 regs->ARM_pc += isize; 856 857 switch (CODING_BITS(instr)) { 858 case 0x00000000: /* 3.13.4 load/store instruction extensions */ 859 if (LDSTHD_I_BIT(instr)) 860 offset.un = (instr & 0xf00) >> 4 | (instr & 15); 861 else 862 offset.un = regs->uregs[RM_BITS(instr)]; 863 864 if ((instr & 0x000000f0) == 0x000000b0 || /* LDRH, STRH */ 865 (instr & 0x001000f0) == 0x001000f0) /* LDRSH */ 866 handler = do_alignment_ldrhstrh; 867 else if ((instr & 0x001000f0) == 0x000000d0 || /* LDRD */ 868 (instr & 0x001000f0) == 0x000000f0) /* STRD */ 869 handler = do_alignment_ldrdstrd; 870 else if ((instr & 0x01f00ff0) == 0x01000090) /* SWP */ 871 goto swp; 872 else 873 goto bad; 874 break; 875 876 case 0x04000000: /* ldr or str immediate */ 877 if (COND_BITS(instr) == 0xf0000000) /* NEON VLDn, VSTn */ 878 goto bad; 879 offset.un = OFFSET_BITS(instr); 880 handler = do_alignment_ldrstr; 881 break; 882 883 case 0x06000000: /* ldr or str register */ 884 offset.un = regs->uregs[RM_BITS(instr)]; 885 886 if (IS_SHIFT(instr)) { 887 unsigned int shiftval = SHIFT_BITS(instr); 888 889 switch(SHIFT_TYPE(instr)) { 890 case SHIFT_LSL: 891 offset.un <<= shiftval; 892 break; 893 894 case SHIFT_LSR: 895 offset.un >>= shiftval; 896 break; 897 898 case SHIFT_ASR: 899 offset.sn >>= shiftval; 900 break; 901 902 case SHIFT_RORRRX: 903 if (shiftval == 0) { 904 offset.un >>= 1; 905 if (regs->ARM_cpsr & PSR_C_BIT) 906 offset.un |= 1 << 31; 907 } else 908 offset.un = offset.un >> shiftval | 909 offset.un << (32 - shiftval); 910 break; 911 } 912 } 913 handler = do_alignment_ldrstr; 914 break; 915 916 case 0x08000000: /* ldm or stm, or thumb-2 32bit instruction */ 917 if (thumb2_32b) { 918 offset.un = 0; 919 handler = do_alignment_t32_to_handler(&instr, regs, &offset); 920 } else { 921 offset.un = 0; 922 handler = do_alignment_ldmstm; 923 } 924 break; 925 926 default: 927 goto bad; 928 } 929 930 if (!handler) 931 goto bad; 932 type = handler(addr, instr, regs); 933 934 if (type == TYPE_ERROR || type == TYPE_FAULT) { 935 regs->ARM_pc -= isize; 936 goto bad_or_fault; 937 } 938 939 if (type == TYPE_LDST) 940 do_alignment_finish_ldst(addr, instr, regs, offset); 941 942 if (thumb_mode(regs)) 943 regs->ARM_cpsr = it_advance(regs->ARM_cpsr); 944 945 return 0; 946 947 bad_or_fault: 948 if (type == TYPE_ERROR) 949 goto bad; 950 /* 951 * We got a fault - fix it up, or die. 952 */ 953 do_bad_area(addr, fsr, regs); 954 return 0; 955 956 swp: 957 pr_err("Alignment trap: not handling swp instruction\n"); 958 959 bad: 960 /* 961 * Oops, we didn't handle the instruction. 962 */ 963 pr_err("Alignment trap: not handling instruction " 964 "%0*x at [<%08lx>]\n", 965 isize << 1, 966 isize == 2 ? tinstr : instr, instrptr); 967 ai_skipped += 1; 968 return 1; 969 970 user: 971 ai_user += 1; 972 973 if (ai_usermode & UM_WARN) 974 printk("Alignment trap: %s (%d) PC=0x%08lx Instr=0x%0*x " 975 "Address=0x%08lx FSR 0x%03x\n", current->comm, 976 task_pid_nr(current), instrptr, 977 isize << 1, 978 isize == 2 ? tinstr : instr, 979 addr, fsr); 980 981 if (ai_usermode & UM_FIXUP) 982 goto fixup; 983 984 if (ai_usermode & UM_SIGNAL) { 985 force_sig_fault(SIGBUS, BUS_ADRALN, (void __user *)addr); 986 } else { 987 /* 988 * We're about to disable the alignment trap and return to 989 * user space. But if an interrupt occurs before actually 990 * reaching user space, then the IRQ vector entry code will 991 * notice that we were still in kernel space and therefore 992 * the alignment trap won't be re-enabled in that case as it 993 * is presumed to be always on from kernel space. 994 * Let's prevent that race by disabling interrupts here (they 995 * are disabled on the way back to user space anyway in 996 * entry-common.S) and disable the alignment trap only if 997 * there is no work pending for this thread. 998 */ 999 raw_local_irq_disable(); 1000 if (!(read_thread_flags() & _TIF_WORK_MASK)) 1001 set_cr(cr_no_alignment); 1002 } 1003 1004 return 0; 1005} 1006 1007static int __init noalign_setup(char *__unused) 1008{ 1009 set_cr(__clear_cr(CR_A)); 1010 return 1; 1011} 1012__setup("noalign", noalign_setup); 1013 1014/* 1015 * This needs to be done after sysctl_init_bases(), otherwise sys/ will be 1016 * overwritten. Actually, this shouldn't be in sys/ at all since 1017 * it isn't a sysctl, and it doesn't contain sysctl information. 1018 * We now locate it in /proc/cpu/alignment instead. 1019 */ 1020static int __init alignment_init(void) 1021{ 1022#ifdef CONFIG_PROC_FS 1023 struct proc_dir_entry *res; 1024 1025 res = proc_create("cpu/alignment", S_IWUSR | S_IRUGO, NULL, 1026 &alignment_proc_ops); 1027 if (!res) 1028 return -ENOMEM; 1029#endif 1030 1031 if (cpu_is_v6_unaligned()) { 1032 set_cr(__clear_cr(CR_A)); 1033 ai_usermode = safe_usermode(ai_usermode, false); 1034 } 1035 1036 cr_no_alignment = get_cr() & ~CR_A; 1037 1038 hook_fault_code(FAULT_CODE_ALIGNMENT, do_alignment, SIGBUS, BUS_ADRALN, 1039 "alignment exception"); 1040 1041 /* 1042 * ARMv6K and ARMv7 use fault status 3 (0b00011) as Access Flag section 1043 * fault, not as alignment error. 1044 * 1045 * TODO: handle ARMv6K properly. Runtime check for 'K' extension is 1046 * needed. 1047 */ 1048 if (cpu_architecture() <= CPU_ARCH_ARMv6) { 1049 hook_fault_code(3, do_alignment, SIGBUS, BUS_ADRALN, 1050 "alignment exception"); 1051 } 1052 1053 return 0; 1054} 1055 1056fs_initcall(alignment_init);
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