pm.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * arch/arm/mach-lpc32xx/pm.c
  4 *
  5 * Original authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com>
  6 * Modified by Kevin Wells <kevin.wells@nxp.com>
  7 *
  8 * 2005 (c) MontaVista Software, Inc.
  9 */
 10
 11/*
 12 * LPC32XX CPU and system power management
 13 *
 14 * The LPC32XX has three CPU modes for controlling system power: run,
 15 * direct-run, and halt modes. When switching between halt and run modes,
 16 * the CPU transistions through direct-run mode. For Linux, direct-run
 17 * mode is not used in normal operation. Halt mode is used when the
 18 * system is fully suspended.
 19 *
 20 * Run mode:
 21 * The ARM CPU clock (HCLK_PLL), HCLK bus clock, and PCLK bus clocks are
 22 * derived from the HCLK PLL. The HCLK and PCLK bus rates are divided from
 23 * the HCLK_PLL rate. Linux runs in this mode.
 24 *
 25 * Direct-run mode:
 26 * The ARM CPU clock, HCLK bus clock, and PCLK bus clocks are driven from
 27 * SYSCLK. SYSCLK is usually around 13MHz, but may vary based on SYSCLK
 28 * source or the frequency of the main oscillator. In this mode, the
 29 * HCLK_PLL can be safely enabled, changed, or disabled.
 30 *
 31 * Halt mode:
 32 * SYSCLK is gated off and the CPU and system clocks are halted.
 33 * Peripherals based on the 32KHz oscillator clock (ie, RTC, touch,
 34 * key scanner, etc.) still operate if enabled. In this state, an enabled
 35 * system event (ie, GPIO state change, RTC match, key press, etc.) will
 36 * wake the system up back into direct-run mode.
 37 *
 38 * DRAM refresh
 39 * DRAM clocking and refresh are slightly different for systems with DDR
 40 * DRAM or regular SDRAM devices. If SDRAM is used in the system, the
 41 * SDRAM will still be accessible in direct-run mode. In DDR based systems,
 42 * a transition to direct-run mode will stop all DDR accesses (no clocks).
 43 * Because of this, the code to switch power modes and the code to enter
 44 * and exit DRAM self-refresh modes must not be executed in DRAM. A small
 45 * section of IRAM is used instead for this.
 46 *
 47 * Suspend is handled with the following logic:
 48 *  Backup a small area of IRAM used for the suspend code
 49 *  Copy suspend code to IRAM
 50 *  Transfer control to code in IRAM
 51 *  Places DRAMs in self-refresh mode
 52 *  Enter direct-run mode
 53 *  Save state of HCLK_PLL PLL
 54 *  Disable HCLK_PLL PLL
 55 *  Enter halt mode - CPU and buses will stop
 56 *  System enters direct-run mode when an enabled event occurs
 57 *  HCLK PLL state is restored
 58 *  Run mode is entered
 59 *  DRAMS are placed back into normal mode
 60 *  Code execution returns from IRAM
 61 *  IRAM code are used for suspend is restored
 62 *  Suspend mode is exited
 63 */
 64
 65#include <linux/suspend.h>
 66#include <linux/io.h>
 67#include <linux/slab.h>
 68
 69#include <asm/cacheflush.h>
 70
 71#include "lpc32xx.h"
 72#include "common.h"
 73
 74#define TEMP_IRAM_AREA  IO_ADDRESS(LPC32XX_IRAM_BASE)
 75
 76/*
 77 * Both STANDBY and MEM suspend states are handled the same with no
 78 * loss of CPU or memory state
 79 */
 80static int lpc32xx_pm_enter(suspend_state_t state)
 81{
 82	int (*lpc32xx_suspend_ptr) (void);
 83	void *iram_swap_area;
 84
 85	/* Allocate some space for temporary IRAM storage */
 86	iram_swap_area = kmemdup((void *)TEMP_IRAM_AREA,
 87				 lpc32xx_sys_suspend_sz, GFP_KERNEL);
 88	if (!iram_swap_area)
 89		return -ENOMEM;
 90
 91	/*
 92	 * Copy code to suspend system into IRAM. The suspend code
 93	 * needs to run from IRAM as DRAM may no longer be available
 94	 * when the PLL is stopped.
 95	 */
 96	memcpy((void *) TEMP_IRAM_AREA, &lpc32xx_sys_suspend,
 97		lpc32xx_sys_suspend_sz);
 98	flush_icache_range((unsigned long)TEMP_IRAM_AREA,
 99		(unsigned long)(TEMP_IRAM_AREA) + lpc32xx_sys_suspend_sz);
100
101	/* Transfer to suspend code in IRAM */
102	lpc32xx_suspend_ptr = (void *) TEMP_IRAM_AREA;
103	flush_cache_all();
104	(void) lpc32xx_suspend_ptr();
105
106	/* Restore original IRAM contents */
107	memcpy((void *) TEMP_IRAM_AREA, iram_swap_area,
108		lpc32xx_sys_suspend_sz);
109
110	kfree(iram_swap_area);
111
112	return 0;
113}
114
115static const struct platform_suspend_ops lpc32xx_pm_ops = {
116	.valid	= suspend_valid_only_mem,
117	.enter	= lpc32xx_pm_enter,
118};
119
120#define EMC_DYN_MEM_CTRL_OFS 0x20
121#define EMC_SRMMC           (1 << 3)
122#define EMC_CTRL_REG io_p2v(LPC32XX_EMC_BASE + EMC_DYN_MEM_CTRL_OFS)
123static int __init lpc32xx_pm_init(void)
124{
125	/*
126	 * Setup SDRAM self-refresh clock to automatically disable o
127	 * start of self-refresh. This only needs to be done once.
128	 */
129	__raw_writel(__raw_readl(EMC_CTRL_REG) | EMC_SRMMC, EMC_CTRL_REG);
130
131	suspend_set_ops(&lpc32xx_pm_ops);
132
133	return 0;
134}
135arch_initcall(lpc32xx_pm_init);