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da850.c
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linux-6.19.14/arch/arm/mach-davinci/da850.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * TI DA850/OMAP-L138 chip specific setup 4 * 5 * Copyright (C) 2009 Texas Instruments Incorporated - https://www.ti.com/ 6 * 7 * Original Copyrights follow: 8 * 9 * 2009 (c) MontaVista Software, Inc. 10 */ 11 12#include <linux/gpio.h> 13#include <linux/init.h> 14#include <linux/io.h> 15#include <linux/mfd/da8xx-cfgchip.h> 16#include <linux/platform_device.h> 17#include <linux/regmap.h> 18#include <linux/regulator/consumer.h> 19#include <clocksource/timer-davinci.h> 20 21#include <asm/mach/map.h> 22 23#include "common.h" 24#include "cputype.h" 25#include "da8xx.h" 26#include "hardware.h" 27#include "pm.h" 28#include "irqs.h" 29#include "mux.h" 30 31#define DA850_PLL1_BASE 0x01e1a000 32#define DA850_TIMER64P2_BASE 0x01f0c000 33#define DA850_TIMER64P3_BASE 0x01f0d000 34 35#define DA850_REF_FREQ 24000000 36 37/* 38 * Device specific mux setup 39 * 40 * soc description mux mode mode mux dbg 41 * reg offset mask mode 42 */ 43static const struct mux_config da850_pins[] = { 44#ifdef CONFIG_DAVINCI_MUX 45 /* UART0 function */ 46 MUX_CFG(DA850, NUART0_CTS, 3, 24, 15, 2, false) 47 MUX_CFG(DA850, NUART0_RTS, 3, 28, 15, 2, false) 48 MUX_CFG(DA850, UART0_RXD, 3, 16, 15, 2, false) 49 MUX_CFG(DA850, UART0_TXD, 3, 20, 15, 2, false) 50 /* UART1 function */ 51 MUX_CFG(DA850, UART1_RXD, 4, 24, 15, 2, false) 52 MUX_CFG(DA850, UART1_TXD, 4, 28, 15, 2, false) 53 /* UART2 function */ 54 MUX_CFG(DA850, UART2_RXD, 4, 16, 15, 2, false) 55 MUX_CFG(DA850, UART2_TXD, 4, 20, 15, 2, false) 56 /* I2C1 function */ 57 MUX_CFG(DA850, I2C1_SCL, 4, 16, 15, 4, false) 58 MUX_CFG(DA850, I2C1_SDA, 4, 20, 15, 4, false) 59 /* I2C0 function */ 60 MUX_CFG(DA850, I2C0_SDA, 4, 12, 15, 2, false) 61 MUX_CFG(DA850, I2C0_SCL, 4, 8, 15, 2, false) 62 /* EMAC function */ 63 MUX_CFG(DA850, MII_TXEN, 2, 4, 15, 8, false) 64 MUX_CFG(DA850, MII_TXCLK, 2, 8, 15, 8, false) 65 MUX_CFG(DA850, MII_COL, 2, 12, 15, 8, false) 66 MUX_CFG(DA850, MII_TXD_3, 2, 16, 15, 8, false) 67 MUX_CFG(DA850, MII_TXD_2, 2, 20, 15, 8, false) 68 MUX_CFG(DA850, MII_TXD_1, 2, 24, 15, 8, false) 69 MUX_CFG(DA850, MII_TXD_0, 2, 28, 15, 8, false) 70 MUX_CFG(DA850, MII_RXCLK, 3, 0, 15, 8, false) 71 MUX_CFG(DA850, MII_RXDV, 3, 4, 15, 8, false) 72 MUX_CFG(DA850, MII_RXER, 3, 8, 15, 8, false) 73 MUX_CFG(DA850, MII_CRS, 3, 12, 15, 8, false) 74 MUX_CFG(DA850, MII_RXD_3, 3, 16, 15, 8, false) 75 MUX_CFG(DA850, MII_RXD_2, 3, 20, 15, 8, false) 76 MUX_CFG(DA850, MII_RXD_1, 3, 24, 15, 8, false) 77 MUX_CFG(DA850, MII_RXD_0, 3, 28, 15, 8, false) 78 MUX_CFG(DA850, MDIO_CLK, 4, 0, 15, 8, false) 79 MUX_CFG(DA850, MDIO_D, 4, 4, 15, 8, false) 80 MUX_CFG(DA850, RMII_TXD_0, 14, 12, 15, 8, false) 81 MUX_CFG(DA850, RMII_TXD_1, 14, 8, 15, 8, false) 82 MUX_CFG(DA850, RMII_TXEN, 14, 16, 15, 8, false) 83 MUX_CFG(DA850, RMII_CRS_DV, 15, 4, 15, 8, false) 84 MUX_CFG(DA850, RMII_RXD_0, 14, 24, 15, 8, false) 85 MUX_CFG(DA850, RMII_RXD_1, 14, 20, 15, 8, false) 86 MUX_CFG(DA850, RMII_RXER, 14, 28, 15, 8, false) 87 MUX_CFG(DA850, RMII_MHZ_50_CLK, 15, 0, 15, 0, false) 88 /* McASP function */ 89 MUX_CFG(DA850, ACLKR, 0, 0, 15, 1, false) 90 MUX_CFG(DA850, ACLKX, 0, 4, 15, 1, false) 91 MUX_CFG(DA850, AFSR, 0, 8, 15, 1, false) 92 MUX_CFG(DA850, AFSX, 0, 12, 15, 1, false) 93 MUX_CFG(DA850, AHCLKR, 0, 16, 15, 1, false) 94 MUX_CFG(DA850, AHCLKX, 0, 20, 15, 1, false) 95 MUX_CFG(DA850, AMUTE, 0, 24, 15, 1, false) 96 MUX_CFG(DA850, AXR_15, 1, 0, 15, 1, false) 97 MUX_CFG(DA850, AXR_14, 1, 4, 15, 1, false) 98 MUX_CFG(DA850, AXR_13, 1, 8, 15, 1, false) 99 MUX_CFG(DA850, AXR_12, 1, 12, 15, 1, false) 100 MUX_CFG(DA850, AXR_11, 1, 16, 15, 1, false) 101 MUX_CFG(DA850, AXR_10, 1, 20, 15, 1, false) 102 MUX_CFG(DA850, AXR_9, 1, 24, 15, 1, false) 103 MUX_CFG(DA850, AXR_8, 1, 28, 15, 1, false) 104 MUX_CFG(DA850, AXR_7, 2, 0, 15, 1, false) 105 MUX_CFG(DA850, AXR_6, 2, 4, 15, 1, false) 106 MUX_CFG(DA850, AXR_5, 2, 8, 15, 1, false) 107 MUX_CFG(DA850, AXR_4, 2, 12, 15, 1, false) 108 MUX_CFG(DA850, AXR_3, 2, 16, 15, 1, false) 109 MUX_CFG(DA850, AXR_2, 2, 20, 15, 1, false) 110 MUX_CFG(DA850, AXR_1, 2, 24, 15, 1, false) 111 MUX_CFG(DA850, AXR_0, 2, 28, 15, 1, false) 112 /* LCD function */ 113 MUX_CFG(DA850, LCD_D_7, 16, 8, 15, 2, false) 114 MUX_CFG(DA850, LCD_D_6, 16, 12, 15, 2, false) 115 MUX_CFG(DA850, LCD_D_5, 16, 16, 15, 2, false) 116 MUX_CFG(DA850, LCD_D_4, 16, 20, 15, 2, false) 117 MUX_CFG(DA850, LCD_D_3, 16, 24, 15, 2, false) 118 MUX_CFG(DA850, LCD_D_2, 16, 28, 15, 2, false) 119 MUX_CFG(DA850, LCD_D_1, 17, 0, 15, 2, false) 120 MUX_CFG(DA850, LCD_D_0, 17, 4, 15, 2, false) 121 MUX_CFG(DA850, LCD_D_15, 17, 8, 15, 2, false) 122 MUX_CFG(DA850, LCD_D_14, 17, 12, 15, 2, false) 123 MUX_CFG(DA850, LCD_D_13, 17, 16, 15, 2, false) 124 MUX_CFG(DA850, LCD_D_12, 17, 20, 15, 2, false) 125 MUX_CFG(DA850, LCD_D_11, 17, 24, 15, 2, false) 126 MUX_CFG(DA850, LCD_D_10, 17, 28, 15, 2, false) 127 MUX_CFG(DA850, LCD_D_9, 18, 0, 15, 2, false) 128 MUX_CFG(DA850, LCD_D_8, 18, 4, 15, 2, false) 129 MUX_CFG(DA850, LCD_PCLK, 18, 24, 15, 2, false) 130 MUX_CFG(DA850, LCD_HSYNC, 19, 0, 15, 2, false) 131 MUX_CFG(DA850, LCD_VSYNC, 19, 4, 15, 2, false) 132 MUX_CFG(DA850, NLCD_AC_ENB_CS, 19, 24, 15, 2, false) 133 /* MMC/SD0 function */ 134 MUX_CFG(DA850, MMCSD0_DAT_0, 10, 8, 15, 2, false) 135 MUX_CFG(DA850, MMCSD0_DAT_1, 10, 12, 15, 2, false) 136 MUX_CFG(DA850, MMCSD0_DAT_2, 10, 16, 15, 2, false) 137 MUX_CFG(DA850, MMCSD0_DAT_3, 10, 20, 15, 2, false) 138 MUX_CFG(DA850, MMCSD0_CLK, 10, 0, 15, 2, false) 139 MUX_CFG(DA850, MMCSD0_CMD, 10, 4, 15, 2, false) 140 /* MMC/SD1 function */ 141 MUX_CFG(DA850, MMCSD1_DAT_0, 18, 8, 15, 2, false) 142 MUX_CFG(DA850, MMCSD1_DAT_1, 19, 16, 15, 2, false) 143 MUX_CFG(DA850, MMCSD1_DAT_2, 19, 12, 15, 2, false) 144 MUX_CFG(DA850, MMCSD1_DAT_3, 19, 8, 15, 2, false) 145 MUX_CFG(DA850, MMCSD1_CLK, 18, 12, 15, 2, false) 146 MUX_CFG(DA850, MMCSD1_CMD, 18, 16, 15, 2, false) 147 /* EMIF2.5/EMIFA function */ 148 MUX_CFG(DA850, EMA_D_7, 9, 0, 15, 1, false) 149 MUX_CFG(DA850, EMA_D_6, 9, 4, 15, 1, false) 150 MUX_CFG(DA850, EMA_D_5, 9, 8, 15, 1, false) 151 MUX_CFG(DA850, EMA_D_4, 9, 12, 15, 1, false) 152 MUX_CFG(DA850, EMA_D_3, 9, 16, 15, 1, false) 153 MUX_CFG(DA850, EMA_D_2, 9, 20, 15, 1, false) 154 MUX_CFG(DA850, EMA_D_1, 9, 24, 15, 1, false) 155 MUX_CFG(DA850, EMA_D_0, 9, 28, 15, 1, false) 156 MUX_CFG(DA850, EMA_A_1, 12, 24, 15, 1, false) 157 MUX_CFG(DA850, EMA_A_2, 12, 20, 15, 1, false) 158 MUX_CFG(DA850, NEMA_CS_3, 7, 4, 15, 1, false) 159 MUX_CFG(DA850, NEMA_CS_4, 7, 8, 15, 1, false) 160 MUX_CFG(DA850, NEMA_WE, 7, 16, 15, 1, false) 161 MUX_CFG(DA850, NEMA_OE, 7, 20, 15, 1, false) 162 MUX_CFG(DA850, EMA_A_0, 12, 28, 15, 1, false) 163 MUX_CFG(DA850, EMA_A_3, 12, 16, 15, 1, false) 164 MUX_CFG(DA850, EMA_A_4, 12, 12, 15, 1, false) 165 MUX_CFG(DA850, EMA_A_5, 12, 8, 15, 1, false) 166 MUX_CFG(DA850, EMA_A_6, 12, 4, 15, 1, false) 167 MUX_CFG(DA850, EMA_A_7, 12, 0, 15, 1, false) 168 MUX_CFG(DA850, EMA_A_8, 11, 28, 15, 1, false) 169 MUX_CFG(DA850, EMA_A_9, 11, 24, 15, 1, false) 170 MUX_CFG(DA850, EMA_A_10, 11, 20, 15, 1, false) 171 MUX_CFG(DA850, EMA_A_11, 11, 16, 15, 1, false) 172 MUX_CFG(DA850, EMA_A_12, 11, 12, 15, 1, false) 173 MUX_CFG(DA850, EMA_A_13, 11, 8, 15, 1, false) 174 MUX_CFG(DA850, EMA_A_14, 11, 4, 15, 1, false) 175 MUX_CFG(DA850, EMA_A_15, 11, 0, 15, 1, false) 176 MUX_CFG(DA850, EMA_A_16, 10, 28, 15, 1, false) 177 MUX_CFG(DA850, EMA_A_17, 10, 24, 15, 1, false) 178 MUX_CFG(DA850, EMA_A_18, 10, 20, 15, 1, false) 179 MUX_CFG(DA850, EMA_A_19, 10, 16, 15, 1, false) 180 MUX_CFG(DA850, EMA_A_20, 10, 12, 15, 1, false) 181 MUX_CFG(DA850, EMA_A_21, 10, 8, 15, 1, false) 182 MUX_CFG(DA850, EMA_A_22, 10, 4, 15, 1, false) 183 MUX_CFG(DA850, EMA_A_23, 10, 0, 15, 1, false) 184 MUX_CFG(DA850, EMA_D_8, 8, 28, 15, 1, false) 185 MUX_CFG(DA850, EMA_D_9, 8, 24, 15, 1, false) 186 MUX_CFG(DA850, EMA_D_10, 8, 20, 15, 1, false) 187 MUX_CFG(DA850, EMA_D_11, 8, 16, 15, 1, false) 188 MUX_CFG(DA850, EMA_D_12, 8, 12, 15, 1, false) 189 MUX_CFG(DA850, EMA_D_13, 8, 8, 15, 1, false) 190 MUX_CFG(DA850, EMA_D_14, 8, 4, 15, 1, false) 191 MUX_CFG(DA850, EMA_D_15, 8, 0, 15, 1, false) 192 MUX_CFG(DA850, EMA_BA_1, 5, 24, 15, 1, false) 193 MUX_CFG(DA850, EMA_CLK, 6, 0, 15, 1, false) 194 MUX_CFG(DA850, EMA_WAIT_1, 6, 24, 15, 1, false) 195 MUX_CFG(DA850, NEMA_CS_2, 7, 0, 15, 1, false) 196 /* GPIO function */ 197 MUX_CFG(DA850, GPIO2_4, 6, 12, 15, 8, false) 198 MUX_CFG(DA850, GPIO2_6, 6, 4, 15, 8, false) 199 MUX_CFG(DA850, GPIO2_8, 5, 28, 15, 8, false) 200 MUX_CFG(DA850, GPIO2_15, 5, 0, 15, 8, false) 201 MUX_CFG(DA850, GPIO3_12, 7, 12, 15, 8, false) 202 MUX_CFG(DA850, GPIO3_13, 7, 8, 15, 8, false) 203 MUX_CFG(DA850, GPIO4_0, 10, 28, 15, 8, false) 204 MUX_CFG(DA850, GPIO4_1, 10, 24, 15, 8, false) 205 MUX_CFG(DA850, GPIO6_9, 13, 24, 15, 8, false) 206 MUX_CFG(DA850, GPIO6_10, 13, 20, 15, 8, false) 207 MUX_CFG(DA850, GPIO6_13, 13, 8, 15, 8, false) 208 MUX_CFG(DA850, RTC_ALARM, 0, 28, 15, 2, false) 209 /* VPIF Capture */ 210 MUX_CFG(DA850, VPIF_DIN0, 15, 4, 15, 1, false) 211 MUX_CFG(DA850, VPIF_DIN1, 15, 0, 15, 1, false) 212 MUX_CFG(DA850, VPIF_DIN2, 14, 28, 15, 1, false) 213 MUX_CFG(DA850, VPIF_DIN3, 14, 24, 15, 1, false) 214 MUX_CFG(DA850, VPIF_DIN4, 14, 20, 15, 1, false) 215 MUX_CFG(DA850, VPIF_DIN5, 14, 16, 15, 1, false) 216 MUX_CFG(DA850, VPIF_DIN6, 14, 12, 15, 1, false) 217 MUX_CFG(DA850, VPIF_DIN7, 14, 8, 15, 1, false) 218 MUX_CFG(DA850, VPIF_DIN8, 16, 4, 15, 1, false) 219 MUX_CFG(DA850, VPIF_DIN9, 16, 0, 15, 1, false) 220 MUX_CFG(DA850, VPIF_DIN10, 15, 28, 15, 1, false) 221 MUX_CFG(DA850, VPIF_DIN11, 15, 24, 15, 1, false) 222 MUX_CFG(DA850, VPIF_DIN12, 15, 20, 15, 1, false) 223 MUX_CFG(DA850, VPIF_DIN13, 15, 16, 15, 1, false) 224 MUX_CFG(DA850, VPIF_DIN14, 15, 12, 15, 1, false) 225 MUX_CFG(DA850, VPIF_DIN15, 15, 8, 15, 1, false) 226 MUX_CFG(DA850, VPIF_CLKIN0, 14, 0, 15, 1, false) 227 MUX_CFG(DA850, VPIF_CLKIN1, 14, 4, 15, 1, false) 228 MUX_CFG(DA850, VPIF_CLKIN2, 19, 8, 15, 1, false) 229 MUX_CFG(DA850, VPIF_CLKIN3, 19, 16, 15, 1, false) 230 /* VPIF Display */ 231 MUX_CFG(DA850, VPIF_DOUT0, 17, 4, 15, 1, false) 232 MUX_CFG(DA850, VPIF_DOUT1, 17, 0, 15, 1, false) 233 MUX_CFG(DA850, VPIF_DOUT2, 16, 28, 15, 1, false) 234 MUX_CFG(DA850, VPIF_DOUT3, 16, 24, 15, 1, false) 235 MUX_CFG(DA850, VPIF_DOUT4, 16, 20, 15, 1, false) 236 MUX_CFG(DA850, VPIF_DOUT5, 16, 16, 15, 1, false) 237 MUX_CFG(DA850, VPIF_DOUT6, 16, 12, 15, 1, false) 238 MUX_CFG(DA850, VPIF_DOUT7, 16, 8, 15, 1, false) 239 MUX_CFG(DA850, VPIF_DOUT8, 18, 4, 15, 1, false) 240 MUX_CFG(DA850, VPIF_DOUT9, 18, 0, 15, 1, false) 241 MUX_CFG(DA850, VPIF_DOUT10, 17, 28, 15, 1, false) 242 MUX_CFG(DA850, VPIF_DOUT11, 17, 24, 15, 1, false) 243 MUX_CFG(DA850, VPIF_DOUT12, 17, 20, 15, 1, false) 244 MUX_CFG(DA850, VPIF_DOUT13, 17, 16, 15, 1, false) 245 MUX_CFG(DA850, VPIF_DOUT14, 17, 12, 15, 1, false) 246 MUX_CFG(DA850, VPIF_DOUT15, 17, 8, 15, 1, false) 247 MUX_CFG(DA850, VPIF_CLKO2, 19, 12, 15, 1, false) 248 MUX_CFG(DA850, VPIF_CLKO3, 19, 20, 15, 1, false) 249#endif 250}; 251 252static struct map_desc da850_io_desc[] = { 253 { 254 .virtual = IO_VIRT, 255 .pfn = __phys_to_pfn(IO_PHYS), 256 .length = IO_SIZE, 257 .type = MT_DEVICE 258 }, 259 { 260 .virtual = DA8XX_CP_INTC_VIRT, 261 .pfn = __phys_to_pfn(DA8XX_CP_INTC_BASE), 262 .length = DA8XX_CP_INTC_SIZE, 263 .type = MT_DEVICE 264 }, 265}; 266 267/* Contents of JTAG ID register used to identify exact cpu type */ 268static struct davinci_id da850_ids[] = { 269 { 270 .variant = 0x0, 271 .part_no = 0xb7d1, 272 .manufacturer = 0x017, /* 0x02f >> 1 */ 273 .cpu_id = DAVINCI_CPU_ID_DA850, 274 .name = "da850/omap-l138", 275 }, 276 { 277 .variant = 0x1, 278 .part_no = 0xb7d1, 279 .manufacturer = 0x017, /* 0x02f >> 1 */ 280 .cpu_id = DAVINCI_CPU_ID_DA850, 281 .name = "da850/omap-l138/am18x", 282 }, 283}; 284 285/* VPIF resource, platform data */ 286static u64 da850_vpif_dma_mask = DMA_BIT_MASK(32); 287 288static struct resource da850_vpif_display_resource[] = { 289 { 290 .start = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT), 291 .end = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT), 292 .flags = IORESOURCE_IRQ, 293 }, 294}; 295 296static struct platform_device da850_vpif_display_dev = { 297 .name = "vpif_display", 298 .id = -1, 299 .dev = { 300 .dma_mask = &da850_vpif_dma_mask, 301 .coherent_dma_mask = DMA_BIT_MASK(32), 302 }, 303 .resource = da850_vpif_display_resource, 304 .num_resources = ARRAY_SIZE(da850_vpif_display_resource), 305}; 306 307static struct resource da850_vpif_capture_resource[] = { 308 { 309 .start = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT), 310 .end = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT), 311 .flags = IORESOURCE_IRQ, 312 }, 313 { 314 .start = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT), 315 .end = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT), 316 .flags = IORESOURCE_IRQ, 317 }, 318}; 319 320static struct platform_device da850_vpif_capture_dev = { 321 .name = "vpif_capture", 322 .id = -1, 323 .dev = { 324 .dma_mask = &da850_vpif_dma_mask, 325 .coherent_dma_mask = DMA_BIT_MASK(32), 326 }, 327 .resource = da850_vpif_capture_resource, 328 .num_resources = ARRAY_SIZE(da850_vpif_capture_resource), 329}; 330 331int __init da850_register_vpif_display(struct vpif_display_config 332 *display_config) 333{ 334 da850_vpif_display_dev.dev.platform_data = display_config; 335 return platform_device_register(&da850_vpif_display_dev); 336} 337 338int __init da850_register_vpif_capture(struct vpif_capture_config 339 *capture_config) 340{ 341 da850_vpif_capture_dev.dev.platform_data = capture_config; 342 return platform_device_register(&da850_vpif_capture_dev); 343} 344 345static const struct davinci_soc_info davinci_soc_info_da850 = { 346 .io_desc = da850_io_desc, 347 .io_desc_num = ARRAY_SIZE(da850_io_desc), 348 .jtag_id_reg = DA8XX_SYSCFG0_BASE + DA8XX_JTAG_ID_REG, 349 .ids = da850_ids, 350 .ids_num = ARRAY_SIZE(da850_ids), 351 .pinmux_base = DA8XX_SYSCFG0_BASE + 0x120, 352 .pinmux_pins = da850_pins, 353 .pinmux_pins_num = ARRAY_SIZE(da850_pins), 354 .sram_dma = DA8XX_SHARED_RAM_BASE, 355 .sram_len = SZ_128K, 356}; 357 358void __init da850_init(void) 359{ 360 davinci_common_init(&davinci_soc_info_da850); 361 362 da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K); 363 if (WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module")) 364 return; 365 366 da8xx_syscfg1_base = ioremap(DA8XX_SYSCFG1_BASE, SZ_4K); 367 WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module"); 368}
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