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sa1111.c
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linux-6.19.14/arch/arm/common/sa1111.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * linux/arch/arm/common/sa1111.c 4 * 5 * SA1111 support 6 * 7 * Original code by John Dorsey 8 * 9 * This file contains all generic SA1111 support. 10 * 11 * All initialization functions provided here are intended to be called 12 * from machine specific code with proper arguments when required. 13 */ 14#include <linux/module.h> 15#include <linux/gpio/driver.h> 16#include <linux/init.h> 17#include <linux/irq.h> 18#include <linux/kernel.h> 19#include <linux/delay.h> 20#include <linux/errno.h> 21#include <linux/ioport.h> 22#include <linux/platform_device.h> 23#include <linux/slab.h> 24#include <linux/spinlock.h> 25#include <linux/dma-map-ops.h> 26#include <linux/clk.h> 27#include <linux/io.h> 28 29#include <asm/mach/irq.h> 30#include <asm/mach-types.h> 31#include <linux/sizes.h> 32 33#include <asm/hardware/sa1111.h> 34 35#ifdef CONFIG_ARCH_SA1100 36#include <mach/hardware.h> 37#endif 38 39/* SA1111 IRQs */ 40#define IRQ_GPAIN0 (0) 41#define IRQ_GPAIN1 (1) 42#define IRQ_GPAIN2 (2) 43#define IRQ_GPAIN3 (3) 44#define IRQ_GPBIN0 (4) 45#define IRQ_GPBIN1 (5) 46#define IRQ_GPBIN2 (6) 47#define IRQ_GPBIN3 (7) 48#define IRQ_GPBIN4 (8) 49#define IRQ_GPBIN5 (9) 50#define IRQ_GPCIN0 (10) 51#define IRQ_GPCIN1 (11) 52#define IRQ_GPCIN2 (12) 53#define IRQ_GPCIN3 (13) 54#define IRQ_GPCIN4 (14) 55#define IRQ_GPCIN5 (15) 56#define IRQ_GPCIN6 (16) 57#define IRQ_GPCIN7 (17) 58#define IRQ_MSTXINT (18) 59#define IRQ_MSRXINT (19) 60#define IRQ_MSSTOPERRINT (20) 61#define IRQ_TPTXINT (21) 62#define IRQ_TPRXINT (22) 63#define IRQ_TPSTOPERRINT (23) 64#define SSPXMTINT (24) 65#define SSPRCVINT (25) 66#define SSPROR (26) 67#define AUDXMTDMADONEA (32) 68#define AUDRCVDMADONEA (33) 69#define AUDXMTDMADONEB (34) 70#define AUDRCVDMADONEB (35) 71#define AUDTFSR (36) 72#define AUDRFSR (37) 73#define AUDTUR (38) 74#define AUDROR (39) 75#define AUDDTS (40) 76#define AUDRDD (41) 77#define AUDSTO (42) 78#define IRQ_USBPWR (43) 79#define IRQ_HCIM (44) 80#define IRQ_HCIBUFFACC (45) 81#define IRQ_HCIRMTWKP (46) 82#define IRQ_NHCIMFCIR (47) 83#define IRQ_USB_PORT_RESUME (48) 84#define IRQ_S0_READY_NINT (49) 85#define IRQ_S1_READY_NINT (50) 86#define IRQ_S0_CD_VALID (51) 87#define IRQ_S1_CD_VALID (52) 88#define IRQ_S0_BVD1_STSCHG (53) 89#define IRQ_S1_BVD1_STSCHG (54) 90#define SA1111_IRQ_NR (55) 91 92extern void sa1110_mb_enable(void); 93extern void sa1110_mb_disable(void); 94 95/* 96 * We keep the following data for the overall SA1111. Note that the 97 * struct device and struct resource are "fake"; they should be supplied 98 * by the bus above us. However, in the interests of getting all SA1111 99 * drivers converted over to the device model, we provide this as an 100 * anchor point for all the other drivers. 101 */ 102struct sa1111 { 103 struct device *dev; 104 struct clk *clk; 105 unsigned long phys; 106 int irq; 107 int irq_base; /* base for cascaded on-chip IRQs */ 108 spinlock_t lock; 109 void __iomem *base; 110 struct sa1111_platform_data *pdata; 111 struct irq_domain *irqdomain; 112 struct gpio_chip gc; 113#ifdef CONFIG_PM 114 void *saved_state; 115#endif 116}; 117 118/* 119 * We _really_ need to eliminate this. Its only users 120 * are the PWM and DMA checking code. 121 */ 122static struct sa1111 *g_sa1111; 123 124struct sa1111_dev_info { 125 unsigned long offset; 126 unsigned long skpcr_mask; 127 bool dma; 128 unsigned int devid; 129 unsigned int hwirq[6]; 130}; 131 132static struct sa1111_dev_info sa1111_devices[] = { 133 { 134 .offset = SA1111_USB, 135 .skpcr_mask = SKPCR_UCLKEN, 136 .dma = true, 137 .devid = SA1111_DEVID_USB, 138 .hwirq = { 139 IRQ_USBPWR, 140 IRQ_HCIM, 141 IRQ_HCIBUFFACC, 142 IRQ_HCIRMTWKP, 143 IRQ_NHCIMFCIR, 144 IRQ_USB_PORT_RESUME 145 }, 146 }, 147 { 148 .offset = 0x0600, 149 .skpcr_mask = SKPCR_I2SCLKEN | SKPCR_L3CLKEN, 150 .dma = true, 151 .devid = SA1111_DEVID_SAC, 152 .hwirq = { 153 AUDXMTDMADONEA, 154 AUDXMTDMADONEB, 155 AUDRCVDMADONEA, 156 AUDRCVDMADONEB 157 }, 158 }, 159 { 160 .offset = 0x0800, 161 .skpcr_mask = SKPCR_SCLKEN, 162 .devid = SA1111_DEVID_SSP, 163 }, 164 { 165 .offset = SA1111_KBD, 166 .skpcr_mask = SKPCR_PTCLKEN, 167 .devid = SA1111_DEVID_PS2_KBD, 168 .hwirq = { 169 IRQ_TPRXINT, 170 IRQ_TPTXINT 171 }, 172 }, 173 { 174 .offset = SA1111_MSE, 175 .skpcr_mask = SKPCR_PMCLKEN, 176 .devid = SA1111_DEVID_PS2_MSE, 177 .hwirq = { 178 IRQ_MSRXINT, 179 IRQ_MSTXINT 180 }, 181 }, 182 { 183 .offset = 0x1800, 184 .skpcr_mask = 0, 185 .devid = SA1111_DEVID_PCMCIA, 186 .hwirq = { 187 IRQ_S0_READY_NINT, 188 IRQ_S0_CD_VALID, 189 IRQ_S0_BVD1_STSCHG, 190 IRQ_S1_READY_NINT, 191 IRQ_S1_CD_VALID, 192 IRQ_S1_BVD1_STSCHG, 193 }, 194 }, 195}; 196 197static int sa1111_map_irq(struct sa1111 *sachip, irq_hw_number_t hwirq) 198{ 199 return irq_create_mapping(sachip->irqdomain, hwirq); 200} 201 202/* 203 * SA1111 interrupt support. Since clearing an IRQ while there are 204 * active IRQs causes the interrupt output to pulse, the upper levels 205 * will call us again if there are more interrupts to process. 206 */ 207static void sa1111_irq_handler(struct irq_desc *desc) 208{ 209 unsigned int stat0, stat1, i; 210 struct sa1111 *sachip = irq_desc_get_handler_data(desc); 211 struct irq_domain *irqdomain; 212 void __iomem *mapbase = sachip->base + SA1111_INTC; 213 214 stat0 = readl_relaxed(mapbase + SA1111_INTSTATCLR0); 215 stat1 = readl_relaxed(mapbase + SA1111_INTSTATCLR1); 216 217 writel_relaxed(stat0, mapbase + SA1111_INTSTATCLR0); 218 219 desc->irq_data.chip->irq_ack(&desc->irq_data); 220 221 writel_relaxed(stat1, mapbase + SA1111_INTSTATCLR1); 222 223 if (stat0 == 0 && stat1 == 0) { 224 do_bad_IRQ(desc); 225 return; 226 } 227 228 irqdomain = sachip->irqdomain; 229 230 for (i = 0; stat0; i++, stat0 >>= 1) 231 if (stat0 & 1) 232 generic_handle_domain_irq(irqdomain, i); 233 234 for (i = 32; stat1; i++, stat1 >>= 1) 235 if (stat1 & 1) 236 generic_handle_domain_irq(irqdomain, i); 237 238 /* For level-based interrupts */ 239 desc->irq_data.chip->irq_unmask(&desc->irq_data); 240} 241 242static u32 sa1111_irqmask(struct irq_data *d) 243{ 244 return BIT(irqd_to_hwirq(d) & 31); 245} 246 247static int sa1111_irqbank(struct irq_data *d) 248{ 249 return (irqd_to_hwirq(d) / 32) * 4; 250} 251 252static void sa1111_ack_irq(struct irq_data *d) 253{ 254} 255 256static void sa1111_mask_irq(struct irq_data *d) 257{ 258 struct sa1111 *sachip = irq_data_get_irq_chip_data(d); 259 void __iomem *mapbase = sachip->base + SA1111_INTC + sa1111_irqbank(d); 260 u32 ie; 261 262 ie = readl_relaxed(mapbase + SA1111_INTEN0); 263 ie &= ~sa1111_irqmask(d); 264 writel(ie, mapbase + SA1111_INTEN0); 265} 266 267static void sa1111_unmask_irq(struct irq_data *d) 268{ 269 struct sa1111 *sachip = irq_data_get_irq_chip_data(d); 270 void __iomem *mapbase = sachip->base + SA1111_INTC + sa1111_irqbank(d); 271 u32 ie; 272 273 ie = readl_relaxed(mapbase + SA1111_INTEN0); 274 ie |= sa1111_irqmask(d); 275 writel_relaxed(ie, mapbase + SA1111_INTEN0); 276} 277 278/* 279 * Attempt to re-trigger the interrupt. The SA1111 contains a register 280 * (INTSET) which claims to do this. However, in practice no amount of 281 * manipulation of INTEN and INTSET guarantees that the interrupt will 282 * be triggered. In fact, its very difficult, if not impossible to get 283 * INTSET to re-trigger the interrupt. 284 */ 285static int sa1111_retrigger_irq(struct irq_data *d) 286{ 287 struct sa1111 *sachip = irq_data_get_irq_chip_data(d); 288 void __iomem *mapbase = sachip->base + SA1111_INTC + sa1111_irqbank(d); 289 u32 ip, mask = sa1111_irqmask(d); 290 int i; 291 292 ip = readl_relaxed(mapbase + SA1111_INTPOL0); 293 for (i = 0; i < 8; i++) { 294 writel_relaxed(ip ^ mask, mapbase + SA1111_INTPOL0); 295 writel_relaxed(ip, mapbase + SA1111_INTPOL0); 296 if (readl_relaxed(mapbase + SA1111_INTSTATCLR0) & mask) 297 break; 298 } 299 300 if (i == 8) { 301 pr_err("Danger Will Robinson: failed to re-trigger IRQ%d\n", 302 d->irq); 303 return 0; 304 } 305 306 return 1; 307} 308 309static int sa1111_type_irq(struct irq_data *d, unsigned int flags) 310{ 311 struct sa1111 *sachip = irq_data_get_irq_chip_data(d); 312 void __iomem *mapbase = sachip->base + SA1111_INTC + sa1111_irqbank(d); 313 u32 ip, mask = sa1111_irqmask(d); 314 315 if (flags == IRQ_TYPE_PROBE) 316 return 0; 317 318 if ((!(flags & IRQ_TYPE_EDGE_RISING) ^ !(flags & IRQ_TYPE_EDGE_FALLING)) == 0) 319 return -EINVAL; 320 321 ip = readl_relaxed(mapbase + SA1111_INTPOL0); 322 if (flags & IRQ_TYPE_EDGE_RISING) 323 ip &= ~mask; 324 else 325 ip |= mask; 326 writel_relaxed(ip, mapbase + SA1111_INTPOL0); 327 writel_relaxed(ip, mapbase + SA1111_WAKEPOL0); 328 329 return 0; 330} 331 332static int sa1111_wake_irq(struct irq_data *d, unsigned int on) 333{ 334 struct sa1111 *sachip = irq_data_get_irq_chip_data(d); 335 void __iomem *mapbase = sachip->base + SA1111_INTC + sa1111_irqbank(d); 336 u32 we, mask = sa1111_irqmask(d); 337 338 we = readl_relaxed(mapbase + SA1111_WAKEEN0); 339 if (on) 340 we |= mask; 341 else 342 we &= ~mask; 343 writel_relaxed(we, mapbase + SA1111_WAKEEN0); 344 345 return 0; 346} 347 348static struct irq_chip sa1111_irq_chip = { 349 .name = "SA1111", 350 .irq_ack = sa1111_ack_irq, 351 .irq_mask = sa1111_mask_irq, 352 .irq_unmask = sa1111_unmask_irq, 353 .irq_retrigger = sa1111_retrigger_irq, 354 .irq_set_type = sa1111_type_irq, 355 .irq_set_wake = sa1111_wake_irq, 356}; 357 358static int sa1111_irqdomain_map(struct irq_domain *d, unsigned int irq, 359 irq_hw_number_t hwirq) 360{ 361 struct sa1111 *sachip = d->host_data; 362 363 /* Disallow unavailable interrupts */ 364 if (hwirq > SSPROR && hwirq < AUDXMTDMADONEA) 365 return -EINVAL; 366 367 irq_set_chip_data(irq, sachip); 368 irq_set_chip_and_handler(irq, &sa1111_irq_chip, handle_edge_irq); 369 irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE); 370 371 return 0; 372} 373 374static const struct irq_domain_ops sa1111_irqdomain_ops = { 375 .map = sa1111_irqdomain_map, 376 .xlate = irq_domain_xlate_twocell, 377}; 378 379static int sa1111_setup_irq(struct sa1111 *sachip, unsigned irq_base) 380{ 381 void __iomem *irqbase = sachip->base + SA1111_INTC; 382 int ret; 383 384 /* 385 * We're guaranteed that this region hasn't been taken. 386 */ 387 request_mem_region(sachip->phys + SA1111_INTC, 512, "irq"); 388 389 ret = irq_alloc_descs(-1, irq_base, SA1111_IRQ_NR, -1); 390 if (ret <= 0) { 391 dev_err(sachip->dev, "unable to allocate %u irqs: %d\n", 392 SA1111_IRQ_NR, ret); 393 if (ret == 0) 394 ret = -EINVAL; 395 return ret; 396 } 397 398 sachip->irq_base = ret; 399 400 /* disable all IRQs */ 401 writel_relaxed(0, irqbase + SA1111_INTEN0); 402 writel_relaxed(0, irqbase + SA1111_INTEN1); 403 writel_relaxed(0, irqbase + SA1111_WAKEEN0); 404 writel_relaxed(0, irqbase + SA1111_WAKEEN1); 405 406 /* 407 * detect on rising edge. Note: Feb 2001 Errata for SA1111 408 * specifies that S0ReadyInt and S1ReadyInt should be '1'. 409 */ 410 writel_relaxed(0, irqbase + SA1111_INTPOL0); 411 writel_relaxed(BIT(IRQ_S0_READY_NINT & 31) | 412 BIT(IRQ_S1_READY_NINT & 31), 413 irqbase + SA1111_INTPOL1); 414 415 /* clear all IRQs */ 416 writel_relaxed(~0, irqbase + SA1111_INTSTATCLR0); 417 writel_relaxed(~0, irqbase + SA1111_INTSTATCLR1); 418 419 sachip->irqdomain = irq_domain_create_linear(NULL, SA1111_IRQ_NR, 420 &sa1111_irqdomain_ops, 421 sachip); 422 if (!sachip->irqdomain) { 423 irq_free_descs(sachip->irq_base, SA1111_IRQ_NR); 424 return -ENOMEM; 425 } 426 427 irq_domain_associate_many(sachip->irqdomain, 428 sachip->irq_base + IRQ_GPAIN0, 429 IRQ_GPAIN0, SSPROR + 1 - IRQ_GPAIN0); 430 irq_domain_associate_many(sachip->irqdomain, 431 sachip->irq_base + AUDXMTDMADONEA, 432 AUDXMTDMADONEA, 433 IRQ_S1_BVD1_STSCHG + 1 - AUDXMTDMADONEA); 434 435 /* 436 * Register SA1111 interrupt 437 */ 438 irq_set_irq_type(sachip->irq, IRQ_TYPE_EDGE_RISING); 439 irq_set_chained_handler_and_data(sachip->irq, sa1111_irq_handler, 440 sachip); 441 442 dev_info(sachip->dev, "Providing IRQ%u-%u\n", 443 sachip->irq_base, sachip->irq_base + SA1111_IRQ_NR - 1); 444 445 return 0; 446} 447 448static void sa1111_remove_irq(struct sa1111 *sachip) 449{ 450 struct irq_domain *domain = sachip->irqdomain; 451 void __iomem *irqbase = sachip->base + SA1111_INTC; 452 int i; 453 454 /* disable all IRQs */ 455 writel_relaxed(0, irqbase + SA1111_INTEN0); 456 writel_relaxed(0, irqbase + SA1111_INTEN1); 457 writel_relaxed(0, irqbase + SA1111_WAKEEN0); 458 writel_relaxed(0, irqbase + SA1111_WAKEEN1); 459 460 irq_set_chained_handler_and_data(sachip->irq, NULL, NULL); 461 for (i = 0; i < SA1111_IRQ_NR; i++) 462 irq_dispose_mapping(irq_find_mapping(domain, i)); 463 irq_domain_remove(domain); 464 465 release_mem_region(sachip->phys + SA1111_INTC, 512); 466} 467 468enum { 469 SA1111_GPIO_PXDDR = (SA1111_GPIO_PADDR - SA1111_GPIO_PADDR), 470 SA1111_GPIO_PXDRR = (SA1111_GPIO_PADRR - SA1111_GPIO_PADDR), 471 SA1111_GPIO_PXDWR = (SA1111_GPIO_PADWR - SA1111_GPIO_PADDR), 472 SA1111_GPIO_PXSDR = (SA1111_GPIO_PASDR - SA1111_GPIO_PADDR), 473 SA1111_GPIO_PXSSR = (SA1111_GPIO_PASSR - SA1111_GPIO_PADDR), 474}; 475 476static struct sa1111 *gc_to_sa1111(struct gpio_chip *gc) 477{ 478 return container_of(gc, struct sa1111, gc); 479} 480 481static void __iomem *sa1111_gpio_map_reg(struct sa1111 *sachip, unsigned offset) 482{ 483 void __iomem *reg = sachip->base + SA1111_GPIO; 484 485 if (offset < 4) 486 return reg + SA1111_GPIO_PADDR; 487 if (offset < 10) 488 return reg + SA1111_GPIO_PBDDR; 489 if (offset < 18) 490 return reg + SA1111_GPIO_PCDDR; 491 return NULL; 492} 493 494static u32 sa1111_gpio_map_bit(unsigned offset) 495{ 496 if (offset < 4) 497 return BIT(offset); 498 if (offset < 10) 499 return BIT(offset - 4); 500 if (offset < 18) 501 return BIT(offset - 10); 502 return 0; 503} 504 505static void sa1111_gpio_modify(void __iomem *reg, u32 mask, u32 set) 506{ 507 u32 val; 508 509 val = readl_relaxed(reg); 510 val &= ~mask; 511 val |= mask & set; 512 writel_relaxed(val, reg); 513} 514 515static int sa1111_gpio_get_direction(struct gpio_chip *gc, unsigned offset) 516{ 517 struct sa1111 *sachip = gc_to_sa1111(gc); 518 void __iomem *reg = sa1111_gpio_map_reg(sachip, offset); 519 u32 mask = sa1111_gpio_map_bit(offset); 520 521 return !!(readl_relaxed(reg + SA1111_GPIO_PXDDR) & mask); 522} 523 524static int sa1111_gpio_direction_input(struct gpio_chip *gc, unsigned offset) 525{ 526 struct sa1111 *sachip = gc_to_sa1111(gc); 527 unsigned long flags; 528 void __iomem *reg = sa1111_gpio_map_reg(sachip, offset); 529 u32 mask = sa1111_gpio_map_bit(offset); 530 531 spin_lock_irqsave(&sachip->lock, flags); 532 sa1111_gpio_modify(reg + SA1111_GPIO_PXDDR, mask, mask); 533 sa1111_gpio_modify(reg + SA1111_GPIO_PXSDR, mask, mask); 534 spin_unlock_irqrestore(&sachip->lock, flags); 535 536 return 0; 537} 538 539static int sa1111_gpio_direction_output(struct gpio_chip *gc, unsigned offset, 540 int value) 541{ 542 struct sa1111 *sachip = gc_to_sa1111(gc); 543 unsigned long flags; 544 void __iomem *reg = sa1111_gpio_map_reg(sachip, offset); 545 u32 mask = sa1111_gpio_map_bit(offset); 546 547 spin_lock_irqsave(&sachip->lock, flags); 548 sa1111_gpio_modify(reg + SA1111_GPIO_PXDWR, mask, value ? mask : 0); 549 sa1111_gpio_modify(reg + SA1111_GPIO_PXSSR, mask, value ? mask : 0); 550 sa1111_gpio_modify(reg + SA1111_GPIO_PXDDR, mask, 0); 551 sa1111_gpio_modify(reg + SA1111_GPIO_PXSDR, mask, 0); 552 spin_unlock_irqrestore(&sachip->lock, flags); 553 554 return 0; 555} 556 557static int sa1111_gpio_get(struct gpio_chip *gc, unsigned offset) 558{ 559 struct sa1111 *sachip = gc_to_sa1111(gc); 560 void __iomem *reg = sa1111_gpio_map_reg(sachip, offset); 561 u32 mask = sa1111_gpio_map_bit(offset); 562 563 return !!(readl_relaxed(reg + SA1111_GPIO_PXDRR) & mask); 564} 565 566static int sa1111_gpio_set(struct gpio_chip *gc, unsigned int offset, int value) 567{ 568 struct sa1111 *sachip = gc_to_sa1111(gc); 569 unsigned long flags; 570 void __iomem *reg = sa1111_gpio_map_reg(sachip, offset); 571 u32 mask = sa1111_gpio_map_bit(offset); 572 573 spin_lock_irqsave(&sachip->lock, flags); 574 sa1111_gpio_modify(reg + SA1111_GPIO_PXDWR, mask, value ? mask : 0); 575 sa1111_gpio_modify(reg + SA1111_GPIO_PXSSR, mask, value ? mask : 0); 576 spin_unlock_irqrestore(&sachip->lock, flags); 577 578 return 0; 579} 580 581static int sa1111_gpio_set_multiple(struct gpio_chip *gc, unsigned long *mask, 582 unsigned long *bits) 583{ 584 struct sa1111 *sachip = gc_to_sa1111(gc); 585 unsigned long flags; 586 void __iomem *reg = sachip->base + SA1111_GPIO; 587 u32 msk, val; 588 589 msk = *mask; 590 val = *bits; 591 592 spin_lock_irqsave(&sachip->lock, flags); 593 sa1111_gpio_modify(reg + SA1111_GPIO_PADWR, msk & 15, val); 594 sa1111_gpio_modify(reg + SA1111_GPIO_PASSR, msk & 15, val); 595 sa1111_gpio_modify(reg + SA1111_GPIO_PBDWR, (msk >> 4) & 255, val >> 4); 596 sa1111_gpio_modify(reg + SA1111_GPIO_PBSSR, (msk >> 4) & 255, val >> 4); 597 sa1111_gpio_modify(reg + SA1111_GPIO_PCDWR, (msk >> 12) & 255, val >> 12); 598 sa1111_gpio_modify(reg + SA1111_GPIO_PCSSR, (msk >> 12) & 255, val >> 12); 599 spin_unlock_irqrestore(&sachip->lock, flags); 600 601 return 0; 602} 603 604static int sa1111_gpio_to_irq(struct gpio_chip *gc, unsigned offset) 605{ 606 struct sa1111 *sachip = gc_to_sa1111(gc); 607 608 return sa1111_map_irq(sachip, offset); 609} 610 611static int sa1111_setup_gpios(struct sa1111 *sachip) 612{ 613 sachip->gc.label = "sa1111"; 614 sachip->gc.parent = sachip->dev; 615 sachip->gc.owner = THIS_MODULE; 616 sachip->gc.get_direction = sa1111_gpio_get_direction; 617 sachip->gc.direction_input = sa1111_gpio_direction_input; 618 sachip->gc.direction_output = sa1111_gpio_direction_output; 619 sachip->gc.get = sa1111_gpio_get; 620 sachip->gc.set = sa1111_gpio_set; 621 sachip->gc.set_multiple = sa1111_gpio_set_multiple; 622 sachip->gc.to_irq = sa1111_gpio_to_irq; 623 sachip->gc.base = -1; 624 sachip->gc.ngpio = 18; 625 626 return devm_gpiochip_add_data(sachip->dev, &sachip->gc, sachip); 627} 628 629/* 630 * Bring the SA1111 out of reset. This requires a set procedure: 631 * 1. nRESET asserted (by hardware) 632 * 2. CLK turned on from SA1110 633 * 3. nRESET deasserted 634 * 4. VCO turned on, PLL_BYPASS turned off 635 * 5. Wait lock time, then assert RCLKEn 636 * 7. PCR set to allow clocking of individual functions 637 * 638 * Until we've done this, the only registers we can access are: 639 * SBI_SKCR 640 * SBI_SMCR 641 * SBI_SKID 642 */ 643static void sa1111_wake(struct sa1111 *sachip) 644{ 645 unsigned long flags, r; 646 647 spin_lock_irqsave(&sachip->lock, flags); 648 649 clk_enable(sachip->clk); 650 651 /* 652 * Turn VCO on, and disable PLL Bypass. 653 */ 654 r = readl_relaxed(sachip->base + SA1111_SKCR); 655 r &= ~SKCR_VCO_OFF; 656 writel_relaxed(r, sachip->base + SA1111_SKCR); 657 r |= SKCR_PLL_BYPASS | SKCR_OE_EN; 658 writel_relaxed(r, sachip->base + SA1111_SKCR); 659 660 /* 661 * Wait lock time. SA1111 manual _doesn't_ 662 * specify a figure for this! We choose 100us. 663 */ 664 udelay(100); 665 666 /* 667 * Enable RCLK. We also ensure that RDYEN is set. 668 */ 669 r |= SKCR_RCLKEN | SKCR_RDYEN; 670 writel_relaxed(r, sachip->base + SA1111_SKCR); 671 672 /* 673 * Wait 14 RCLK cycles for the chip to finish coming out 674 * of reset. (RCLK=24MHz). This is 590ns. 675 */ 676 udelay(1); 677 678 /* 679 * Ensure all clocks are initially off. 680 */ 681 writel_relaxed(0, sachip->base + SA1111_SKPCR); 682 683 spin_unlock_irqrestore(&sachip->lock, flags); 684} 685 686#ifdef CONFIG_ARCH_SA1100 687 688static u32 sa1111_dma_mask[] = { 689 ~0, 690 ~(1 << 20), 691 ~(1 << 23), 692 ~(1 << 24), 693 ~(1 << 25), 694 ~(1 << 20), 695 ~(1 << 20), 696 0, 697}; 698 699/* 700 * Configure the SA1111 shared memory controller. 701 */ 702static void 703sa1111_configure_smc(struct sa1111 *sachip, int sdram, unsigned int drac, 704 unsigned int cas_latency) 705{ 706 unsigned int smcr = SMCR_DTIM | SMCR_MBGE | FInsrt(drac, SMCR_DRAC); 707 708 if (cas_latency == 3) 709 smcr |= SMCR_CLAT; 710 711 writel_relaxed(smcr, sachip->base + SA1111_SMCR); 712 713 /* 714 * Now clear the bits in the DMA mask to work around the SA1111 715 * DMA erratum (Intel StrongARM SA-1111 Microprocessor Companion 716 * Chip Specification Update, June 2000, Erratum #7). 717 */ 718 if (sachip->dev->dma_mask) 719 *sachip->dev->dma_mask &= sa1111_dma_mask[drac >> 2]; 720 721 sachip->dev->coherent_dma_mask &= sa1111_dma_mask[drac >> 2]; 722} 723#endif 724 725static void sa1111_dev_release(struct device *_dev) 726{ 727 struct sa1111_dev *dev = to_sa1111_device(_dev); 728 729 kfree(dev); 730} 731 732static int 733sa1111_init_one_child(struct sa1111 *sachip, struct resource *parent, 734 struct sa1111_dev_info *info) 735{ 736 struct sa1111_dev *dev; 737 unsigned i; 738 int ret; 739 740 dev = kzalloc(sizeof(struct sa1111_dev), GFP_KERNEL); 741 if (!dev) { 742 ret = -ENOMEM; 743 goto err_alloc; 744 } 745 746 device_initialize(&dev->dev); 747 dev_set_name(&dev->dev, "%4.4lx", info->offset); 748 dev->devid = info->devid; 749 dev->dev.parent = sachip->dev; 750 dev->dev.bus = &sa1111_bus_type; 751 dev->dev.release = sa1111_dev_release; 752 dev->res.start = sachip->phys + info->offset; 753 dev->res.end = dev->res.start + 511; 754 dev->res.name = dev_name(&dev->dev); 755 dev->res.flags = IORESOURCE_MEM; 756 dev->mapbase = sachip->base + info->offset; 757 dev->skpcr_mask = info->skpcr_mask; 758 759 for (i = 0; i < ARRAY_SIZE(info->hwirq); i++) 760 dev->hwirq[i] = info->hwirq[i]; 761 762 /* 763 * If the parent device has a DMA mask associated with it, and 764 * this child supports DMA, propagate it down to the children. 765 */ 766 if (info->dma && sachip->dev->dma_mask) { 767 dev->dma_mask = *sachip->dev->dma_mask; 768 dev->dev.dma_mask = &dev->dma_mask; 769 dev->dev.coherent_dma_mask = sachip->dev->coherent_dma_mask; 770 } 771 772 ret = request_resource(parent, &dev->res); 773 if (ret) { 774 dev_err(sachip->dev, "failed to allocate resource for %s\n", 775 dev->res.name); 776 goto err_resource; 777 } 778 779 ret = device_add(&dev->dev); 780 if (ret) 781 goto err_add; 782 return 0; 783 784 err_add: 785 release_resource(&dev->res); 786 err_resource: 787 put_device(&dev->dev); 788 err_alloc: 789 return ret; 790} 791 792static int __sa1111_probe(struct device *me, struct resource *mem, int irq) 793{ 794 struct sa1111_platform_data *pd = me->platform_data; 795 struct sa1111 *sachip; 796 unsigned long id; 797 unsigned int has_devs; 798 int i, ret = -ENODEV; 799 800 if (!pd) 801 return -EINVAL; 802 803 sachip = devm_kzalloc(me, sizeof(struct sa1111), GFP_KERNEL); 804 if (!sachip) 805 return -ENOMEM; 806 807 sachip->clk = devm_clk_get(me, "SA1111_CLK"); 808 if (IS_ERR(sachip->clk)) 809 return PTR_ERR(sachip->clk); 810 811 ret = clk_prepare(sachip->clk); 812 if (ret) 813 return ret; 814 815 spin_lock_init(&sachip->lock); 816 817 sachip->dev = me; 818 dev_set_drvdata(sachip->dev, sachip); 819 820 sachip->pdata = pd; 821 sachip->phys = mem->start; 822 sachip->irq = irq; 823 824 /* 825 * Map the whole region. This also maps the 826 * registers for our children. 827 */ 828 sachip->base = ioremap(mem->start, PAGE_SIZE * 2); 829 if (!sachip->base) { 830 ret = -ENOMEM; 831 goto err_clk_unprep; 832 } 833 834 /* 835 * Probe for the chip. Only touch the SBI registers. 836 */ 837 id = readl_relaxed(sachip->base + SA1111_SKID); 838 if ((id & SKID_ID_MASK) != SKID_SA1111_ID) { 839 printk(KERN_DEBUG "SA1111 not detected: ID = %08lx\n", id); 840 ret = -ENODEV; 841 goto err_unmap; 842 } 843 844 pr_info("SA1111 Microprocessor Companion Chip: silicon revision %lx, metal revision %lx\n", 845 (id & SKID_SIREV_MASK) >> 4, id & SKID_MTREV_MASK); 846 847 /* 848 * We found it. Wake the chip up, and initialise. 849 */ 850 sa1111_wake(sachip); 851 852 /* 853 * The interrupt controller must be initialised before any 854 * other device to ensure that the interrupts are available. 855 */ 856 ret = sa1111_setup_irq(sachip, pd->irq_base); 857 if (ret) 858 goto err_clk; 859 860 /* Setup the GPIOs - should really be done after the IRQ setup */ 861 ret = sa1111_setup_gpios(sachip); 862 if (ret) 863 goto err_irq; 864 865#ifdef CONFIG_ARCH_SA1100 866 { 867 unsigned int val; 868 869 /* 870 * The SDRAM configuration of the SA1110 and the SA1111 must 871 * match. This is very important to ensure that SA1111 accesses 872 * don't corrupt the SDRAM. Note that this ungates the SA1111's 873 * MBGNT signal, so we must have called sa1110_mb_disable() 874 * beforehand. 875 */ 876 sa1111_configure_smc(sachip, 1, 877 FExtr(MDCNFG, MDCNFG_SA1110_DRAC0), 878 FExtr(MDCNFG, MDCNFG_SA1110_TDL0)); 879 880 /* 881 * We only need to turn on DCLK whenever we want to use the 882 * DMA. It can otherwise be held firmly in the off position. 883 * (currently, we always enable it.) 884 */ 885 val = readl_relaxed(sachip->base + SA1111_SKPCR); 886 writel_relaxed(val | SKPCR_DCLKEN, sachip->base + SA1111_SKPCR); 887 888 /* 889 * Enable the SA1110 memory bus request and grant signals. 890 */ 891 sa1110_mb_enable(); 892 } 893#endif 894 895 g_sa1111 = sachip; 896 897 has_devs = ~0; 898 if (pd) 899 has_devs &= ~pd->disable_devs; 900 901 for (i = 0; i < ARRAY_SIZE(sa1111_devices); i++) 902 if (sa1111_devices[i].devid & has_devs) 903 sa1111_init_one_child(sachip, mem, &sa1111_devices[i]); 904 905 return 0; 906 907 err_irq: 908 sa1111_remove_irq(sachip); 909 err_clk: 910 clk_disable(sachip->clk); 911 err_unmap: 912 iounmap(sachip->base); 913 err_clk_unprep: 914 clk_unprepare(sachip->clk); 915 return ret; 916} 917 918static int sa1111_remove_one(struct device *dev, void *data) 919{ 920 struct sa1111_dev *sadev = to_sa1111_device(dev); 921 if (dev->bus != &sa1111_bus_type) 922 return 0; 923 device_del(&sadev->dev); 924 release_resource(&sadev->res); 925 put_device(&sadev->dev); 926 return 0; 927} 928 929static void __sa1111_remove(struct sa1111 *sachip) 930{ 931 device_for_each_child(sachip->dev, NULL, sa1111_remove_one); 932 933 sa1111_remove_irq(sachip); 934 935 clk_disable(sachip->clk); 936 clk_unprepare(sachip->clk); 937 938 iounmap(sachip->base); 939} 940 941struct sa1111_save_data { 942 unsigned int skcr; 943 unsigned int skpcr; 944 unsigned int skcdr; 945 unsigned char skaud; 946 unsigned char skpwm0; 947 unsigned char skpwm1; 948 949 /* 950 * Interrupt controller 951 */ 952 unsigned int intpol0; 953 unsigned int intpol1; 954 unsigned int inten0; 955 unsigned int inten1; 956 unsigned int wakepol0; 957 unsigned int wakepol1; 958 unsigned int wakeen0; 959 unsigned int wakeen1; 960}; 961 962#ifdef CONFIG_PM 963 964static int sa1111_suspend_noirq(struct device *dev) 965{ 966 struct sa1111 *sachip = dev_get_drvdata(dev); 967 struct sa1111_save_data *save; 968 unsigned long flags; 969 unsigned int val; 970 void __iomem *base; 971 972 save = kmalloc(sizeof(struct sa1111_save_data), GFP_KERNEL); 973 if (!save) 974 return -ENOMEM; 975 sachip->saved_state = save; 976 977 spin_lock_irqsave(&sachip->lock, flags); 978 979 /* 980 * Save state. 981 */ 982 base = sachip->base; 983 save->skcr = readl_relaxed(base + SA1111_SKCR); 984 save->skpcr = readl_relaxed(base + SA1111_SKPCR); 985 save->skcdr = readl_relaxed(base + SA1111_SKCDR); 986 save->skaud = readl_relaxed(base + SA1111_SKAUD); 987 save->skpwm0 = readl_relaxed(base + SA1111_SKPWM0); 988 save->skpwm1 = readl_relaxed(base + SA1111_SKPWM1); 989 990 writel_relaxed(0, sachip->base + SA1111_SKPWM0); 991 writel_relaxed(0, sachip->base + SA1111_SKPWM1); 992 993 base = sachip->base + SA1111_INTC; 994 save->intpol0 = readl_relaxed(base + SA1111_INTPOL0); 995 save->intpol1 = readl_relaxed(base + SA1111_INTPOL1); 996 save->inten0 = readl_relaxed(base + SA1111_INTEN0); 997 save->inten1 = readl_relaxed(base + SA1111_INTEN1); 998 save->wakepol0 = readl_relaxed(base + SA1111_WAKEPOL0); 999 save->wakepol1 = readl_relaxed(base + SA1111_WAKEPOL1); 1000 save->wakeen0 = readl_relaxed(base + SA1111_WAKEEN0); 1001 save->wakeen1 = readl_relaxed(base + SA1111_WAKEEN1); 1002 1003 /* 1004 * Disable. 1005 */ 1006 val = readl_relaxed(sachip->base + SA1111_SKCR); 1007 writel_relaxed(val | SKCR_SLEEP, sachip->base + SA1111_SKCR); 1008 1009 clk_disable(sachip->clk); 1010 1011 spin_unlock_irqrestore(&sachip->lock, flags); 1012 1013#ifdef CONFIG_ARCH_SA1100 1014 sa1110_mb_disable(); 1015#endif 1016 1017 return 0; 1018} 1019 1020/* 1021 * sa1111_resume - Restore the SA1111 device state. 1022 * @dev: device to restore 1023 * 1024 * Restore the general state of the SA1111; clock control and 1025 * interrupt controller. Other parts of the SA1111 must be 1026 * restored by their respective drivers, and must be called 1027 * via LDM after this function. 1028 */ 1029static int sa1111_resume_noirq(struct device *dev) 1030{ 1031 struct sa1111 *sachip = dev_get_drvdata(dev); 1032 struct sa1111_save_data *save; 1033 unsigned long flags, id; 1034 void __iomem *base; 1035 1036 save = sachip->saved_state; 1037 if (!save) 1038 return 0; 1039 1040 /* 1041 * Ensure that the SA1111 is still here. 1042 * FIXME: shouldn't do this here. 1043 */ 1044 id = readl_relaxed(sachip->base + SA1111_SKID); 1045 if ((id & SKID_ID_MASK) != SKID_SA1111_ID) { 1046 __sa1111_remove(sachip); 1047 dev_set_drvdata(dev, NULL); 1048 kfree(save); 1049 return 0; 1050 } 1051 1052 /* 1053 * First of all, wake up the chip. 1054 */ 1055 sa1111_wake(sachip); 1056 1057#ifdef CONFIG_ARCH_SA1100 1058 /* Enable the memory bus request/grant signals */ 1059 sa1110_mb_enable(); 1060#endif 1061 1062 /* 1063 * Only lock for write ops. Also, sa1111_wake must be called with 1064 * released spinlock! 1065 */ 1066 spin_lock_irqsave(&sachip->lock, flags); 1067 1068 writel_relaxed(0, sachip->base + SA1111_INTC + SA1111_INTEN0); 1069 writel_relaxed(0, sachip->base + SA1111_INTC + SA1111_INTEN1); 1070 1071 base = sachip->base; 1072 writel_relaxed(save->skcr, base + SA1111_SKCR); 1073 writel_relaxed(save->skpcr, base + SA1111_SKPCR); 1074 writel_relaxed(save->skcdr, base + SA1111_SKCDR); 1075 writel_relaxed(save->skaud, base + SA1111_SKAUD); 1076 writel_relaxed(save->skpwm0, base + SA1111_SKPWM0); 1077 writel_relaxed(save->skpwm1, base + SA1111_SKPWM1); 1078 1079 base = sachip->base + SA1111_INTC; 1080 writel_relaxed(save->intpol0, base + SA1111_INTPOL0); 1081 writel_relaxed(save->intpol1, base + SA1111_INTPOL1); 1082 writel_relaxed(save->inten0, base + SA1111_INTEN0); 1083 writel_relaxed(save->inten1, base + SA1111_INTEN1); 1084 writel_relaxed(save->wakepol0, base + SA1111_WAKEPOL0); 1085 writel_relaxed(save->wakepol1, base + SA1111_WAKEPOL1); 1086 writel_relaxed(save->wakeen0, base + SA1111_WAKEEN0); 1087 writel_relaxed(save->wakeen1, base + SA1111_WAKEEN1); 1088 1089 spin_unlock_irqrestore(&sachip->lock, flags); 1090 1091 sachip->saved_state = NULL; 1092 kfree(save); 1093 1094 return 0; 1095} 1096 1097#else 1098#define sa1111_suspend_noirq NULL 1099#define sa1111_resume_noirq NULL 1100#endif 1101 1102/** 1103 * sa1111_probe - probe for a single SA1111 chip. 1104 * @pdev: platform device. 1105 * 1106 * Probe for a SA1111 chip. This must be called 1107 * before any other SA1111-specific code. 1108 * 1109 * Returns: 1110 * * %-ENODEV - device not found. 1111 * * %-ENOMEM - memory allocation failure. 1112 * * %-EBUSY - physical address already marked in-use. 1113 * * %-EINVAL - no platform data passed 1114 * * %0 - successful. 1115 */ 1116static int sa1111_probe(struct platform_device *pdev) 1117{ 1118 struct resource *mem; 1119 int irq; 1120 1121 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1122 if (!mem) 1123 return -EINVAL; 1124 irq = platform_get_irq(pdev, 0); 1125 if (irq < 0) 1126 return irq; 1127 1128 return __sa1111_probe(&pdev->dev, mem, irq); 1129} 1130 1131static void sa1111_remove(struct platform_device *pdev) 1132{ 1133 struct sa1111 *sachip = platform_get_drvdata(pdev); 1134 1135 if (sachip) { 1136#ifdef CONFIG_PM 1137 kfree(sachip->saved_state); 1138 sachip->saved_state = NULL; 1139#endif 1140 __sa1111_remove(sachip); 1141 platform_set_drvdata(pdev, NULL); 1142 } 1143} 1144 1145static struct dev_pm_ops sa1111_pm_ops = { 1146 .suspend_noirq = sa1111_suspend_noirq, 1147 .resume_noirq = sa1111_resume_noirq, 1148}; 1149 1150/* 1151 * Not sure if this should be on the system bus or not yet. 1152 * We really want some way to register a system device at 1153 * the per-machine level, and then have this driver pick 1154 * up the registered devices. 1155 * 1156 * We also need to handle the SDRAM configuration for 1157 * PXA250/SA1110 machine classes. 1158 */ 1159static struct platform_driver sa1111_device_driver = { 1160 .probe = sa1111_probe, 1161 .remove = sa1111_remove, 1162 .driver = { 1163 .name = "sa1111", 1164 .pm = &sa1111_pm_ops, 1165 }, 1166}; 1167 1168/* 1169 * Get the parent device driver (us) structure 1170 * from a child function device 1171 */ 1172static inline struct sa1111 *sa1111_chip_driver(struct sa1111_dev *sadev) 1173{ 1174 return (struct sa1111 *)dev_get_drvdata(sadev->dev.parent); 1175} 1176 1177/* 1178 * The bits in the opdiv field are non-linear. 1179 */ 1180static unsigned char opdiv_table[] = { 1, 4, 2, 8 }; 1181 1182static unsigned int __sa1111_pll_clock(struct sa1111 *sachip) 1183{ 1184 unsigned int skcdr, fbdiv, ipdiv, opdiv; 1185 1186 skcdr = readl_relaxed(sachip->base + SA1111_SKCDR); 1187 1188 fbdiv = (skcdr & 0x007f) + 2; 1189 ipdiv = ((skcdr & 0x0f80) >> 7) + 2; 1190 opdiv = opdiv_table[(skcdr & 0x3000) >> 12]; 1191 1192 return 3686400 * fbdiv / (ipdiv * opdiv); 1193} 1194 1195/** 1196 * sa1111_pll_clock - return the current PLL clock frequency. 1197 * @sadev: SA1111 function block 1198 * 1199 * BUG: we should look at SKCR. We also blindly believe that 1200 * the chip is being fed with the 3.6864MHz clock. 1201 * 1202 * Returns the PLL clock in Hz. 1203 */ 1204unsigned int sa1111_pll_clock(struct sa1111_dev *sadev) 1205{ 1206 struct sa1111 *sachip = sa1111_chip_driver(sadev); 1207 1208 return __sa1111_pll_clock(sachip); 1209} 1210EXPORT_SYMBOL(sa1111_pll_clock); 1211 1212/** 1213 * sa1111_select_audio_mode - select I2S or AC link mode 1214 * @sadev: SA1111 function block 1215 * @mode: One of %SA1111_AUDIO_ACLINK or %SA1111_AUDIO_I2S 1216 * 1217 * Frob the SKCR to select AC Link mode or I2S mode for 1218 * the audio block. 1219 */ 1220void sa1111_select_audio_mode(struct sa1111_dev *sadev, int mode) 1221{ 1222 struct sa1111 *sachip = sa1111_chip_driver(sadev); 1223 unsigned long flags; 1224 unsigned int val; 1225 1226 spin_lock_irqsave(&sachip->lock, flags); 1227 1228 val = readl_relaxed(sachip->base + SA1111_SKCR); 1229 if (mode == SA1111_AUDIO_I2S) { 1230 val &= ~SKCR_SELAC; 1231 } else { 1232 val |= SKCR_SELAC; 1233 } 1234 writel_relaxed(val, sachip->base + SA1111_SKCR); 1235 1236 spin_unlock_irqrestore(&sachip->lock, flags); 1237} 1238EXPORT_SYMBOL(sa1111_select_audio_mode); 1239 1240/** 1241 * sa1111_set_audio_rate - set the audio sample rate 1242 * @sadev: SA1111 SAC function block 1243 * @rate: sample rate to select 1244 */ 1245int sa1111_set_audio_rate(struct sa1111_dev *sadev, int rate) 1246{ 1247 struct sa1111 *sachip = sa1111_chip_driver(sadev); 1248 unsigned int div; 1249 1250 if (sadev->devid != SA1111_DEVID_SAC) 1251 return -EINVAL; 1252 1253 div = (__sa1111_pll_clock(sachip) / 256 + rate / 2) / rate; 1254 if (div == 0) 1255 div = 1; 1256 if (div > 128) 1257 div = 128; 1258 1259 writel_relaxed(div - 1, sachip->base + SA1111_SKAUD); 1260 1261 return 0; 1262} 1263EXPORT_SYMBOL(sa1111_set_audio_rate); 1264 1265/** 1266 * sa1111_get_audio_rate - get the audio sample rate 1267 * @sadev: SA1111 SAC function block device 1268 */ 1269int sa1111_get_audio_rate(struct sa1111_dev *sadev) 1270{ 1271 struct sa1111 *sachip = sa1111_chip_driver(sadev); 1272 unsigned long div; 1273 1274 if (sadev->devid != SA1111_DEVID_SAC) 1275 return -EINVAL; 1276 1277 div = readl_relaxed(sachip->base + SA1111_SKAUD) + 1; 1278 1279 return __sa1111_pll_clock(sachip) / (256 * div); 1280} 1281EXPORT_SYMBOL(sa1111_get_audio_rate); 1282 1283/* 1284 * Individual device operations. 1285 */ 1286 1287/** 1288 * sa1111_enable_device - enable an on-chip SA1111 function block 1289 * @sadev: SA1111 function block device to enable 1290 */ 1291int sa1111_enable_device(struct sa1111_dev *sadev) 1292{ 1293 struct sa1111 *sachip = sa1111_chip_driver(sadev); 1294 unsigned long flags; 1295 unsigned int val; 1296 int ret = 0; 1297 1298 if (sachip->pdata && sachip->pdata->enable) 1299 ret = sachip->pdata->enable(sachip->pdata->data, sadev->devid); 1300 1301 if (ret == 0) { 1302 spin_lock_irqsave(&sachip->lock, flags); 1303 val = readl_relaxed(sachip->base + SA1111_SKPCR); 1304 writel_relaxed(val | sadev->skpcr_mask, sachip->base + SA1111_SKPCR); 1305 spin_unlock_irqrestore(&sachip->lock, flags); 1306 } 1307 return ret; 1308} 1309EXPORT_SYMBOL(sa1111_enable_device); 1310 1311/** 1312 * sa1111_disable_device - disable an on-chip SA1111 function block 1313 * @sadev: SA1111 function block device to disable 1314 */ 1315void sa1111_disable_device(struct sa1111_dev *sadev) 1316{ 1317 struct sa1111 *sachip = sa1111_chip_driver(sadev); 1318 unsigned long flags; 1319 unsigned int val; 1320 1321 spin_lock_irqsave(&sachip->lock, flags); 1322 val = readl_relaxed(sachip->base + SA1111_SKPCR); 1323 writel_relaxed(val & ~sadev->skpcr_mask, sachip->base + SA1111_SKPCR); 1324 spin_unlock_irqrestore(&sachip->lock, flags); 1325 1326 if (sachip->pdata && sachip->pdata->disable) 1327 sachip->pdata->disable(sachip->pdata->data, sadev->devid); 1328} 1329EXPORT_SYMBOL(sa1111_disable_device); 1330 1331int sa1111_get_irq(struct sa1111_dev *sadev, unsigned num) 1332{ 1333 struct sa1111 *sachip = sa1111_chip_driver(sadev); 1334 if (num >= ARRAY_SIZE(sadev->hwirq)) 1335 return -EINVAL; 1336 return sa1111_map_irq(sachip, sadev->hwirq[num]); 1337} 1338EXPORT_SYMBOL_GPL(sa1111_get_irq); 1339 1340/* 1341 * SA1111 "Register Access Bus." 1342 * 1343 * We model this as a regular bus type, and hang devices directly 1344 * off this. 1345 */ 1346static int sa1111_match(struct device *_dev, const struct device_driver *_drv) 1347{ 1348 struct sa1111_dev *dev = to_sa1111_device(_dev); 1349 const struct sa1111_driver *drv = SA1111_DRV(_drv); 1350 1351 return !!(dev->devid & drv->devid); 1352} 1353 1354static int sa1111_bus_probe(struct device *dev) 1355{ 1356 struct sa1111_dev *sadev = to_sa1111_device(dev); 1357 struct sa1111_driver *drv = SA1111_DRV(dev->driver); 1358 int ret = -ENODEV; 1359 1360 if (drv->probe) 1361 ret = drv->probe(sadev); 1362 return ret; 1363} 1364 1365static void sa1111_bus_remove(struct device *dev) 1366{ 1367 struct sa1111_dev *sadev = to_sa1111_device(dev); 1368 struct sa1111_driver *drv = SA1111_DRV(dev->driver); 1369 1370 if (drv->remove) 1371 drv->remove(sadev); 1372} 1373 1374const struct bus_type sa1111_bus_type = { 1375 .name = "sa1111-rab", 1376 .match = sa1111_match, 1377 .probe = sa1111_bus_probe, 1378 .remove = sa1111_bus_remove, 1379}; 1380EXPORT_SYMBOL(sa1111_bus_type); 1381 1382int sa1111_driver_register(struct sa1111_driver *driver) 1383{ 1384 driver->drv.bus = &sa1111_bus_type; 1385 return driver_register(&driver->drv); 1386} 1387EXPORT_SYMBOL(sa1111_driver_register); 1388 1389void sa1111_driver_unregister(struct sa1111_driver *driver) 1390{ 1391 driver_unregister(&driver->drv); 1392} 1393EXPORT_SYMBOL(sa1111_driver_unregister); 1394 1395static int __init sa1111_init(void) 1396{ 1397 int ret = bus_register(&sa1111_bus_type); 1398 if (ret == 0) 1399 platform_driver_register(&sa1111_device_driver); 1400 return ret; 1401} 1402 1403static void __exit sa1111_exit(void) 1404{ 1405 platform_driver_unregister(&sa1111_device_driver); 1406 bus_unregister(&sa1111_bus_type); 1407} 1408 1409subsys_initcall(sa1111_init); 1410module_exit(sa1111_exit); 1411 1412MODULE_DESCRIPTION("Intel Corporation SA1111 core driver"); 1413MODULE_LICENSE("GPL");
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