wm8750.dtsi

  1// SPDX-License-Identifier: GPL-2.0-or-later
  2/*
  3 * wm8750.dtsi - Device tree file for Wondermedia WM8750 SoC
  4 *
  5 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
  6 */
  7
  8/ {
  9	#address-cells = <1>;
 10	#size-cells = <1>;
 11	compatible = "wm,wm8750";
 12
 13	cpus {
 14		#address-cells = <1>;
 15		#size-cells = <0>;
 16
 17		cpu@0 {
 18			device_type = "cpu";
 19			compatible = "arm,arm1176jzf";
 20			reg = <0x0>;
 21		};
 22	};
 23
 24	aliases {
 25		serial0 = &uart0;
 26		serial1 = &uart1;
 27		serial2 = &uart2;
 28		serial3 = &uart3;
 29		serial4 = &uart4;
 30		serial5 = &uart5;
 31		i2c0 = &i2c_0;
 32		i2c1 = &i2c_1;
 33	};
 34
 35	soc {
 36		#address-cells = <1>;
 37		#size-cells = <1>;
 38		compatible = "simple-bus";
 39		ranges;
 40		interrupt-parent = <&intc0>;
 41
 42		intc0: interrupt-controller@d8140000 {
 43			compatible = "via,vt8500-intc";
 44			interrupt-controller;
 45			reg = <0xd8140000 0x10000>;
 46			#interrupt-cells = <1>;
 47		};
 48
 49		/* Secondary IC cascaded to intc0 */
 50		intc1: interrupt-controller@d8150000 {
 51			compatible = "via,vt8500-intc";
 52			interrupt-controller;
 53			#interrupt-cells = <1>;
 54			reg = <0xD8150000 0x10000>;
 55			interrupts = <56 57 58 59 60 61 62 63>;
 56		};
 57
 58		pinctrl: pinctrl@d8110000 {
 59			compatible = "wm,wm8750-pinctrl";
 60			reg = <0xd8110000 0x10000>;
 61			interrupt-controller;
 62			#interrupt-cells = <2>;
 63			gpio-controller;
 64			#gpio-cells = <2>;
 65		};
 66
 67		chipid@d8120000 {
 68			compatible = "via,vt8500-scc-id";
 69			reg = <0xd8120000 0x4>;
 70		};
 71
 72		pmc@d8130000 {
 73			compatible = "via,vt8500-pmc";
 74			reg = <0xd8130000 0x1000>;
 75
 76			clocks {
 77				#address-cells = <1>;
 78				#size-cells = <0>;
 79
 80				ref24: ref24M {
 81					#clock-cells = <0>;
 82					compatible = "fixed-clock";
 83					clock-frequency = <24000000>;
 84				};
 85
 86				ref25: ref25M {
 87					#clock-cells = <0>;
 88					compatible = "fixed-clock";
 89					clock-frequency = <25000000>;
 90				};
 91
 92				plla: plla {
 93					#clock-cells = <0>;
 94					compatible = "wm,wm8750-pll-clock";
 95					clocks = <&ref25>;
 96					reg = <0x200>;
 97				};
 98
 99				pllb: pllb {
100					#clock-cells = <0>;
101					compatible = "wm,wm8750-pll-clock";
102					clocks = <&ref25>;
103					reg = <0x204>;
104				};
105
106				pllc: pllc {
107					#clock-cells = <0>;
108					compatible = "wm,wm8750-pll-clock";
109					clocks = <&ref25>;
110					reg = <0x208>;
111				};
112
113				plld: plld {
114					#clock-cells = <0>;
115					compatible = "wm,wm8750-pll-clock";
116					clocks = <&ref25>;
117					reg = <0x20C>;
118				};
119
120				plle: plle {
121					#clock-cells = <0>;
122					compatible = "wm,wm8750-pll-clock";
123					clocks = <&ref25>;
124					reg = <0x210>;
125				};
126
127				clkarm: arm {
128					#clock-cells = <0>;
129					compatible = "via,vt8500-device-clock";
130					clocks = <&plla>;
131					divisor-reg = <0x300>;
132				};
133
134				clkahb: ahb {
135					#clock-cells = <0>;
136					compatible = "via,vt8500-device-clock";
137					clocks = <&pllb>;
138					divisor-reg = <0x304>;
139				};
140
141				clkapb: apb {
142					#clock-cells = <0>;
143					compatible = "via,vt8500-device-clock";
144					clocks = <&pllb>;
145					divisor-reg = <0x320>;
146				};
147
148				clkddr: ddr {
149					#clock-cells = <0>;
150					compatible = "via,vt8500-device-clock";
151					clocks = <&plld>;
152					divisor-reg = <0x310>;
153				};
154
155				clkuart0: uart0 {
156					#clock-cells = <0>;
157					compatible = "via,vt8500-device-clock";
158					clocks = <&ref24>;
159					enable-reg = <0x254>;
160					enable-bit = <24>;
161				};
162
163				clkuart1: uart1 {
164					#clock-cells = <0>;
165					compatible = "via,vt8500-device-clock";
166					clocks = <&ref24>;
167					enable-reg = <0x254>;
168					enable-bit = <25>;
169				};
170
171                                clkuart2: uart2 {
172                                        #clock-cells = <0>;
173                                        compatible = "via,vt8500-device-clock";
174                                        clocks = <&ref24>;
175                                        enable-reg = <0x254>;
176                                        enable-bit = <26>;
177                                };
178
179                                clkuart3: uart3 {
180                                        #clock-cells = <0>;
181                                        compatible = "via,vt8500-device-clock";
182                                        clocks = <&ref24>;
183                                        enable-reg = <0x254>;
184                                        enable-bit = <27>;
185                                };
186
187                                clkuart4: uart4 {
188                                        #clock-cells = <0>;
189                                        compatible = "via,vt8500-device-clock";
190                                        clocks = <&ref24>;
191                                        enable-reg = <0x254>;
192                                        enable-bit = <28>;
193                                };
194
195                                clkuart5: uart5 {
196                                        #clock-cells = <0>;
197                                        compatible = "via,vt8500-device-clock";
198                                        clocks = <&ref24>;
199                                        enable-reg = <0x254>;
200                                        enable-bit = <29>;
201                                };
202
203				clkpwm: pwm {
204					#clock-cells = <0>;
205					compatible = "via,vt8500-device-clock";
206					clocks = <&pllb>;
207					divisor-reg = <0x350>;
208					enable-reg = <0x250>;
209					enable-bit = <17>;
210				};
211
212				clksdhc: sdhc {
213					#clock-cells = <0>;
214					compatible = "via,vt8500-device-clock";
215					clocks = <&pllb>;
216					divisor-reg = <0x330>;
217					divisor-mask = <0x3f>;
218					enable-reg = <0x250>;
219					enable-bit = <0>;
220				};
221
222				clki2c0: i2c0clk {
223					#clock-cells = <0>;
224					compatible = "via,vt8500-device-clock";
225					clocks = <&pllb>;
226					divisor-reg = <0x3A0>;
227					enable-reg = <0x250>;
228					enable-bit = <8>;
229				};
230
231				clki2c1: i2c1clk {
232					#clock-cells = <0>;
233					compatible = "via,vt8500-device-clock";
234					clocks = <&pllb>;
235					divisor-reg = <0x3A4>;
236					enable-reg = <0x250>;
237					enable-bit = <9>;
238				};
239			};
240		};
241
242		pwm: pwm@d8220000 {
243			#pwm-cells = <3>;
244			compatible = "via,vt8500-pwm";
245			reg = <0xd8220000 0x100>;
246			clocks = <&clkpwm>;
247		};
248
249		timer@d8130100 {
250			compatible = "via,vt8500-timer";
251			reg = <0xd8130100 0x28>;
252			interrupts = <36>, <37>, <38>, <39>;
253		};
254
255		usb@d8007900 {
256			compatible = "via,vt8500-ehci";
257			reg = <0xd8007900 0x200>;
258			interrupts = <26>;
259		};
260
261		usb@d8007b00 {
262			compatible = "platform-uhci";
263			reg = <0xd8007b00 0x200>;
264			interrupts = <26>;
265		};
266
267		usb@d8008d00 {
268			compatible = "platform-uhci";
269			reg = <0xd8008d00 0x200>;
270			interrupts = <26>;
271		};
272
273		uart0: serial@d8200000 {
274			compatible = "via,vt8500-uart";
275			reg = <0xd8200000 0x1040>;
276			interrupts = <32>;
277			clocks = <&clkuart0>;
278			status = "disabled";
279		};
280
281		uart1: serial@d82b0000 {
282			compatible = "via,vt8500-uart";
283			reg = <0xd82b0000 0x1040>;
284			interrupts = <33>;
285			clocks = <&clkuart1>;
286			status = "disabled";
287		};
288
289                uart2: serial@d8210000 {
290                        compatible = "via,vt8500-uart";
291                        reg = <0xd8210000 0x1040>;
292                        interrupts = <47>;
293                        clocks = <&clkuart2>;
294			status = "disabled";
295                };
296
297                uart3: serial@d82c0000 {
298                        compatible = "via,vt8500-uart";
299                        reg = <0xd82c0000 0x1040>;
300                        interrupts = <50>;
301                        clocks = <&clkuart3>;
302			status = "disabled";
303                };
304
305                uart4: serial@d8370000 {
306                        compatible = "via,vt8500-uart";
307                        reg = <0xd8370000 0x1040>;
308                        interrupts = <30>;
309                        clocks = <&clkuart4>;
310			status = "disabled";
311                };
312
313                uart5: serial@d8380000 {
314                        compatible = "via,vt8500-uart";
315                        reg = <0xd8380000 0x1040>;
316                        interrupts = <43>;
317                        clocks = <&clkuart5>;
318			status = "disabled";
319                };
320
321		rtc@d8100000 {
322			compatible = "via,vt8500-rtc";
323			reg = <0xd8100000 0x10000>;
324			interrupts = <48>;
325		};
326
327		mmc@d800a000 {
328			compatible = "wm,wm8505-sdhc";
329			reg = <0xd800a000 0x1000>;
330			interrupts = <20 21>;
331			clocks = <&clksdhc>;
332			bus-width = <4>;
333			sdon-inverted;
334		};
335
336		i2c_0: i2c@d8280000 {
337			compatible = "wm,wm8505-i2c";
338			reg = <0xd8280000 0x1000>;
339			interrupts = <19>;
340			clocks = <&clki2c0>;
341			clock-frequency = <400000>;
342		};
343
344		i2c_1: i2c@d8320000 {
345			compatible = "wm,wm8505-i2c";
346			reg = <0xd8320000 0x1000>;
347			interrupts = <18>;
348			clocks = <&clki2c1>;
349			clock-frequency = <400000>;
350		};
351	};
352};