omap54xx-clocks.dtsi

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Device Tree Source for OMAP5 clock data
   4 *
   5 * Copyright (C) 2013 Texas Instruments, Inc.
   6 */
   7&cm_core_aon_clocks {
   8	pad_clks_src_ck: pad_clks_src_ck {
   9		#clock-cells = <0>;
  10		compatible = "fixed-clock";
  11		clock-output-names = "pad_clks_src_ck";
  12		clock-frequency = <12000000>;
  13	};
  14
  15	pad_clks_ck: pad_clks_ck@108 {
  16		#clock-cells = <0>;
  17		compatible = "ti,gate-clock";
  18		clock-output-names = "pad_clks_ck";
  19		clocks = <&pad_clks_src_ck>;
  20		ti,bit-shift = <8>;
  21		reg = <0x0108>;
  22	};
  23
  24	secure_32k_clk_src_ck: secure_32k_clk_src_ck {
  25		#clock-cells = <0>;
  26		compatible = "fixed-clock";
  27		clock-output-names = "secure_32k_clk_src_ck";
  28		clock-frequency = <32768>;
  29	};
  30
  31	slimbus_src_clk: slimbus_src_clk {
  32		#clock-cells = <0>;
  33		compatible = "fixed-clock";
  34		clock-output-names = "slimbus_src_clk";
  35		clock-frequency = <12000000>;
  36	};
  37
  38	slimbus_clk: slimbus_clk@108 {
  39		#clock-cells = <0>;
  40		compatible = "ti,gate-clock";
  41		clock-output-names = "slimbus_clk";
  42		clocks = <&slimbus_src_clk>;
  43		ti,bit-shift = <10>;
  44		reg = <0x0108>;
  45	};
  46
  47	sys_32k_ck: sys_32k_ck {
  48		#clock-cells = <0>;
  49		compatible = "fixed-clock";
  50		clock-output-names = "sys_32k_ck";
  51		clock-frequency = <32768>;
  52	};
  53
  54	virt_12000000_ck: virt_12000000_ck {
  55		#clock-cells = <0>;
  56		compatible = "fixed-clock";
  57		clock-output-names = "virt_12000000_ck";
  58		clock-frequency = <12000000>;
  59	};
  60
  61	virt_13000000_ck: virt_13000000_ck {
  62		#clock-cells = <0>;
  63		compatible = "fixed-clock";
  64		clock-output-names = "virt_13000000_ck";
  65		clock-frequency = <13000000>;
  66	};
  67
  68	virt_16800000_ck: virt_16800000_ck {
  69		#clock-cells = <0>;
  70		compatible = "fixed-clock";
  71		clock-output-names = "virt_16800000_ck";
  72		clock-frequency = <16800000>;
  73	};
  74
  75	virt_19200000_ck: virt_19200000_ck {
  76		#clock-cells = <0>;
  77		compatible = "fixed-clock";
  78		clock-output-names = "virt_19200000_ck";
  79		clock-frequency = <19200000>;
  80	};
  81
  82	virt_26000000_ck: virt_26000000_ck {
  83		#clock-cells = <0>;
  84		compatible = "fixed-clock";
  85		clock-output-names = "virt_26000000_ck";
  86		clock-frequency = <26000000>;
  87	};
  88
  89	virt_27000000_ck: virt_27000000_ck {
  90		#clock-cells = <0>;
  91		compatible = "fixed-clock";
  92		clock-output-names = "virt_27000000_ck";
  93		clock-frequency = <27000000>;
  94	};
  95
  96	virt_38400000_ck: virt_38400000_ck {
  97		#clock-cells = <0>;
  98		compatible = "fixed-clock";
  99		clock-output-names = "virt_38400000_ck";
 100		clock-frequency = <38400000>;
 101	};
 102
 103	xclk60mhsp1_ck: xclk60mhsp1_ck {
 104		#clock-cells = <0>;
 105		compatible = "fixed-clock";
 106		clock-output-names = "xclk60mhsp1_ck";
 107		clock-frequency = <60000000>;
 108	};
 109
 110	xclk60mhsp2_ck: xclk60mhsp2_ck {
 111		#clock-cells = <0>;
 112		compatible = "fixed-clock";
 113		clock-output-names = "xclk60mhsp2_ck";
 114		clock-frequency = <60000000>;
 115	};
 116
 117	dpll_abe_ck: dpll_abe_ck@1e0 {
 118		#clock-cells = <0>;
 119		compatible = "ti,omap4-dpll-m4xen-clock";
 120		clock-output-names = "dpll_abe_ck";
 121		clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
 122		reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
 123	};
 124
 125	dpll_abe_x2_ck: dpll_abe_x2_ck {
 126		#clock-cells = <0>;
 127		compatible = "ti,omap4-dpll-x2-clock";
 128		clock-output-names = "dpll_abe_x2_ck";
 129		clocks = <&dpll_abe_ck>;
 130	};
 131
 132	dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 {
 133		#clock-cells = <0>;
 134		compatible = "ti,divider-clock";
 135		clock-output-names = "dpll_abe_m2x2_ck";
 136		clocks = <&dpll_abe_x2_ck>;
 137		ti,max-div = <31>;
 138		reg = <0x01f0>;
 139		ti,index-starts-at-one;
 140	};
 141
 142	abe_24m_fclk: abe_24m_fclk {
 143		#clock-cells = <0>;
 144		compatible = "fixed-factor-clock";
 145		clock-output-names = "abe_24m_fclk";
 146		clocks = <&dpll_abe_m2x2_ck>;
 147		clock-mult = <1>;
 148		clock-div = <8>;
 149	};
 150
 151	abe_clk: abe_clk@108 {
 152		#clock-cells = <0>;
 153		compatible = "ti,divider-clock";
 154		clock-output-names = "abe_clk";
 155		clocks = <&dpll_abe_m2x2_ck>;
 156		ti,max-div = <4>;
 157		reg = <0x0108>;
 158		ti,index-power-of-two;
 159	};
 160
 161	abe_iclk: abe_iclk@528 {
 162		#clock-cells = <0>;
 163		compatible = "ti,divider-clock";
 164		clock-output-names = "abe_iclk";
 165		clocks = <&aess_fclk>;
 166		ti,bit-shift = <24>;
 167		reg = <0x0528>;
 168		ti,dividers = <2>, <1>;
 169	};
 170
 171	abe_lp_clk_div: abe_lp_clk_div {
 172		#clock-cells = <0>;
 173		compatible = "fixed-factor-clock";
 174		clock-output-names = "abe_lp_clk_div";
 175		clocks = <&dpll_abe_m2x2_ck>;
 176		clock-mult = <1>;
 177		clock-div = <16>;
 178	};
 179
 180	dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 {
 181		#clock-cells = <0>;
 182		compatible = "ti,divider-clock";
 183		clock-output-names = "dpll_abe_m3x2_ck";
 184		clocks = <&dpll_abe_x2_ck>;
 185		ti,max-div = <31>;
 186		reg = <0x01f4>;
 187		ti,index-starts-at-one;
 188	};
 189
 190	dpll_core_byp_mux: dpll_core_byp_mux@12c {
 191		#clock-cells = <0>;
 192		compatible = "ti,mux-clock";
 193		clock-output-names = "dpll_core_byp_mux";
 194		clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>;
 195		ti,bit-shift = <23>;
 196		reg = <0x012c>;
 197	};
 198
 199	dpll_core_ck: dpll_core_ck@120 {
 200		#clock-cells = <0>;
 201		compatible = "ti,omap4-dpll-core-clock";
 202		clock-output-names = "dpll_core_ck";
 203		clocks = <&sys_clkin>, <&dpll_core_byp_mux>;
 204		reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
 205	};
 206
 207	dpll_core_x2_ck: dpll_core_x2_ck {
 208		#clock-cells = <0>;
 209		compatible = "ti,omap4-dpll-x2-clock";
 210		clock-output-names = "dpll_core_x2_ck";
 211		clocks = <&dpll_core_ck>;
 212	};
 213
 214	dpll_core_h21x2_ck: dpll_core_h21x2_ck@150 {
 215		#clock-cells = <0>;
 216		compatible = "ti,divider-clock";
 217		clock-output-names = "dpll_core_h21x2_ck";
 218		clocks = <&dpll_core_x2_ck>;
 219		ti,max-div = <63>;
 220		reg = <0x0150>;
 221		ti,index-starts-at-one;
 222	};
 223
 224	c2c_fclk: c2c_fclk {
 225		#clock-cells = <0>;
 226		compatible = "fixed-factor-clock";
 227		clock-output-names = "c2c_fclk";
 228		clocks = <&dpll_core_h21x2_ck>;
 229		clock-mult = <1>;
 230		clock-div = <1>;
 231	};
 232
 233	c2c_iclk: c2c_iclk {
 234		#clock-cells = <0>;
 235		compatible = "fixed-factor-clock";
 236		clock-output-names = "c2c_iclk";
 237		clocks = <&c2c_fclk>;
 238		clock-mult = <1>;
 239		clock-div = <2>;
 240	};
 241
 242	dpll_core_h11x2_ck: dpll_core_h11x2_ck@138 {
 243		#clock-cells = <0>;
 244		compatible = "ti,divider-clock";
 245		clock-output-names = "dpll_core_h11x2_ck";
 246		clocks = <&dpll_core_x2_ck>;
 247		ti,max-div = <63>;
 248		reg = <0x0138>;
 249		ti,index-starts-at-one;
 250	};
 251
 252	dpll_core_h12x2_ck: dpll_core_h12x2_ck@13c {
 253		#clock-cells = <0>;
 254		compatible = "ti,divider-clock";
 255		clock-output-names = "dpll_core_h12x2_ck";
 256		clocks = <&dpll_core_x2_ck>;
 257		ti,max-div = <63>;
 258		reg = <0x013c>;
 259		ti,index-starts-at-one;
 260	};
 261
 262	dpll_core_h13x2_ck: dpll_core_h13x2_ck@140 {
 263		#clock-cells = <0>;
 264		compatible = "ti,divider-clock";
 265		clock-output-names = "dpll_core_h13x2_ck";
 266		clocks = <&dpll_core_x2_ck>;
 267		ti,max-div = <63>;
 268		reg = <0x0140>;
 269		ti,index-starts-at-one;
 270	};
 271
 272	dpll_core_h14x2_ck: dpll_core_h14x2_ck@144 {
 273		#clock-cells = <0>;
 274		compatible = "ti,divider-clock";
 275		clock-output-names = "dpll_core_h14x2_ck";
 276		clocks = <&dpll_core_x2_ck>;
 277		ti,max-div = <63>;
 278		reg = <0x0144>;
 279		ti,index-starts-at-one;
 280	};
 281
 282	dpll_core_h22x2_ck: dpll_core_h22x2_ck@154 {
 283		#clock-cells = <0>;
 284		compatible = "ti,divider-clock";
 285		clock-output-names = "dpll_core_h22x2_ck";
 286		clocks = <&dpll_core_x2_ck>;
 287		ti,max-div = <63>;
 288		reg = <0x0154>;
 289		ti,index-starts-at-one;
 290	};
 291
 292	dpll_core_h23x2_ck: dpll_core_h23x2_ck@158 {
 293		#clock-cells = <0>;
 294		compatible = "ti,divider-clock";
 295		clock-output-names = "dpll_core_h23x2_ck";
 296		clocks = <&dpll_core_x2_ck>;
 297		ti,max-div = <63>;
 298		reg = <0x0158>;
 299		ti,index-starts-at-one;
 300	};
 301
 302	dpll_core_h24x2_ck: dpll_core_h24x2_ck@15c {
 303		#clock-cells = <0>;
 304		compatible = "ti,divider-clock";
 305		clock-output-names = "dpll_core_h24x2_ck";
 306		clocks = <&dpll_core_x2_ck>;
 307		ti,max-div = <63>;
 308		reg = <0x015c>;
 309		ti,index-starts-at-one;
 310	};
 311
 312	dpll_core_m2_ck: dpll_core_m2_ck@130 {
 313		#clock-cells = <0>;
 314		compatible = "ti,divider-clock";
 315		clock-output-names = "dpll_core_m2_ck";
 316		clocks = <&dpll_core_ck>;
 317		ti,max-div = <31>;
 318		reg = <0x0130>;
 319		ti,index-starts-at-one;
 320	};
 321
 322	dpll_core_m3x2_ck: dpll_core_m3x2_ck@134 {
 323		#clock-cells = <0>;
 324		compatible = "ti,divider-clock";
 325		clock-output-names = "dpll_core_m3x2_ck";
 326		clocks = <&dpll_core_x2_ck>;
 327		ti,max-div = <31>;
 328		reg = <0x0134>;
 329		ti,index-starts-at-one;
 330	};
 331
 332	iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
 333		#clock-cells = <0>;
 334		compatible = "fixed-factor-clock";
 335		clock-output-names = "iva_dpll_hs_clk_div";
 336		clocks = <&dpll_core_h12x2_ck>;
 337		clock-mult = <1>;
 338		clock-div = <1>;
 339	};
 340
 341	dpll_iva_byp_mux: dpll_iva_byp_mux@1ac {
 342		#clock-cells = <0>;
 343		compatible = "ti,mux-clock";
 344		clock-output-names = "dpll_iva_byp_mux";
 345		clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>;
 346		ti,bit-shift = <23>;
 347		reg = <0x01ac>;
 348	};
 349
 350	dpll_iva_ck: dpll_iva_ck@1a0 {
 351		#clock-cells = <0>;
 352		compatible = "ti,omap4-dpll-clock";
 353		clock-output-names = "dpll_iva_ck";
 354		clocks = <&sys_clkin>, <&dpll_iva_byp_mux>;
 355		reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
 356		assigned-clocks = <&dpll_iva_ck>;
 357		assigned-clock-rates = <1165000000>;
 358	};
 359
 360	dpll_iva_x2_ck: dpll_iva_x2_ck {
 361		#clock-cells = <0>;
 362		compatible = "ti,omap4-dpll-x2-clock";
 363		clock-output-names = "dpll_iva_x2_ck";
 364		clocks = <&dpll_iva_ck>;
 365	};
 366
 367	dpll_iva_h11x2_ck: dpll_iva_h11x2_ck@1b8 {
 368		#clock-cells = <0>;
 369		compatible = "ti,divider-clock";
 370		clock-output-names = "dpll_iva_h11x2_ck";
 371		clocks = <&dpll_iva_x2_ck>;
 372		ti,max-div = <63>;
 373		reg = <0x01b8>;
 374		ti,index-starts-at-one;
 375		assigned-clocks = <&dpll_iva_h11x2_ck>;
 376		assigned-clock-rates = <465920000>;
 377	};
 378
 379	dpll_iva_h12x2_ck: dpll_iva_h12x2_ck@1bc {
 380		#clock-cells = <0>;
 381		compatible = "ti,divider-clock";
 382		clock-output-names = "dpll_iva_h12x2_ck";
 383		clocks = <&dpll_iva_x2_ck>;
 384		ti,max-div = <63>;
 385		reg = <0x01bc>;
 386		ti,index-starts-at-one;
 387		assigned-clocks = <&dpll_iva_h12x2_ck>;
 388		assigned-clock-rates = <388300000>;
 389	};
 390
 391	mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
 392		#clock-cells = <0>;
 393		compatible = "fixed-factor-clock";
 394		clock-output-names = "mpu_dpll_hs_clk_div";
 395		clocks = <&dpll_core_h12x2_ck>;
 396		clock-mult = <1>;
 397		clock-div = <1>;
 398	};
 399
 400	dpll_mpu_ck: dpll_mpu_ck@160 {
 401		#clock-cells = <0>;
 402		compatible = "ti,omap5-mpu-dpll-clock";
 403		clock-output-names = "dpll_mpu_ck";
 404		clocks = <&sys_clkin>, <&mpu_dpll_hs_clk_div>;
 405		reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
 406	};
 407
 408	dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 {
 409		#clock-cells = <0>;
 410		compatible = "ti,divider-clock";
 411		clock-output-names = "dpll_mpu_m2_ck";
 412		clocks = <&dpll_mpu_ck>;
 413		ti,max-div = <31>;
 414		reg = <0x0170>;
 415		ti,index-starts-at-one;
 416	};
 417
 418	per_dpll_hs_clk_div: per_dpll_hs_clk_div {
 419		#clock-cells = <0>;
 420		compatible = "fixed-factor-clock";
 421		clock-output-names = "per_dpll_hs_clk_div";
 422		clocks = <&dpll_abe_m3x2_ck>;
 423		clock-mult = <1>;
 424		clock-div = <2>;
 425	};
 426
 427	usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
 428		#clock-cells = <0>;
 429		compatible = "fixed-factor-clock";
 430		clock-output-names = "usb_dpll_hs_clk_div";
 431		clocks = <&dpll_abe_m3x2_ck>;
 432		clock-mult = <1>;
 433		clock-div = <3>;
 434	};
 435
 436	l3_iclk_div: l3_iclk_div@100 {
 437		#clock-cells = <0>;
 438		compatible = "ti,divider-clock";
 439		clock-output-names = "l3_iclk_div";
 440		ti,max-div = <2>;
 441		ti,bit-shift = <4>;
 442		reg = <0x100>;
 443		clocks = <&dpll_core_h12x2_ck>;
 444		ti,index-power-of-two;
 445	};
 446
 447	gpu_l3_iclk: gpu_l3_iclk {
 448		#clock-cells = <0>;
 449		compatible = "fixed-factor-clock";
 450		clock-output-names = "gpu_l3_iclk";
 451		clocks = <&l3_iclk_div>;
 452		clock-mult = <1>;
 453		clock-div = <1>;
 454	};
 455
 456	l4_root_clk_div: l4_root_clk_div@100 {
 457		#clock-cells = <0>;
 458		compatible = "ti,divider-clock";
 459		clock-output-names = "l4_root_clk_div";
 460		ti,max-div = <2>;
 461		ti,bit-shift = <8>;
 462		reg = <0x100>;
 463		clocks = <&l3_iclk_div>;
 464		ti,index-power-of-two;
 465	};
 466
 467	slimbus1_slimbus_clk: slimbus1_slimbus_clk@560 {
 468		#clock-cells = <0>;
 469		compatible = "ti,gate-clock";
 470		clock-output-names = "slimbus1_slimbus_clk";
 471		clocks = <&slimbus_clk>;
 472		ti,bit-shift = <11>;
 473		reg = <0x0560>;
 474	};
 475
 476	aess_fclk: aess_fclk@528 {
 477		#clock-cells = <0>;
 478		compatible = "ti,divider-clock";
 479		clock-output-names = "aess_fclk";
 480		clocks = <&abe_clk>;
 481		ti,bit-shift = <24>;
 482		ti,max-div = <2>;
 483		reg = <0x0528>;
 484	};
 485
 486	mcasp_sync_mux_ck: mcasp_sync_mux_ck@540 {
 487		#clock-cells = <0>;
 488		compatible = "ti,mux-clock";
 489		clock-output-names = "mcasp_sync_mux_ck";
 490		clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
 491		ti,bit-shift = <26>;
 492		reg = <0x0540>;
 493	};
 494
 495	mcasp_gfclk: mcasp_gfclk@540 {
 496		#clock-cells = <0>;
 497		compatible = "ti,mux-clock";
 498		clock-output-names = "mcasp_gfclk";
 499		clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
 500		ti,bit-shift = <24>;
 501		reg = <0x0540>;
 502	};
 503
 504	dummy_ck: dummy_ck {
 505		#clock-cells = <0>;
 506		compatible = "fixed-clock";
 507		clock-output-names = "dummy_ck";
 508		clock-frequency = <0>;
 509	};
 510};
 511&prm_clocks {
 512	sys_clkin: sys_clkin@110 {
 513		#clock-cells = <0>;
 514		compatible = "ti,mux-clock";
 515		clock-output-names = "sys_clkin";
 516		clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
 517		reg = <0x0110>;
 518		ti,index-starts-at-one;
 519	};
 520
 521	abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@108 {
 522		#clock-cells = <0>;
 523		compatible = "ti,mux-clock";
 524		clock-output-names = "abe_dpll_bypass_clk_mux";
 525		clocks = <&sys_clkin>, <&sys_32k_ck>;
 526		reg = <0x0108>;
 527	};
 528
 529	abe_dpll_clk_mux: abe_dpll_clk_mux@10c {
 530		#clock-cells = <0>;
 531		compatible = "ti,mux-clock";
 532		clock-output-names = "abe_dpll_clk_mux";
 533		clocks = <&sys_clkin>, <&sys_32k_ck>;
 534		reg = <0x010c>;
 535	};
 536
 537	custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
 538		#clock-cells = <0>;
 539		compatible = "fixed-factor-clock";
 540		clock-output-names = "custefuse_sys_gfclk_div";
 541		clocks = <&sys_clkin>;
 542		clock-mult = <1>;
 543		clock-div = <2>;
 544	};
 545
 546	dss_syc_gfclk_div: dss_syc_gfclk_div {
 547		#clock-cells = <0>;
 548		compatible = "fixed-factor-clock";
 549		clock-output-names = "dss_syc_gfclk_div";
 550		clocks = <&sys_clkin>;
 551		clock-mult = <1>;
 552		clock-div = <1>;
 553	};
 554
 555	wkupaon_iclk_mux: wkupaon_iclk_mux@108 {
 556		#clock-cells = <0>;
 557		compatible = "ti,mux-clock";
 558		clock-output-names = "wkupaon_iclk_mux";
 559		clocks = <&sys_clkin>, <&abe_lp_clk_div>;
 560		reg = <0x0108>;
 561	};
 562
 563	l3instr_ts_gclk_div: l3instr_ts_gclk_div {
 564		#clock-cells = <0>;
 565		compatible = "fixed-factor-clock";
 566		clock-output-names = "l3instr_ts_gclk_div";
 567		clocks = <&wkupaon_iclk_mux>;
 568		clock-mult = <1>;
 569		clock-div = <1>;
 570	};
 571};
 572
 573&cm_core_clocks {
 574
 575	dpll_per_byp_mux: dpll_per_byp_mux@14c {
 576		#clock-cells = <0>;
 577		compatible = "ti,mux-clock";
 578		clock-output-names = "dpll_per_byp_mux";
 579		clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>;
 580		ti,bit-shift = <23>;
 581		reg = <0x014c>;
 582	};
 583
 584	dpll_per_ck: dpll_per_ck@140 {
 585		#clock-cells = <0>;
 586		compatible = "ti,omap4-dpll-clock";
 587		clock-output-names = "dpll_per_ck";
 588		clocks = <&sys_clkin>, <&dpll_per_byp_mux>;
 589		reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
 590	};
 591
 592	dpll_per_x2_ck: dpll_per_x2_ck {
 593		#clock-cells = <0>;
 594		compatible = "ti,omap4-dpll-x2-clock";
 595		clock-output-names = "dpll_per_x2_ck";
 596		clocks = <&dpll_per_ck>;
 597	};
 598
 599	dpll_per_h11x2_ck: dpll_per_h11x2_ck@158 {
 600		#clock-cells = <0>;
 601		compatible = "ti,divider-clock";
 602		clock-output-names = "dpll_per_h11x2_ck";
 603		clocks = <&dpll_per_x2_ck>;
 604		ti,max-div = <63>;
 605		reg = <0x0158>;
 606		ti,index-starts-at-one;
 607	};
 608
 609	dpll_per_h12x2_ck: dpll_per_h12x2_ck@15c {
 610		#clock-cells = <0>;
 611		compatible = "ti,divider-clock";
 612		clock-output-names = "dpll_per_h12x2_ck";
 613		clocks = <&dpll_per_x2_ck>;
 614		ti,max-div = <63>;
 615		reg = <0x015c>;
 616		ti,index-starts-at-one;
 617	};
 618
 619	dpll_per_h14x2_ck: dpll_per_h14x2_ck@164 {
 620		#clock-cells = <0>;
 621		compatible = "ti,divider-clock";
 622		clock-output-names = "dpll_per_h14x2_ck";
 623		clocks = <&dpll_per_x2_ck>;
 624		ti,max-div = <63>;
 625		reg = <0x0164>;
 626		ti,index-starts-at-one;
 627	};
 628
 629	dpll_per_m2_ck: dpll_per_m2_ck@150 {
 630		#clock-cells = <0>;
 631		compatible = "ti,divider-clock";
 632		clock-output-names = "dpll_per_m2_ck";
 633		clocks = <&dpll_per_ck>;
 634		ti,max-div = <31>;
 635		reg = <0x0150>;
 636		ti,index-starts-at-one;
 637	};
 638
 639	dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 {
 640		#clock-cells = <0>;
 641		compatible = "ti,divider-clock";
 642		clock-output-names = "dpll_per_m2x2_ck";
 643		clocks = <&dpll_per_x2_ck>;
 644		ti,max-div = <31>;
 645		reg = <0x0150>;
 646		ti,index-starts-at-one;
 647	};
 648
 649	dpll_per_m3x2_ck: dpll_per_m3x2_ck@154 {
 650		#clock-cells = <0>;
 651		compatible = "ti,divider-clock";
 652		clock-output-names = "dpll_per_m3x2_ck";
 653		clocks = <&dpll_per_x2_ck>;
 654		ti,max-div = <31>;
 655		reg = <0x0154>;
 656		ti,index-starts-at-one;
 657	};
 658
 659	dpll_unipro1_ck: dpll_unipro1_ck@200 {
 660		#clock-cells = <0>;
 661		compatible = "ti,omap4-dpll-clock";
 662		clock-output-names = "dpll_unipro1_ck";
 663		clocks = <&sys_clkin>, <&sys_clkin>;
 664		reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
 665	};
 666
 667	dpll_unipro1_clkdcoldo: dpll_unipro1_clkdcoldo {
 668		#clock-cells = <0>;
 669		compatible = "fixed-factor-clock";
 670		clock-output-names = "dpll_unipro1_clkdcoldo";
 671		clocks = <&dpll_unipro1_ck>;
 672		clock-mult = <1>;
 673		clock-div = <1>;
 674	};
 675
 676	dpll_unipro1_m2_ck: dpll_unipro1_m2_ck@210 {
 677		#clock-cells = <0>;
 678		compatible = "ti,divider-clock";
 679		clock-output-names = "dpll_unipro1_m2_ck";
 680		clocks = <&dpll_unipro1_ck>;
 681		ti,max-div = <127>;
 682		reg = <0x0210>;
 683		ti,index-starts-at-one;
 684	};
 685
 686	dpll_unipro2_ck: dpll_unipro2_ck@1c0 {
 687		#clock-cells = <0>;
 688		compatible = "ti,omap4-dpll-clock";
 689		clock-output-names = "dpll_unipro2_ck";
 690		clocks = <&sys_clkin>, <&sys_clkin>;
 691		reg = <0x01c0>, <0x01c4>, <0x01cc>, <0x01c8>;
 692	};
 693
 694	dpll_unipro2_clkdcoldo: dpll_unipro2_clkdcoldo {
 695		#clock-cells = <0>;
 696		compatible = "fixed-factor-clock";
 697		clock-output-names = "dpll_unipro2_clkdcoldo";
 698		clocks = <&dpll_unipro2_ck>;
 699		clock-mult = <1>;
 700		clock-div = <1>;
 701	};
 702
 703	dpll_unipro2_m2_ck: dpll_unipro2_m2_ck@1d0 {
 704		#clock-cells = <0>;
 705		compatible = "ti,divider-clock";
 706		clock-output-names = "dpll_unipro2_m2_ck";
 707		clocks = <&dpll_unipro2_ck>;
 708		ti,max-div = <127>;
 709		reg = <0x01d0>;
 710		ti,index-starts-at-one;
 711	};
 712
 713	dpll_usb_byp_mux: dpll_usb_byp_mux@18c {
 714		#clock-cells = <0>;
 715		compatible = "ti,mux-clock";
 716		clock-output-names = "dpll_usb_byp_mux";
 717		clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>;
 718		ti,bit-shift = <23>;
 719		reg = <0x018c>;
 720	};
 721
 722	dpll_usb_ck: dpll_usb_ck@180 {
 723		#clock-cells = <0>;
 724		compatible = "ti,omap4-dpll-j-type-clock";
 725		clock-output-names = "dpll_usb_ck";
 726		clocks = <&sys_clkin>, <&dpll_usb_byp_mux>;
 727		reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
 728	};
 729
 730	dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
 731		#clock-cells = <0>;
 732		compatible = "fixed-factor-clock";
 733		clock-output-names = "dpll_usb_clkdcoldo";
 734		clocks = <&dpll_usb_ck>;
 735		clock-mult = <1>;
 736		clock-div = <1>;
 737	};
 738
 739	dpll_usb_m2_ck: dpll_usb_m2_ck@190 {
 740		#clock-cells = <0>;
 741		compatible = "ti,divider-clock";
 742		clock-output-names = "dpll_usb_m2_ck";
 743		clocks = <&dpll_usb_ck>;
 744		ti,max-div = <127>;
 745		reg = <0x0190>;
 746		ti,index-starts-at-one;
 747	};
 748
 749	func_128m_clk: func_128m_clk {
 750		#clock-cells = <0>;
 751		compatible = "fixed-factor-clock";
 752		clock-output-names = "func_128m_clk";
 753		clocks = <&dpll_per_h11x2_ck>;
 754		clock-mult = <1>;
 755		clock-div = <2>;
 756	};
 757
 758	func_12m_fclk: func_12m_fclk {
 759		#clock-cells = <0>;
 760		compatible = "fixed-factor-clock";
 761		clock-output-names = "func_12m_fclk";
 762		clocks = <&dpll_per_m2x2_ck>;
 763		clock-mult = <1>;
 764		clock-div = <16>;
 765	};
 766
 767	func_24m_clk: func_24m_clk {
 768		#clock-cells = <0>;
 769		compatible = "fixed-factor-clock";
 770		clock-output-names = "func_24m_clk";
 771		clocks = <&dpll_per_m2_ck>;
 772		clock-mult = <1>;
 773		clock-div = <4>;
 774	};
 775
 776	func_48m_fclk: func_48m_fclk {
 777		#clock-cells = <0>;
 778		compatible = "fixed-factor-clock";
 779		clock-output-names = "func_48m_fclk";
 780		clocks = <&dpll_per_m2x2_ck>;
 781		clock-mult = <1>;
 782		clock-div = <4>;
 783	};
 784
 785	func_96m_fclk: func_96m_fclk {
 786		#clock-cells = <0>;
 787		compatible = "fixed-factor-clock";
 788		clock-output-names = "func_96m_fclk";
 789		clocks = <&dpll_per_m2x2_ck>;
 790		clock-mult = <1>;
 791		clock-div = <2>;
 792	};
 793
 794	l3init_60m_fclk: l3init_60m_fclk@104 {
 795		#clock-cells = <0>;
 796		compatible = "ti,divider-clock";
 797		clock-output-names = "l3init_60m_fclk";
 798		clocks = <&dpll_usb_m2_ck>;
 799		reg = <0x0104>;
 800		ti,dividers = <1>, <8>;
 801	};
 802
 803	iss_ctrlclk: iss_ctrlclk@1320 {
 804		#clock-cells = <0>;
 805		compatible = "ti,gate-clock";
 806		clock-output-names = "iss_ctrlclk";
 807		clocks = <&func_96m_fclk>;
 808		ti,bit-shift = <8>;
 809		reg = <0x1320>;
 810	};
 811
 812	lli_txphy_clk: lli_txphy_clk@f20 {
 813		#clock-cells = <0>;
 814		compatible = "ti,gate-clock";
 815		clock-output-names = "lli_txphy_clk";
 816		clocks = <&dpll_unipro1_clkdcoldo>;
 817		ti,bit-shift = <8>;
 818		reg = <0x0f20>;
 819	};
 820
 821	lli_txphy_ls_clk: lli_txphy_ls_clk@f20 {
 822		#clock-cells = <0>;
 823		compatible = "ti,gate-clock";
 824		clock-output-names = "lli_txphy_ls_clk";
 825		clocks = <&dpll_unipro1_m2_ck>;
 826		ti,bit-shift = <9>;
 827		reg = <0x0f20>;
 828	};
 829
 830	usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 {
 831		#clock-cells = <0>;
 832		compatible = "ti,gate-clock";
 833		clock-output-names = "usb_phy_cm_clk32k";
 834		clocks = <&sys_32k_ck>;
 835		ti,bit-shift = <8>;
 836		reg = <0x0640>;
 837	};
 838
 839	fdif_fclk: fdif_fclk@1328 {
 840		#clock-cells = <0>;
 841		compatible = "ti,divider-clock";
 842		clock-output-names = "fdif_fclk";
 843		clocks = <&dpll_per_h11x2_ck>;
 844		ti,bit-shift = <24>;
 845		ti,max-div = <2>;
 846		reg = <0x1328>;
 847	};
 848
 849	gpu_core_gclk_mux: gpu_core_gclk_mux@1520 {
 850		#clock-cells = <0>;
 851		compatible = "ti,mux-clock";
 852		clock-output-names = "gpu_core_gclk_mux";
 853		clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
 854		ti,bit-shift = <24>;
 855		reg = <0x1520>;
 856	};
 857
 858	gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1520 {
 859		#clock-cells = <0>;
 860		compatible = "ti,mux-clock";
 861		clock-output-names = "gpu_hyd_gclk_mux";
 862		clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
 863		ti,bit-shift = <25>;
 864		reg = <0x1520>;
 865	};
 866
 867	hsi_fclk: hsi_fclk@1638 {
 868		#clock-cells = <0>;
 869		compatible = "ti,divider-clock";
 870		clock-output-names = "hsi_fclk";
 871		clocks = <&dpll_per_m2x2_ck>;
 872		ti,bit-shift = <24>;
 873		ti,max-div = <2>;
 874		reg = <0x1638>;
 875	};
 876};
 877
 878&cm_core_clockdomains {
 879	l3init_clkdm: l3init_clkdm {
 880		compatible = "ti,clockdomain";
 881		clock-output-names = "l3init_clkdm";
 882		clocks = <&dpll_usb_ck>;
 883	};
 884};
 885
 886&scrm_clocks {
 887	auxclk0_src_gate_ck: auxclk0_src_gate_ck@310 {
 888		#clock-cells = <0>;
 889		compatible = "ti,composite-no-wait-gate-clock";
 890		clock-output-names = "auxclk0_src_gate_ck";
 891		clocks = <&dpll_core_m3x2_ck>;
 892		ti,bit-shift = <8>;
 893		reg = <0x0310>;
 894	};
 895
 896	auxclk0_src_mux_ck: auxclk0_src_mux_ck@310 {
 897		#clock-cells = <0>;
 898		compatible = "ti,composite-mux-clock";
 899		clock-output-names = "auxclk0_src_mux_ck";
 900		clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
 901		ti,bit-shift = <1>;
 902		reg = <0x0310>;
 903	};
 904
 905	auxclk0_src_ck: auxclk0_src_ck {
 906		#clock-cells = <0>;
 907		compatible = "ti,composite-clock";
 908		clock-output-names = "auxclk0_src_ck";
 909		clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>;
 910	};
 911
 912	auxclk0_ck: auxclk0_ck@310 {
 913		#clock-cells = <0>;
 914		compatible = "ti,divider-clock";
 915		clock-output-names = "auxclk0_ck";
 916		clocks = <&auxclk0_src_ck>;
 917		ti,bit-shift = <16>;
 918		ti,max-div = <16>;
 919		reg = <0x0310>;
 920	};
 921
 922	auxclk1_src_gate_ck: auxclk1_src_gate_ck@314 {
 923		#clock-cells = <0>;
 924		compatible = "ti,composite-no-wait-gate-clock";
 925		clock-output-names = "auxclk1_src_gate_ck";
 926		clocks = <&dpll_core_m3x2_ck>;
 927		ti,bit-shift = <8>;
 928		reg = <0x0314>;
 929	};
 930
 931	auxclk1_src_mux_ck: auxclk1_src_mux_ck@314 {
 932		#clock-cells = <0>;
 933		compatible = "ti,composite-mux-clock";
 934		clock-output-names = "auxclk1_src_mux_ck";
 935		clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
 936		ti,bit-shift = <1>;
 937		reg = <0x0314>;
 938	};
 939
 940	auxclk1_src_ck: auxclk1_src_ck {
 941		#clock-cells = <0>;
 942		compatible = "ti,composite-clock";
 943		clock-output-names = "auxclk1_src_ck";
 944		clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>;
 945	};
 946
 947	auxclk1_ck: auxclk1_ck@314 {
 948		#clock-cells = <0>;
 949		compatible = "ti,divider-clock";
 950		clock-output-names = "auxclk1_ck";
 951		clocks = <&auxclk1_src_ck>;
 952		ti,bit-shift = <16>;
 953		ti,max-div = <16>;
 954		reg = <0x0314>;
 955	};
 956
 957	auxclk2_src_gate_ck: auxclk2_src_gate_ck@318 {
 958		#clock-cells = <0>;
 959		compatible = "ti,composite-no-wait-gate-clock";
 960		clock-output-names = "auxclk2_src_gate_ck";
 961		clocks = <&dpll_core_m3x2_ck>;
 962		ti,bit-shift = <8>;
 963		reg = <0x0318>;
 964	};
 965
 966	auxclk2_src_mux_ck: auxclk2_src_mux_ck@318 {
 967		#clock-cells = <0>;
 968		compatible = "ti,composite-mux-clock";
 969		clock-output-names = "auxclk2_src_mux_ck";
 970		clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
 971		ti,bit-shift = <1>;
 972		reg = <0x0318>;
 973	};
 974
 975	auxclk2_src_ck: auxclk2_src_ck {
 976		#clock-cells = <0>;
 977		compatible = "ti,composite-clock";
 978		clock-output-names = "auxclk2_src_ck";
 979		clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>;
 980	};
 981
 982	auxclk2_ck: auxclk2_ck@318 {
 983		#clock-cells = <0>;
 984		compatible = "ti,divider-clock";
 985		clock-output-names = "auxclk2_ck";
 986		clocks = <&auxclk2_src_ck>;
 987		ti,bit-shift = <16>;
 988		ti,max-div = <16>;
 989		reg = <0x0318>;
 990	};
 991
 992	auxclk3_src_gate_ck: auxclk3_src_gate_ck@31c {
 993		#clock-cells = <0>;
 994		compatible = "ti,composite-no-wait-gate-clock";
 995		clock-output-names = "auxclk3_src_gate_ck";
 996		clocks = <&dpll_core_m3x2_ck>;
 997		ti,bit-shift = <8>;
 998		reg = <0x031c>;
 999	};
1000
1001	auxclk3_src_mux_ck: auxclk3_src_mux_ck@31c {
1002		#clock-cells = <0>;
1003		compatible = "ti,composite-mux-clock";
1004		clock-output-names = "auxclk3_src_mux_ck";
1005		clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
1006		ti,bit-shift = <1>;
1007		reg = <0x031c>;
1008	};
1009
1010	auxclk3_src_ck: auxclk3_src_ck {
1011		#clock-cells = <0>;
1012		compatible = "ti,composite-clock";
1013		clock-output-names = "auxclk3_src_ck";
1014		clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>;
1015	};
1016
1017	auxclk3_ck: auxclk3_ck@31c {
1018		#clock-cells = <0>;
1019		compatible = "ti,divider-clock";
1020		clock-output-names = "auxclk3_ck";
1021		clocks = <&auxclk3_src_ck>;
1022		ti,bit-shift = <16>;
1023		ti,max-div = <16>;
1024		reg = <0x031c>;
1025	};
1026
1027	auxclk4_src_gate_ck: auxclk4_src_gate_ck@320 {
1028		#clock-cells = <0>;
1029		compatible = "ti,composite-no-wait-gate-clock";
1030		clock-output-names = "auxclk4_src_gate_ck";
1031		clocks = <&dpll_core_m3x2_ck>;
1032		ti,bit-shift = <8>;
1033		reg = <0x0320>;
1034	};
1035
1036	auxclk4_src_mux_ck: auxclk4_src_mux_ck@320 {
1037		#clock-cells = <0>;
1038		compatible = "ti,composite-mux-clock";
1039		clock-output-names = "auxclk4_src_mux_ck";
1040		clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
1041		ti,bit-shift = <1>;
1042		reg = <0x0320>;
1043	};
1044
1045	auxclk4_src_ck: auxclk4_src_ck {
1046		#clock-cells = <0>;
1047		compatible = "ti,composite-clock";
1048		clock-output-names = "auxclk4_src_ck";
1049		clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>;
1050	};
1051
1052	auxclk4_ck: auxclk4_ck@320 {
1053		#clock-cells = <0>;
1054		compatible = "ti,divider-clock";
1055		clock-output-names = "auxclk4_ck";
1056		clocks = <&auxclk4_src_ck>;
1057		ti,bit-shift = <16>;
1058		ti,max-div = <16>;
1059		reg = <0x0320>;
1060	};
1061
1062	auxclkreq0_ck: auxclkreq0_ck@210 {
1063		#clock-cells = <0>;
1064		compatible = "ti,mux-clock";
1065		clock-output-names = "auxclkreq0_ck";
1066		clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
1067		ti,bit-shift = <2>;
1068		reg = <0x0210>;
1069	};
1070
1071	auxclkreq1_ck: auxclkreq1_ck@214 {
1072		#clock-cells = <0>;
1073		compatible = "ti,mux-clock";
1074		clock-output-names = "auxclkreq1_ck";
1075		clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
1076		ti,bit-shift = <2>;
1077		reg = <0x0214>;
1078	};
1079
1080	auxclkreq2_ck: auxclkreq2_ck@218 {
1081		#clock-cells = <0>;
1082		compatible = "ti,mux-clock";
1083		clock-output-names = "auxclkreq2_ck";
1084		clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
1085		ti,bit-shift = <2>;
1086		reg = <0x0218>;
1087	};
1088
1089	auxclkreq3_ck: auxclkreq3_ck@21c {
1090		#clock-cells = <0>;
1091		compatible = "ti,mux-clock";
1092		clock-output-names = "auxclkreq3_ck";
1093		clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
1094		ti,bit-shift = <2>;
1095		reg = <0x021c>;
1096	};
1097};
1098
1099&cm_core_aon {
1100	mpu_cm: mpu_cm@300 {
1101		compatible = "ti,omap4-cm";
1102		clock-output-names = "mpu_cm";
1103		reg = <0x300 0x100>;
1104		#address-cells = <1>;
1105		#size-cells = <1>;
1106		ranges = <0 0x300 0x100>;
1107
1108		mpu_clkctrl: clk@20 {
1109			compatible = "ti,clkctrl";
1110			clock-output-names = "mpu_clkctrl";
1111			reg = <0x20 0x4>;
1112			#clock-cells = <2>;
1113		};
1114	};
1115
1116	dsp_cm: dsp_cm@400 {
1117		compatible = "ti,omap4-cm";
1118		clock-output-names = "dsp_cm";
1119		reg = <0x400 0x100>;
1120		#address-cells = <1>;
1121		#size-cells = <1>;
1122		ranges = <0 0x400 0x100>;
1123
1124		dsp_clkctrl: clk@20 {
1125			compatible = "ti,clkctrl";
1126			clock-output-names = "dsp_clkctrl";
1127			reg = <0x20 0x4>;
1128			#clock-cells = <2>;
1129		};
1130	};
1131
1132	abe_cm: abe_cm@500 {
1133		compatible = "ti,omap4-cm";
1134		clock-output-names = "abe_cm";
1135		reg = <0x500 0x100>;
1136		#address-cells = <1>;
1137		#size-cells = <1>;
1138		ranges = <0 0x500 0x100>;
1139
1140		abe_clkctrl: clk@20 {
1141			compatible = "ti,clkctrl";
1142			clock-output-names = "abe_clkctrl";
1143			reg = <0x20 0x64>;
1144			#clock-cells = <2>;
1145		};
1146	};
1147
1148};
1149
1150&cm_core {
1151	l3main1_cm: l3main1_cm@700 {
1152		compatible = "ti,omap4-cm";
1153		clock-output-names = "l3main1_cm";
1154		reg = <0x700 0x100>;
1155		#address-cells = <1>;
1156		#size-cells = <1>;
1157		ranges = <0 0x700 0x100>;
1158
1159		l3main1_clkctrl: clk@20 {
1160			compatible = "ti,clkctrl";
1161			clock-output-names = "l3main1_clkctrl";
1162			reg = <0x20 0x4>;
1163			#clock-cells = <2>;
1164		};
1165	};
1166
1167	l3main2_cm: l3main2_cm@800 {
1168		compatible = "ti,omap4-cm";
1169		clock-output-names = "l3main2_cm";
1170		reg = <0x800 0x100>;
1171		#address-cells = <1>;
1172		#size-cells = <1>;
1173		ranges = <0 0x800 0x100>;
1174
1175		l3main2_clkctrl: clk@20 {
1176			compatible = "ti,clkctrl";
1177			clock-output-names = "l3main2_clkctrl";
1178			reg = <0x20 0x4>;
1179			#clock-cells = <2>;
1180		};
1181	};
1182
1183	ipu_cm: ipu_cm@900 {
1184		compatible = "ti,omap4-cm";
1185		clock-output-names = "ipu_cm";
1186		reg = <0x900 0x100>;
1187		#address-cells = <1>;
1188		#size-cells = <1>;
1189		ranges = <0 0x900 0x100>;
1190
1191		ipu_clkctrl: clk@20 {
1192			compatible = "ti,clkctrl";
1193			clock-output-names = "ipu_clkctrl";
1194			reg = <0x20 0x4>;
1195			#clock-cells = <2>;
1196		};
1197	};
1198
1199	dma_cm: dma_cm@a00 {
1200		compatible = "ti,omap4-cm";
1201		clock-output-names = "dma_cm";
1202		reg = <0xa00 0x100>;
1203		#address-cells = <1>;
1204		#size-cells = <1>;
1205		ranges = <0 0xa00 0x100>;
1206
1207		dma_clkctrl: clk@20 {
1208			compatible = "ti,clkctrl";
1209			clock-output-names = "dma_clkctrl";
1210			reg = <0x20 0x4>;
1211			#clock-cells = <2>;
1212		};
1213	};
1214
1215	emif_cm: emif_cm@b00 {
1216		compatible = "ti,omap4-cm";
1217		clock-output-names = "emif_cm";
1218		reg = <0xb00 0x100>;
1219		#address-cells = <1>;
1220		#size-cells = <1>;
1221		ranges = <0 0xb00 0x100>;
1222
1223		emif_clkctrl: clk@20 {
1224			compatible = "ti,clkctrl";
1225			clock-output-names = "emif_clkctrl";
1226			reg = <0x20 0x1c>;
1227			#clock-cells = <2>;
1228		};
1229	};
1230
1231	l4cfg_cm: l4cfg_cm@d00 {
1232		compatible = "ti,omap4-cm";
1233		clock-output-names = "l4cfg_cm";
1234		reg = <0xd00 0x100>;
1235		#address-cells = <1>;
1236		#size-cells = <1>;
1237		ranges = <0 0xd00 0x100>;
1238
1239		l4cfg_clkctrl: clk@20 {
1240			compatible = "ti,clkctrl";
1241			clock-output-names = "l4cfg_clkctrl";
1242			reg = <0x20 0x14>;
1243			#clock-cells = <2>;
1244		};
1245	};
1246
1247	l3instr_cm: l3instr_cm@e00 {
1248		compatible = "ti,omap4-cm";
1249		clock-output-names = "l3instr_cm";
1250		reg = <0xe00 0x100>;
1251		#address-cells = <1>;
1252		#size-cells = <1>;
1253		ranges = <0 0xe00 0x100>;
1254
1255		l3instr_clkctrl: clk@20 {
1256			compatible = "ti,clkctrl";
1257			clock-output-names = "l3instr_clkctrl";
1258			reg = <0x20 0xc>;
1259			#clock-cells = <2>;
1260		};
1261	};
1262
1263	l4per_cm: clock@1000 {
1264		compatible = "ti,omap4-cm";
1265		clock-output-names = "l4per_cm";
1266		reg = <0x1000 0x200>;
1267		#address-cells = <1>;
1268		#size-cells = <1>;
1269		ranges = <0 0x1000 0x200>;
1270
1271		l4per_clkctrl: clock@20 {
1272			compatible = "ti,clkctrl";
1273			clock-output-names = "l4per_clkctrl";
1274			reg = <0x20 0x15c>;
1275			#clock-cells = <2>;
1276		};
1277
1278		l4sec_clkctrl: clock@1a0 {
1279			compatible = "ti,clkctrl";
1280			clock-output-names = "l4sec_clkctrl";
1281			reg = <0x1a0 0x3c>;
1282			#clock-cells = <2>;
1283		};
1284	};
1285
1286	dss_cm: dss_cm@1400 {
1287		compatible = "ti,omap4-cm";
1288		clock-output-names = "dss_cm";
1289		reg = <0x1400 0x100>;
1290		#address-cells = <1>;
1291		#size-cells = <1>;
1292		ranges = <0 0x1400 0x100>;
1293
1294		dss_clkctrl: clk@20 {
1295			compatible = "ti,clkctrl";
1296			clock-output-names = "dss_clkctrl";
1297			reg = <0x20 0x4>;
1298			#clock-cells = <2>;
1299		};
1300	};
1301
1302	gpu_cm: gpu_cm@1500 {
1303		compatible = "ti,omap4-cm";
1304		clock-output-names = "gpu_cm";
1305		reg = <0x1500 0x100>;
1306		#address-cells = <1>;
1307		#size-cells = <1>;
1308		ranges = <0 0x1500 0x100>;
1309
1310		gpu_clkctrl: clk@20 {
1311			compatible = "ti,clkctrl";
1312			clock-output-names = "gpu_clkctrl";
1313			reg = <0x20 0x4>;
1314			#clock-cells = <2>;
1315		};
1316	};
1317
1318	l3init_cm: l3init_cm@1600 {
1319		compatible = "ti,omap4-cm";
1320		clock-output-names = "l3init_cm";
1321		reg = <0x1600 0x100>;
1322		#address-cells = <1>;
1323		#size-cells = <1>;
1324		ranges = <0 0x1600 0x100>;
1325
1326		l3init_clkctrl: clk@20 {
1327			compatible = "ti,clkctrl";
1328			clock-output-names = "l3init_clkctrl";
1329			reg = <0x20 0xd4>;
1330			#clock-cells = <2>;
1331		};
1332	};
1333};
1334
1335&prm {
1336	wkupaon_cm: wkupaon_cm@1900 {
1337		compatible = "ti,omap4-cm";
1338		clock-output-names = "wkupaon_cm";
1339		reg = <0x1900 0x100>;
1340		#address-cells = <1>;
1341		#size-cells = <1>;
1342		ranges = <0 0x1900 0x100>;
1343
1344		wkupaon_clkctrl: clk@20 {
1345			compatible = "ti,clkctrl";
1346			clock-output-names = "wkupaon_clkctrl";
1347			reg = <0x20 0x5c>;
1348			#clock-cells = <2>;
1349		};
1350	};
1351};
1352
1353&scm_wkup_pad_conf_clocks {
1354	fref_xtal_ck: fref_xtal_ck {
1355		#clock-cells = <0>;
1356		compatible = "ti,gate-clock";
1357		clock-output-names = "fref_xtal_ck";
1358		clocks = <&sys_clkin>;
1359		ti,bit-shift = <28>;
1360		reg = <0x14>;
1361	};
1362};