omap36xx.dtsi

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Device Tree Source for OMAP3 SoC
  4 *
  5 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
  6 */
  7
  8#include <dt-bindings/bus/ti-sysc.h>
  9#include <dt-bindings/media/omap3-isp.h>
 10
 11#include "omap3.dtsi"
 12
 13/ {
 14	aliases {
 15		serial3 = &uart4;
 16	};
 17
 18	cpus {
 19		/* OMAP3630/OMAP37xx variants OPP50 to OPP130 and OPP1G */
 20		cpu: cpu@0 {
 21			operating-points-v2 = <&cpu0_opp_table>;
 22
 23			vbb-supply = <&abb_mpu_iva>;
 24			clock-latency = <300000>; /* From omap-cpufreq driver */
 25			#cooling-cells = <2>;
 26		};
 27	};
 28
 29	cpu0_opp_table: opp-table {
 30		compatible = "operating-points-v2-ti-cpu";
 31		syscon = <&scm_conf>;
 32
 33		opp-50-300000000 {
 34			/* OPP50 */
 35			opp-hz = /bits/ 64 <300000000>;
 36			/*
 37			 * we currently only select the max voltage from table
 38			 * Table 4-19 of the DM3730 Data sheet (SPRS685B)
 39			 * Format is:	cpu0-supply:	<target min max>
 40			 *		vbb-supply:	<target min max>
 41			 */
 42			opp-microvolt = <1012500 1012500 1012500>,
 43					 <1012500 1012500 1012500>;
 44			/*
 45			 * first value is silicon revision bit mask
 46			 * second one is "speed binned" bit mask
 47			 */
 48			opp-supported-hw = <0xffffffff 3>;
 49			opp-suspend;
 50		};
 51
 52		opp-100-600000000 {
 53			/* OPP100 */
 54			opp-hz = /bits/ 64 <600000000>;
 55			opp-microvolt = <1200000 1200000 1200000>,
 56					 <1200000 1200000 1200000>;
 57			opp-supported-hw = <0xffffffff 3>;
 58		};
 59
 60		opp-130-800000000 {
 61			/* OPP130 */
 62			opp-hz = /bits/ 64 <800000000>;
 63			opp-microvolt = <1325000 1325000 1325000>,
 64					 <1325000 1325000 1325000>;
 65			opp-supported-hw = <0xffffffff 3>;
 66		};
 67
 68		opp-1000000000 {
 69			/* OPP1G */
 70			opp-hz = /bits/ 64 <1000000000>;
 71			opp-microvolt = <1375000 1375000 1375000>,
 72					 <1375000 1375000 1375000>;
 73			/* only on am/dm37x with speed-binned bit set */
 74			opp-supported-hw = <0xffffffff 2>;
 75			turbo-mode;
 76		};
 77	};
 78
 79	opp_supply_mpu_iva: opp-supply {
 80		compatible = "ti,omap-opp-supply";
 81		ti,absolute-max-voltage-uv = <1375000>;
 82	};
 83
 84	ocp@68000000 {
 85		uart4: serial@49042000 {
 86			compatible = "ti,omap3-uart";
 87			reg = <0x49042000 0x400>;
 88			interrupts = <80>;
 89			dmas = <&sdma 81 &sdma 82>;
 90			dma-names = "tx", "rx";
 91			ti,hwmods = "uart4";
 92			clock-frequency = <48000000>;
 93		};
 94
 95		abb_mpu_iva: regulator-abb-mpu {
 96			compatible = "ti,abb-v1";
 97			regulator-name = "abb_mpu_iva";
 98			#address-cells = <0>;
 99			#size-cells = <0>;
100			reg = <0x483072f0 0x8>, <0x48306818 0x4>;
101			reg-names = "base-address", "int-address";
102			ti,tranxdone-status-mask = <0x4000000>;
103			clocks = <&sys_ck>;
104			ti,settling-time = <30>;
105			ti,clock-cycles = <8>;
106			ti,abb_info = <
107			/*uV		ABB	efuse	rbb_m	fbb_m	vset_m*/
108			1012500		0	0	0	0	0
109			1200000		0	0	0	0	0
110			1325000		0	0	0	0	0
111			1375000		1	0	0	0	0
112			>;
113		};
114
115		omap3_pmx_core2: pinmux@480025a0 {
116			compatible = "ti,omap3-padconf", "pinctrl-single";
117			reg = <0x480025a0 0x5c>;
118			#address-cells = <1>;
119			#size-cells = <0>;
120			#pinctrl-cells = <1>;
121			#interrupt-cells = <1>;
122			interrupt-controller;
123			pinctrl-single,register-width = <16>;
124			pinctrl-single,function-mask = <0xff1f>;
125		};
126
127		isp: isp@480bc000 {
128			compatible = "ti,omap3-isp";
129			reg = <0x480bc000 0x12fc
130			       0x480bd800 0x0600>;
131			interrupts = <24>;
132			iommus = <&mmu_isp>;
133			syscon = <&scm_conf 0x2f0>;
134			ti,phy-type = <OMAP3ISP_PHY_TYPE_CSIPHY>;
135			#clock-cells = <1>;
136			ports {
137				#address-cells = <1>;
138				#size-cells = <0>;
139			};
140		};
141
142		bandgap: bandgap@48002524 {
143			reg = <0x48002524 0x4>;
144			compatible = "ti,omap36xx-bandgap";
145			#thermal-sensor-cells = <0>;
146		};
147
148		target-module@480cb000 {
149			compatible = "ti,sysc-omap3630-sr", "ti,sysc";
150			ti,hwmods = "smartreflex_core";
151			reg = <0x480cb038 0x4>;
152			reg-names = "sysc";
153			ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
154			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
155					<SYSC_IDLE_NO>,
156					<SYSC_IDLE_SMART>;
157			clocks = <&sr2_fck>;
158			clock-names = "fck";
159			#address-cells = <1>;
160			#size-cells = <1>;
161			ranges = <0 0x480cb000 0x001000>;
162
163			smartreflex_core: smartreflex@0 {
164				compatible = "ti,omap3-smartreflex-core";
165				reg = <0 0x400>;
166				interrupts = <19>;
167			};
168		};
169
170		target-module@480c9000 {
171			compatible = "ti,sysc-omap3630-sr", "ti,sysc";
172			ti,hwmods = "smartreflex_mpu_iva";
173			reg = <0x480c9038 0x4>;
174			reg-names = "sysc";
175			ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
176			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
177					<SYSC_IDLE_NO>,
178					<SYSC_IDLE_SMART>;
179			clocks = <&sr1_fck>;
180			clock-names = "fck";
181			#address-cells = <1>;
182			#size-cells = <1>;
183			ranges = <0 0x480c9000 0x001000>;
184
185
186			smartreflex_mpu_iva: smartreflex@480c9000 {
187				compatible = "ti,omap3-smartreflex-mpu-iva";
188				reg = <0 0x400>;
189				interrupts = <18>;
190			};
191		};
192
193		/*
194		 * Note that the sysconfig register layout is a subset of the
195		 * "ti,sysc-omap4" type register with just sidle and midle bits
196		 * available while omap34xx has "ti,sysc-omap2" type sysconfig.
197		 */
198		sgx_module: target-module@50000000 {
199			compatible = "ti,sysc-omap4", "ti,sysc";
200			reg = <0x5000fe00 0x4>,
201			      <0x5000fe10 0x4>;
202			reg-names = "rev", "sysc";
203			ti,sysc-midle = <SYSC_IDLE_FORCE>,
204					<SYSC_IDLE_NO>,
205					<SYSC_IDLE_SMART>;
206			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
207					<SYSC_IDLE_NO>,
208					<SYSC_IDLE_SMART>;
209			clocks = <&sgx_fck>, <&sgx_ick>;
210			clock-names = "fck", "ick";
211			#address-cells = <1>;
212			#size-cells = <1>;
213			ranges = <0 0x50000000 0x2000000>;
214
215			gpu@0 {
216				compatible = "ti,omap3630-gpu", "img,powervr-sgx530";
217				reg = <0x0 0x2000000>; /* 32MB */
218				interrupts = <21>;
219			};
220		};
221	};
222
223	thermal_zones: thermal-zones {
224		#include "omap3-cpu-thermal.dtsi"
225	};
226};
227
228&sdma {
229	compatible = "ti,omap3630-sdma", "ti,omap-sdma";
230};
231
232/* OMAP3630 needs dss_96m_fck for VENC */
233&venc {
234	clocks = <&dss_tv_fck>, <&dss_96m_fck>;
235	clock-names = "fck", "tv_dac_clk";
236};
237
238&ssi {
239	status = "okay";
240
241	clocks = <&ssi_ssr_fck>,
242		 <&ssi_sst_fck>,
243		 <&ssi_ick>;
244	clock-names = "ssi_ssr_fck",
245		      "ssi_sst_fck",
246		      "ssi_ick";
247};
248
249&usb_otg_target {
250	clocks = <&hsotgusb_ick_3430es2>;
251};
252
253/include/ "omap34xx-omap36xx-clocks.dtsi"
254/include/ "omap36xx-omap3430es2plus-clocks.dtsi"
255/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
256/include/ "omap36xx-clocks.dtsi"